Semiconductor device and methods of formation
TW202633071APending Publication Date: 2026-08-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
View PDF 0 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-03-19
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TA001070044_001 
Figure TWG2TA001070044_002 
Figure TWG2TA001070044_003
Abstract
Memory cell structures of a memory array are formed using materials and processes that are compatible with complementary metal-oxide-semiconductor (CMOS) integrated circuits that have been formed on a semiconductor device. In particular, the transistor structures of the memory cell structures are formed to include oxide-semiconductor channel layers as opposed to semiconductor channel layers. The oxide-semiconductor channel layers may be formed by lower-temperature processes (e.g., chemical vapor deposition (CVD)) relative to semiconductor channel layers (e.g., epitaxial growth). Thus, the formation of the oxide-semiconductor channel layers is less likely to degrade and / or damage the layers and / or structures of the CMOS integrated circuits of the semiconductor device. In this way, the semiconductor device may be formed monolithically, meaning the memory array may be formed above the device layer of the semiconductor device in which the CMOS integrated circuits were formed.
Need to check novelty before this filing date? Find Prior Art