Semiconductor memory devices

Abstract

An embodiment of the present invention provides a semiconductor memory device capable of achieving high integration. The semiconductor memory device of the embodiment includes a first wafer and a second wafer bonded together via a plurality of bonding electrodes. The first wafer includes a semiconductor substrate. The second wafer includes a plurality of first conductive layers, a plurality of semiconductor layers opposite to the plurality of first conductive layers, a first wiring layer including a plurality of bit lines, a second wiring layer including a plurality of wirings, and a third wiring layer including a plurality of first bonding electrodes. Each of the plurality of wirings in the second wiring layer includes: a first portion disposed in a region overlapping one of the plurality of bit lines when viewed from a first direction, and electrically connected to one of the plurality of bit lines; and a second portion disposed in a region overlapping one of the plurality of first bonding electrodes when viewed from a first direction, and connected to one of the plurality of first bonding electrodes. At least a portion of the wiring has a third portion connected to one end of the first portion in a second direction and to one end of the second portion in a second direction.