Ferroelectric unit fabrication process and structure

Abstract

A ferroelectric neural network cell fabrication process and structure with self-learning capabilities and improved character recognition length are disclosed. The proposed ferroelectric neural network cell is based on a content-addressable memory (CAM) structure (FeCAM) using a ferroelectric field-effect transistor (FeFET). This FeCAM is a 1N1P-FeCAM composed of an N-type FeFET and a P-type FeFET. This invention reduces the number of components to minimize cell area. Each cell is constructed from two complementary FeFETs, achieving a density 33% higher than that of a tertiary content-addressable memory (TCAM). Furthermore, through hydrogen plasma processing, the symmetry of ION1 and ION2 can be better improved, which increases the maximum mismatched cell number (Max HD, MHD). This is extremely helpful for image recognition and can be extended to various fields of artificial intelligence.

Description

Technical Field

[0001] This invention relates to a ferroelectric cell fabrication process and its structure, and more particularly to a process for fabricating ferroelectric cells. The FeCAM structure formed by adopting a 1N1P architecture in the structure, especially through the treatment of hydrogen plasma, can better improve the symmetry of ION1 and ION2, and increase the number of mismatched units (Max HD, MHD). Prior Technology

[0002] Content-addressable memory (CAM) utilizes various... Memory technology enables parallel pattern matching and distance calculation. Ferroelectric field-effect transistors (FeFETs) stand out due to their single transistor structure, non-volatility, and energy efficiency. FeFET-based CAM (FeCAM) designs improve data density through multi-level cell (MLC) implementations or component reduction strategies. Compared to designs based on static random-access memory (SRAM), the classic 2FeFET CAM achieves an 8x increase in density. Despite the appeal of FeFET designs, current asymmetry caused by carrier mobility differences, contact resistance, and parasitic capacitance can lead to fluctuations in the matching current, thus limiting the number of mismatched cells, i.e., the Hamming distance (HD).

[0003] Therefore, the current problems faced by FeCAM in operation and application may include: Limitations on write cycles: One of the characteristics of FeFETs is their ferroelectric nature, but the number of write cycles for ferroelectric materials is limited. Prolonged and frequent write operations can lead to the degradation of ferroelectric materials, limiting the lifespan and reliability of the device. Temperature stability: The performance of FeCAM can be affected by temperature changes, especially in extreme temperature conditions. Under certain conditions, temperature variations may cause instability in the properties of FeCAM, which may require additional compensation measures to ensure stable operation.

[0004] Accordingly, an invention is developed that can solve the existing FeCAM problems and the shortcomings of previous technologies. It is absolutely necessary. Summary of the Invention

[0005] The main objective of this invention is to overcome the aforementioned problems encountered in the prior art and A 1N1P-FeCAM is provided, which is composed of 1N-type ferroelectric field-effect transistors (N-type FeFETs) and 1P-type ferroelectric field-effect transistors (P-type FeFETs). Compared with the sample treated with hydrogen plasma, the treated 1N1P-FeCAM has less trap charge, which makes ION1 and ION2 more symmetrical, and can increase the number of mismatched ferroelectric cells in the process and structure.

[0006] Another object of the present invention is to overcome the aforementioned problems encountered in the prior art and A ferroelectric cell fabrication process and structure are provided that can be used for artificial intelligence image recognition, enabling FeCAM cells to store image features using different Vth values ​​to achieve pattern similarity recognition.

[0007] To achieve the above objectives, the present invention provides a method for preparing ferroelectric units, comprising: A process for fabricating an N-type ferroelectric field-effect transistor includes at least the following steps: cleaning a first silicon substrate; growing an interfacial layer (IL) on the first silicon substrate using atomic layer deposition (ALD); stacking hafnium dioxide / zirconium dioxide (HfO2 / ZrO2) in angstrom-level layers on the interfacial layer using ALD to form a first hafnium zirconium oxide (HZO) structure; and covering the first HZO structure with a first titanium nitride (TiN) layer using physical vapor deposition (PVD) to form a first metal oxide semiconductor field-effect transistor. The first silicon substrate, the interface layer, the first HZO structure, and the first TiN layer are etched and patterned to form a first source / drain region (S / D). The first source / drain region is then doped with a P-type dopant, and an annealing process is performed to activate the dopant in the first source / drain region, thus obtaining an N-type ferroelectric field-effect transistor. The N-type ferroelectric field-effect transistor is then subjected to… Hydrogen plasma treatment, with radio frequency power between 100±20% W, involves a hydrogen (H2) flow rate of 20±20% sccm. The flow rate is introduced and maintained for 400±20% seconds.

[0008] In the above embodiments of the present invention, the method for preparing ferroelectric units further includes a P-type... The process for fabricating a ferroelectric field-effect transistor includes at least the following steps: cleaning a second silicon substrate; using ALD to stack HfO2 / ZrO2 in angstrom-level layers on the second silicon substrate to form a second HZO structure; using PVD to sequentially cover the second HZO structure with a second TiN layer, a molybdenum (Mo) layer, and a third TiN layer to form a second MOSFET structure; and etching and patterning the second silicon substrate, the second HZO structure, the second TiN layer, the molybdenum layer, and the third TiN layer to form a second source / drain region, then doping the second source / drain region with a B-type dopant, and then performing an annealing process to activate the dopant in the second source / drain region to obtain a P-type ferroelectric field-effect transistor.

[0009] In the above embodiments of the present invention, the cleaning system of the first or the second silicon substrate is... RCA Clean's standard process cleaning.

[0010] In the above embodiments of the present invention, the interface layer is aluminum oxide (AlOx) with a thickness of It is 1±20% nm.

[0011] In the above embodiments of the present invention, the thickness of the first or the second HZO structure is The 9±20% nm is formed by cyclically stacking HfO2 and 7Å ZrO2 with each cycle thickness of 7 Å in the ALD.

[0012] In the above embodiments of the present invention, the thickness of the first TiN layer is 50 ± 20% nm.

[0013] In the above embodiments of the present invention, the thickness of the second TiN layer is 2.5 ± 20% nm. The thickness of the molybdenum layer is 30±20% nm, and the thickness of the third TiN layer is 50±20% nm.

[0014] In the above embodiments of the present invention, the first or the second source / drain region is the first Or the doped region in the second silicon substrate.

[0015] In the above embodiments of the present invention, the annealing process includes a temperature of 900±20%°C. Annealing the first or second source / drain region on the first or second silicon substrate for 5 ± 20% seconds to activate the P-type or B-type dopant therein.

[0016] To achieve the above objectives, the present invention further provides a ferroelectric unit comprising: an N-type ferroelectric... A field-effect transistor (FET) includes a first silicon substrate; a first gate stack disposed above the first silicon substrate, the first gate stack including an interface layer, a first HZO structure disposed above the interface layer, and a first TiN layer disposed above the first HZO structure; and a first source / drain region disposed adjacent to both sides of the first gate stack; wherein the N-type ferroelectric field-effect transistor system is a ferroelectric field-effect transistor after hydrogen plasma treatment; and a P-type ferroelectric field-effect transistor includes a second silicon substrate; and a second gate stack disposed above the first silicon substrate. Above the second silicon substrate, the second gate stack includes a second HZO structure, a second TiN layer disposed above the second HZO structure, a molybdenum layer disposed above the second TiN layer, and a third TiN layer disposed above the molybdenum layer; and a second source / drain region disposed adjacent to both sides of the second gate stack; wherein the source regions of the N-type ferroelectric field-effect transistor and the P-type ferroelectric field-effect transistor are coupled to a matching line (ML), and the drain regions of the N-type ferroelectric field-effect transistor and the P-type ferroelectric field-effect transistor are coupled to a ground terminal.

[0017] In the above embodiments of the present invention, the interface layer is aluminum oxide with a thickness of 1±20%. nm.

[0018] In the above embodiments of the present invention, the first and second HZO structures are cyclically stacked. The total thickness is 9 ± 20% nm, formed by combining 7 Å HfO2 and 7 Å ZrO2.

[0019] In the above embodiments of the present invention, the thickness of the first TiN layer is 50 ± 20% nm. The thickness of the second TiN layer is 2.5 ± 20% nm, the thickness of the molybdenum layer is 30 ± 20% nm, and the thickness of the third TiN layer is 50 ± 20% nm.

[0020] In the above embodiments of the present invention, the first source / drain region is located in the first silicon substrate. The P-type doped region, the second source / drain region is the B-type doped region in the second silicon substrate. Simple Explanation of the Diagram

[0021] Figure 1 is a schematic diagram of the structure of the N-type ferroelectric field-effect crystal of the present invention. Figure 2 is a cross-sectional TEM image of the N-type ferroelectric field-effect crystal structure of the present invention. Figure 3 is a schematic diagram of the structure of the P-type ferroelectric field-effect crystal of the present invention. Figure 4 is a circuit diagram of the 1N1P-FeCAM of the present invention. Figure 5 is a schematic diagram of the fabrication process of the N-type ferroelectric field-effect crystal of the present invention. Figure 6 is a schematic diagram of the fabrication process of the P-type ferroelectric field-effect crystal of the present invention. Figure 7 shows the N-type ferroelectric crystal and P-type ferroelectric crystal used in the FeCAM model of this invention. Schematic diagram of ID-VG in crystal. Figure 8 is a schematic diagram illustrating how the present invention forms multiple matching windows at different positions using different bias pulses. . Figure 9 shows the IML-VSL curves of the two 1N1P-FeCAM units written to different states, as measured by this invention. Schematic diagram. Figure 10 is a schematic diagram of the IML-VSL curve of the 1N1P FeCAM of the present invention before hydrogen plasma treatment. Figure 11 is a schematic diagram of the IML-VSL curve of the 1N1P FeCAM of the present invention after hydrogen plasma treatment. Figure 12 shows the IML-VSL curves of the 1N1P FeCAM of this invention at different temperatures before hydrogen plasma treatment. intention. Figure 13 shows the IML-VSL curves of the 1N1P FeCAM of the present invention at different temperatures after hydrogen plasma treatment. intention. Figure 14 is a schematic diagram of the neural network composed of 1T-1FeFET units according to the present invention. Implementation

[0022] Please refer to Figures 1 through 14, which respectively illustrate the N-type ferroelectric field effect of this invention. Schematic diagram of the structure of the transistor; cross-sectional TEM image of the N-type ferroelectric field-effect transistor structure of the present invention; schematic diagram of the structure of the P-type ferroelectric field-effect transistor of the present invention; circuit schematic diagram of the 1N1P-FeCAM of the present invention; schematic diagram of the fabrication process of the N-type ferroelectric field-effect transistor of the present invention; schematic diagram of the fabrication process of the P-type ferroelectric field-effect transistor of the present invention; ID-VG schematic diagram of the N-type and P-type ferroelectric field-effect transistors used in the FeCAM model of the present invention; schematic diagram of the present invention forming multiple matching windows at different positions through different bias pulses; schematic diagram of the present invention measuring the IML-VSL curves of two 1N1P-FeCAM units written to different states; schematic diagram of the IML-VSL curve of the 1N1P FeCAM of the present invention before hydrogen plasma treatment; schematic diagram of the IML-VSL curve of the 1N1P FeCAM of the present invention after hydrogen plasma treatment; schematic diagram of the IML-VSL curves of the 1N1P FeCAM of the present invention at different temperatures before hydrogen plasma treatment; the 1N1P... The figure shows the IML-VSL curves of FeCAM at different temperatures after hydrogen plasma treatment, and the neural network diagram composed of 1T-1FeFET units in this invention. As shown in the figure: This invention is a ferroelectric unit fabrication process and its structure. The proposed ferroelectric unit is a content addressable memory (CAM) structure based on a ferroelectric field-effect transistor (FeFET) (referred to as FeCAM). This FeCAM is a 1N1P-FeCAM composed of an N-type ferroelectric field-effect transistor (N-type FeFET) 1 and a P-type ferroelectric field-effect transistor (P-type FeFET) 2.

[0023] The structure of the aforementioned N-type ferroelectric field-effect crystal 1 is shown in Figure 1, with a cross-section penetrating through. The transmission electron microscope (TEM) image is shown in Figure 2. The N-type ferroelectric field-effect crystal 1 is a ferroelectric field-effect crystal treated with hydrogen plasma, comprising: a first silicon substrate 11; a first gate stack 12 disposed above the first silicon substrate 11, wherein the first gate stack 12 includes an interface layer (IL) 121, a first hafnium zirconium oxide (HZO) structure 122 disposed above the interface layer 121, and a first titanium nitride (TiN) layer 123 disposed above the first HZO structure 122; and a first source / drain region (S / D) 13 disposed adjacent to both sides of the first gate stack 12.

[0024] The structure of the P-type ferroelectric field-effect crystal 2 is shown in Figure 3. The crystal 2 includes: a second silicon substrate 21; a second gate stack 22 disposed above the second silicon substrate 21, wherein the second gate stack 22 includes a second HZO structure 221, a second TiN layer 222 disposed above the second HZO structure 221, a molybdenum (Mo) layer 223 disposed above the second TiN layer 222, and a third TiN layer 224 disposed above the molybdenum layer 223; and a second source / drain region 23 disposed adjacent to both sides of the second gate stack 22.

[0025] The circuit diagram of the 1N1P-FeCAM used in this invention is shown in Figure 4. This N-type ferroelectric field effect... The source regions 13 and 23 of transistor 1 and the P-type ferroelectric transistor 2 are coupled to a matching line (ML) 3, and the drain regions 13 and 23 of N-type ferroelectric transistor 1 and the P-type ferroelectric transistor 2 are coupled to ground terminal 4.

[0026] The fabrication process of the N-type ferroelectric field-effect crystal 1 is shown in Figure 5. Step s11, First, the first silicon substrate 11 is cleaned with RCA Clean. Then, as in step s12, an aluminum oxide (AlOx) interface layer 121 with a thickness of 1 nm is grown on the first silicon substrate 11 using atomic layer deposition (ALD). In step s13, hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) with a thickness of 7 Å per cycle are cyclically stacked on the interface layer 121 to form a first HZO structure 122 with a thickness of 9 nm. Then, as in step s14, a first TiN layer 123 with a thickness of 50 nm is covered on the first HZO structure 122 using physical vapor deposition (PVD) to form a first metal oxide semiconductor field-effect transistor. The first source / drain region 13 is formed by etching and patterning the first silicon substrate 11, the interface layer 121, the first HZO structure 122 and the first TiN layer 123 in step s15 to form the first source / drain region 13. Then, as in step s16, the first source / drain region 13 is doped with P-type dopant. Then, an annealing process is performed to activate the P-type dopant in the first source / drain region 13 at 900°C for 5 seconds. Finally, as in step s17, the obtained N-type ferroelectric field-effect transistor 1 is subjected to hydrogen plasma treatment. Hydrogen gas (H2) is introduced at a flow rate of 20 sccm and the treatment is continued for 400 seconds with a radio frequency power of 100 W.

[0027] The fabrication process of the P-type ferroelectric field-effect crystal 2 is shown in Figure 6. Step s21, first... The second silicon substrate 21 was cleaned with RCA Clean, and then, as in step s22, ALD was applied to the second silicon substrate 21. HfO2 with a thickness of 7 Å and ZrO2 with a thickness of 7 Å are stacked in cycles to form the second HZO structure 221 with a thickness of 9 nm. Then, as in step s23, a second TiN layer 222 with a thickness of 2.5 nm, a molybdenum layer 223 with a thickness of 30 nm, and a third TiN layer 224 with a thickness of 50 nm are sequentially deposited on the second HZO structure 221 using PVD to form a second MOSFET structure. Then, as in step s24, the second silicon substrate 21, the second HZO structure 221, the second TiN layer 222, the molybdenum layer 223, and the third TiN layer 224 are etched and patterned to form a second source / drain region 23. Next, as in step s25, the second source / drain region 23 is doped with B-type dopants, and then an annealing process is performed to activate the dopants in the second source / drain region 23 at 900°C for 5 seconds, resulting in a P-type ferroelectric field-effect transistor 2.

[0028] In the middle of Figure 7 is the circuit diagram of the experimental FeCAM model, and on the left is the experimental FeCAM The ID-VG graph of the N-type ferroelectric field-effect transistor 1 used in the model. The dashed line is without hydrogen plasma treatment, and the solid line is after hydrogen plasma treatment. On the right is the ID-VG graph of the P-type ferroelectric field-effect transistor 2 used in the experimental FeCAM model. As can be seen from the results, after hydrogen plasma treatment, the ratio of ION to IOFF can reach 8 orders of magnitude.

[0029] Figure 8 shows the measured electrical performance of 1N1P-FeCAM. By applying different pulses to change the position of the matching window, 6 different matching windows are obtained. Figure 9 shows the IML-VSL curves of two 1N1P-FeCAM cells written in different states. When IML < IREF, it represents a match, and vice versa, it is a mismatch.

[0030] Figures 10 and 11 show the measurement results of IML-VSL before and after hydrogen plasma treatment at different temperatures (Memory Window, MW = 1V). The IML and VSL curves of FeCAM before and after hydrogen plasma treatment show that after repairing the defects, ION1 and ION2 become more symmetric. According to the formula , this can increase the number of mismatched cells (Max HD, MHD).

[0031] As can be seen from the room temperature (25°C) and 145°C in Figures 12 and 13, as the temperature increases, ION1 and ION2 become more asymmetric, which can be attributed to the difference in mobility between N / P MOS. In contrast, FeCAM treated with hydrogen plasma exhibits better heat resistance with a smaller degree of change.

[0032] Figure 14 illustrates training through different animal patterns (cat, sheep, deer, dog) to... FeCAM units store animal characteristics using different critical voltages (Vth) to achieve pattern similarity recognition.

[0033] As shown in Table 1, the structure of this invention is 1N1P-FeCAM, not 2N-FeCAM, MW It can reach 2.1 V, and the Ion to Ioff ratio can reach 8 orders of magnitude, with endurance of [missing value]. It achieved 1011 cycles with an accuracy of 91.1%. Table 1 [1] [2] [3] [4] [5] This invention CAM unit 2nFeFET 1nFeFET + 1pFeFET 2nFeFET 1T-1FET - 1nFeFET + 1pFeFET MW(V) 1.2 1.5 1 0.4 2 2.1 Endurance 104 - 1010 108 105 1011 ION / IOFF (Order of magnitude) - 5 4 4 4 8 Accuracy (%) - 90 - 91 91 91.1 dielectric layer SiO2 SiO2 SiO2 SiO2 SiO2 AlOx Channel type Si Si Si IWO IGZO Si

[0034] This invention uses 1N-type FeFET and 1P-type FeFET to form a 1N1P-FeCAM. Compared to samples treated with hydrogen plasma, the treated 1N1P-FeCAM exhibits less trap charge, resulting in more symmetrical ION1 and ION2, which can increase the number of mismatched units. Therefore, in applications, this invention can be used for artificial intelligence image recognition, enabling FeCAM units to store image features using different Vth values ​​to achieve pattern similarity recognition.

[0035] In terms of novelty, this invention differs from traditional three-state addressable memory. (Ternary content addressable memory, TCAM) and 2N-FeCAM. This invention is formed by adopting a 1N1P architecture in its structure and can be used in various fields of artificial intelligence.

[0036] In terms of advancement, this invention differs from traditional TCAM and 2N-FeCAM. This invention... The structure employs a 1N1P architecture, reducing the number of components to minimize cell area (compared to designs based on Static Random-Access Memory (SRAM), the classic 2FeFET CAM achieves an 8x increase in density). Each cell is constructed from two complementary FeFETs, resulting in an expected 33% higher density than TCAM. Through hydrogen plasma processing, the symmetry between ION1 and ION2 can be further enhanced, increasing the number of mismatched cells. This is extremely helpful for image recognition and can be extended to various fields of artificial intelligence.

[0037] In summary, this invention relates to a ferroelectric unit fabrication process and its structure, which can effectively improve... Overcoming the shortcomings of conventional designs, the 1N1P architecture reduces the number of components and minimizes cell area. Each cell is constructed from two complementary FeFETs, achieving a density 33% higher than TCAM. Through hydrogen plasma processing, the symmetry between ION1 and ION2 is further enhanced, increasing the number of mismatched cells. This greatly aids in image recognition and can be extended to various fields of artificial intelligence. Therefore, this invention is more advanced, practical, and meets user needs, thus fulfilling the requirements for an invention patent application. Therefore, this patent application is filed in accordance with the law.

[0038] However, the above description is merely a preferred embodiment of the present invention and should not be construed as limiting it. The scope of this invention; therefore, any simplifications made in accordance with the scope of the patent application and the contents of the invention specification are hereby excluded. All equivalent changes and modifications to the single element should still fall within the scope of this invention patent.

[0039] 1: N-type ferroelectric field-effect transistor 11: First silicon substrate 12: First gate stack 121: Interface Layer 122: First HZO structure 123: First TiN layer 13: First source / drain region 2: P-type ferroelectric field-effect transistor 21: Second silicon substrate 22: Second gate stack 221: Second HZO structure 222: Second TiN layer 223: Molybdenum layer 224: Third TiN layer 23: Second source / drain region 3: Matching line 4: Grounding terminal s11~s17: Steps s21~s25: Steps

Claims

1. A method for fabricating a ferroelectric cell, comprising an N-type ferroelectric field-effect transistor (FeFET) process, comprising at least the following steps: cleaning a first silicon substrate; growing an interfacial layer (IL) on the first silicon substrate using atomic layer deposition (ALD); stacking hafnium dioxide / zirconium dioxide (HfO2 / ZrO2) in angstrom-level layers on the interfacial layer using the ALD to form a first hafnium zirconium oxide (HZO) structure; covering the first HZO structure with a first titanium nitride (TiN) layer using physical vapor deposition (PVD) to form a first metal oxide semiconductor field-effect transistor (MOSFET) structure; The first silicon substrate, the interface layer, the first HZO structure, and the first TiN layer are etched and patterned to form a first source / drain region (S / D). Then, the first source / drain region is doped with a P-type dopant. An annealing process is then performed to activate the dopant in the first source / drain region to obtain an N-type ferroelectric field-effect transistor. The N-type ferroelectric field-effect transistor is then subjected to hydrogen plasma treatment. Hydrogen gas (H2) is introduced at a flow rate of 20±20% sccm for 400±20% seconds when the radio frequency power is between 100±20% W.

2. The method for fabricating a ferroelectric unit according to claim 1 further includes a P-type ferroelectric field-effect transistor (P-type FeFET) fabrication process comprising at least the following steps: cleaning a second silicon substrate; using ALD to stack HfO2 / ZrO2 in angstrom-level layers on the second silicon substrate to form a second HZO structure; using PVD to sequentially cover the second HZO structure with a second TiN layer, a molybdenum (Mo) layer and a third TiN layer to form a second MOSFET structure; and etching and patterning the second silicon substrate, the second HZO structure, the second TiN layer, the molybdenum layer and the third TiN layer to form a second source / drain region, then doping the second source / drain region with a B-type dopant, and then performing an annealing process to activate the dopant in the second source / drain region to obtain a P-type ferroelectric field-effect transistor.

3. The method for preparing ferroelectric units according to claim 2, wherein, The first or second silicon substrate was cleaned using RCA Clean's standard process.

4. The method for preparing ferroelectric units according to claim 1, wherein, The interface layer is aluminum oxide (AlOx) with a thickness of 1 ± 20% nm.

5. The method for preparing ferroelectric units according to claim 2, wherein, The thickness of the first or second HZO structure is 9±20% nm, which is formed by cyclically stacking HfO2 and 7Å ZrO2 with a thickness of 7 Å for each cycle of the ALD.

6. The method for preparing ferroelectric units according to claim 1, wherein, The thickness of the first TiN layer is 50 ± 20% nm.

7. The method for preparing a ferroelectric unit as described in claim 2, wherein, The thickness of the second TiN layer is 2.5 ± 20% nm, the thickness of the molybdenum layer is 30 ± 20% nm, and the thickness of the third TiN layer is 50 ± 20% nm.

8. The method for preparing ferroelectric units according to claim 2, wherein, The first or second source / drain region is a doped region in the first or second silicon substrate.

9. The method for preparing a ferroelectric unit according to claim 2, wherein, The annealing process includes annealing the first or second source / drain region on the first or second silicon substrate at a temperature of 900±20%°C for 5±20% seconds to activate the P-type or B-type dopant therein.

10. A ferroelectric unit comprising: An N-type ferroelectric field-effect transistor, comprising a first silicon substrate; A first gate stack is disposed above the first silicon substrate. The first gate stack includes an interface layer, a first HZO structure disposed above the interface layer, and a first TiN layer disposed above the first HZO structure; and a first source / drain region disposed adjacent to both sides of the first gate stack; wherein the N-type ferroelectric field-effect transistor system is a ferroelectric field-effect transistor treated with hydrogen plasma. The N-type ferroelectric field-effect transistor includes a second silicon substrate; a second gate stack disposed above the second silicon substrate, the second gate stack including a second HZO structure, a second TiN layer disposed above the second HZO structure, a molybdenum layer disposed above the second TiN layer, and a third TiN layer disposed above the molybdenum layer; and a second source / drain region disposed adjacent to both sides of the second gate stack; wherein the source regions of the N-type ferroelectric field-effect transistor and the P-type ferroelectric field-effect transistor are coupled to a matching line (ML), and the drain regions of the N-type ferroelectric field-effect transistor and the P-type ferroelectric field-effect transistor are coupled to a ground terminal.

11. The ferroelectric unit as described in claim 10, wherein, The interface layer is made of aluminum oxide and has a thickness of 1 ± 20% nm.

12. The ferroelectric unit as described in claim 10, wherein, The first and second HZO structures are formed by cyclically stacking 7 Å of HfO2 and 7 Å of ZrO2 to create a total thickness of 9 ± 20% nm.

13. The ferroelectric unit as described in claim 10, wherein, The thickness of the first TiN layer is 50±20% nm, the thickness of the second TiN layer is 2.5±20% nm, the thickness of the molybdenum layer is 30±20% nm, and the thickness of the third TiN layer is 50±20% nm.

14. The ferroelectric unit as described in claim 10, wherein, The first source / drain region is a P-type doped region in the first silicon substrate, and the second source / drain region is a B-type doped region in the second silicon substrate.

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