Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure including a substrate, a first electrode, a first support layer, a high dielectric constant (high-k) dielectric layer, a low dielectric constant (low-k) dielectric layer, and a second electrode is provided. The first electrode is located on the substrate. The first electrode is pillar-shaped. The first support layer is located on the sidewall of the first electrode. The high-k dielectric layer is located on the first electrode and the first support layer. The low-k dielectric layer is located between the first support layer and the high-k dielectric layer and between the first electrode and the high-k dielectric layer. The second electrode is located on the high-k dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure having a low dielectric constant dielectric layer and a method for manufacturing the same. Prior Technology

[0002] Capacitors are semiconductor components widely used in electronic products. However, as capacitor sizes continue to shrink, effectively preventing leakage current remains a persistent goal. Summary of the Invention

[0003] This invention provides a semiconductor structure that can effectively prevent leakage current in capacitors.

[0004] This invention proposes a semiconductor structure including a substrate, a first electrode, a first support layer, a high-dielectric-constant dielectric layer, a low-dielectric-constant dielectric layer, and a second electrode. The first electrode is located on the substrate and is columnar. The first support layer is located on the sidewall of the first electrode. The high-dielectric-constant dielectric layer is located on the first electrode and the first support layer. The low-dielectric-constant dielectric layer is located between the first support layer and the high-dielectric-constant dielectric layer, and between the first electrode and the high-dielectric-constant dielectric layer. The second electrode is located on the high-dielectric-constant dielectric layer.

[0005] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a first electrode on the substrate. The first electrode is columnar. Forming a first support layer on the sidewalls of the first electrode. Forming a low-dielectric-constant dielectric layer on the first electrode and the first support layer. Forming a high-dielectric-constant dielectric layer on the low-dielectric-constant dielectric layer. The low-dielectric-constant dielectric layer is located between the first support layer and the high-dielectric-constant dielectric layer, and between the first electrode and the high-dielectric-constant dielectric layer. Forming a second electrode on the high-dielectric-constant dielectric layer.

[0006] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, a capacitor can be formed from a first electrode, a low-dielectric-constant dielectric layer, a high-dielectric-constant dielectric layer, and a second electrode. Furthermore, the low-dielectric-constant dielectric layer is located between the first support layer and the high-dielectric-constant dielectric layer, and between the first electrode and the high-dielectric-constant dielectric layer. Therefore, even if the capacitor bends, leakage current can be effectively prevented by the low-dielectric-constant dielectric layer. In addition, the low-dielectric-constant dielectric layer can be used to avoid leakage current caused by electron accumulation in the high-dielectric-constant dielectric layer. Furthermore, the low-dielectric-constant dielectric layer can reduce parasitic capacitance near the first support layer.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figures 1A to 1E are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Implementation

[0009] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0010] Figures 1A to 1E are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention.

[0011] Referring to Figure 1A, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, although not shown in the figure, depending on the type of semiconductor structure, corresponding components may be present on and / or in the substrate 100. For example, the substrate 100 may have necessary components (not shown), such as isolation structures, doped regions, and / or buried word lines, and the substrate 100 may have necessary components (not shown), such as dielectric layers and / or interconnect structures (e.g., bit lines and contact windows), which are omitted here.

[0012] Next, an electrode 102 is formed on the substrate 100. The electrode 102 is columnar. In some embodiments, the cross-sectional shape of the electrode 102 may be U-shaped. In some embodiments, the material of the electrode 102 is, for example, titanium nitride (TiN). In this embodiment, the number of electrodes 102 is exemplified by multiple electrodes, but the present invention is not limited thereto. As long as the number of electrodes 102 is at least one, it falls within the scope of the present invention.

[0013] A support layer 104 is formed on the sidewall SW1 of electrode 102. In some embodiments, the material of the support layer 104 is, for example, a nitride (e.g., silicon nitride). In some embodiments, a support layer 106 may be formed on the sidewall SW1 of electrode 102. The support layer 106 may be located directly above the support layer 104. In some embodiments, the material of the support layer 106 is, for example, a nitride (e.g., silicon nitride).

[0014] Referring to Figure 1B, a low-dielectric-constant dielectric layer 108 is formed on the electrode 102 and the support layer 104. In some embodiments, the low-dielectric-constant dielectric layer 108 may be formed on the support layer 106. In some embodiments, the dielectric constant of the low-dielectric-constant dielectric layer 108 may be 3 to 4. In some embodiments, the material of the low-dielectric-constant dielectric layer 108 is, for example, silicon carbide (SiCO). In some embodiments, the method for forming the low-dielectric-constant dielectric layer 108 is, for example, atomic layer deposition (ALD).

[0015] In some embodiments, the thickness T1 of the portion of the low-dielectric-constant dielectric layer 108 located on the support layer 104 can be greater than the thickness T2 of the portion of the low-dielectric-constant dielectric layer 108 located on the electrode 102. That is, the portion of the low-dielectric-constant dielectric layer 108 located on the electrode 102 can have a smaller thickness (e.g., thickness T2), thus the dielectric layer 108 has little effect on the capacitance of the capacitor (e.g., capacitor C1 in FIG. 1C). In some embodiments, the thickness T2 of the portion of the low-dielectric-constant dielectric layer 108 located on the electrode 102 can be 72% to 88% of the thickness T1 of the portion of the low-dielectric-constant dielectric layer 108 located on the support layer 104.

[0016] In some embodiments, the thickness T3 of the portion of the low-dielectric-constant dielectric layer 108 located on the support layer 106 may be greater than the thickness T2 of the portion of the low-dielectric-constant dielectric layer 108 located on the electrode 102. In some embodiments, the thickness T2 of the portion of the low-dielectric-constant dielectric layer 108 located on the electrode 102 may be 72% to 88% of the thickness T3 of the portion of the low-dielectric-constant dielectric layer 108 located on the support layer 106.

[0017] Next, a high-dielectric-constant dielectric layer 110 is formed on the low-dielectric-constant dielectric layer 108. The low-dielectric-constant dielectric layer 108 is located between the support layer 104 and the high-dielectric-constant dielectric layer 110, and between the electrode 102 and the high-dielectric-constant dielectric layer 110. In some embodiments, the low-dielectric-constant dielectric layer 108 may be located between the support layer 106 and the high-dielectric-constant dielectric layer 110. In some embodiments, the dielectric constant of the high-dielectric-constant dielectric layer 110 may be 20 to 40. In some embodiments, the material of the high-dielectric-constant dielectric layer 110 is, for example, zirconium oxide (ZrO), aluminum oxide (AlO), or a combination thereof.

[0018] Referring to Figure 1C, an electrode 112, a conductive layer 116, and a conductive layer 118 are formed on a high-dielectric-constant dielectric layer 110. In some embodiments, a capacitor C1 can be formed by an electrode 102, a low-dielectric-constant dielectric layer 108, a high-dielectric-constant dielectric layer 110, and an electrode 112. The electrode 112 can be a single-layer structure or a multi-layer structure. In this embodiment, the electrode 112 is an example of a single-layer structure, but the present invention is not limited thereto. For example, the electrode 112 may include a conductive layer 114. The conductive layer 114 is located on the high-dielectric-constant dielectric layer 110. In some embodiments, the material of the conductive layer 114 is, for example, titanium nitride. The conductive layer 116 is located on the conductive layer 114. In some embodiments, the material of the conductive layer 116 is, for example, a doped semiconductor material, such as boron-doped silicon germanium (BSiGe) or doped polycrystalline silicon. The conductive layer 118 is located on the conductive layer 116. In some embodiments, the material of the conductive layer 118 is, for example, a metal such as tungsten.

[0019] Referring to Figure 1D, a dielectric layer 120 and an interconnect structure 122 can be formed on the conductive layer 118. In some embodiments, the dielectric layer 120 may be a multilayer structure. In some embodiments, the material of the dielectric layer 120 is, for example, an oxide (e.g., silicon oxide). The interconnect structure 122 is located within the dielectric layer 120. In some embodiments, the material of the interconnect structure 122 is, for example, copper, tungsten, or a combination thereof. In some embodiments, the dielectric layer 120 and the interconnect structure 122 may be formed by an interconnect fabrication process.

[0020] Next, a conductive layer 124 may be formed on the dielectric layer 120 and the interconnect structure 122. The conductive layer 124 may be electrically connected to the interconnect structure 122. In some embodiments, the conductive layer 124 may serve as a pad. In some embodiments, the material of the conductive layer 124 may be, for example, aluminum.

[0021] Then, a dielectric layer 126 can be formed on the dielectric layer 120 and the conductive layer 124. The dielectric layer 126 can be a multilayer structure. For example, the dielectric layer 126 may include dielectric layers 126a and 126b, but the present invention is not limited thereto. As long as the dielectric layer 126 is a multilayer structure, it falls within the scope of the present invention. In some embodiments, the dielectric layer 126 can be formed by performing multiple deposition processes. This avoids the formation of voids in the dielectric layer 126. In some embodiments, the deposition process is, for example, chemical vapor deposition, atomic layer deposition, or high-density plasma chemical vapor deposition (HDP CVD).

[0022] Referring to Figure 1E, a portion of the dielectric layer 126 can be removed to expose the conductive layer 124. In some embodiments, the method for removing the portion of the dielectric layer 126 is, for example, chemical mechanical polishing or etch-back.

[0023] Hereinafter, the semiconductor structure 10 of the above embodiment will be described with reference to FIG1E. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0024] Referring to Figure 1E, the semiconductor structure 10 includes a substrate 100, an electrode 102, a support layer 104, a high-dielectric-constant dielectric layer 110, a low-dielectric-constant dielectric layer 108, and an electrode 112. The electrode 102 is located on the substrate 100. The electrode 102 is columnar. The support layer 104 is located on the sidewall of the electrode 102. The high-dielectric-constant dielectric layer 110 is located on the electrode 102 and the support layer 104. The low-dielectric-constant dielectric layer 108 is located between the support layer 104 and the high-dielectric-constant dielectric layer 110, and between the electrode 102 and the high-dielectric-constant dielectric layer 110. The electrode 112 is located on the high-dielectric-constant dielectric layer 110. In some embodiments, the semiconductor structure 10 may further include a support layer 106. The support layer 106 is located directly above the support layer 104. In some embodiments, the low-dielectric-constant dielectric layer 108 may be located on the support layer 106. In some embodiments, the low dielectric constant dielectric layer 108 may be located between the support layer 106 and the high dielectric constant dielectric layer 110.

[0025] The semiconductor structure 10 may further include a dielectric layer 120, an interconnect structure 122, a conductive layer 124, and a dielectric layer 126. The dielectric layer 120 is located on the conductive layer 118. The interconnect structure 122 is located within the dielectric layer 120. The conductive layer 124 is located on the dielectric layer 120 and the interconnect structure 122. The dielectric layer 126 is located on the dielectric layer 120 and between adjacent conductive layers 124. Furthermore, the detailed specifications of each component in the semiconductor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be repeated here.

[0026] Based on the above embodiments, it is understood that in the semiconductor structure 10 and its manufacturing method, capacitor C1 can be formed by electrode 102, low-dielectric-constant dielectric layer 108, high-dielectric-constant dielectric layer 110, and electrode 112. Furthermore, the low-dielectric-constant dielectric layer 108 is located between the support layer 104 and the high-dielectric-constant dielectric layer 110, and between electrode 102 and the high-dielectric-constant dielectric layer 110. Therefore, even if capacitor C1 bends, leakage current of capacitor C1 can be effectively prevented by the low-dielectric-constant dielectric layer 108. In addition, the low-dielectric-constant dielectric layer 108 can be used to avoid leakage current caused by electron accumulation in the high-dielectric-constant dielectric layer 110. Furthermore, the low-dielectric-constant dielectric layer 108 can reduce parasitic capacitance near the support layer 104.

[0027] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0028] 10: Semiconductor Structure 100: Base 102, 112: Electrodes 104, 106: Support layer 108: Low dielectric constant dielectric layer 110: High dielectric constant dielectric layer 114, 116, 118, 124: Conductive layers 120, 126, 126a, 126b: Dielectric layers 122: Internal Wiring Structure C1: Capacitor SW1: Sidewall T1, T2, T3: Thickness

Claims

1. A semiconductor structure, comprising: Base; A first electrode is located on the substrate, wherein the first electrode is columnar; The first support layer is located on the sidewall of the first electrode; A high dielectric constant dielectric layer is located on the first electrode and the first support layer; a low dielectric constant dielectric layer is located between the first support layer and the high dielectric constant dielectric layer, and between the first electrode and the high dielectric constant dielectric layer. and a second electrode, located on the high dielectric constant dielectric layer, wherein the thickness of the portion of the low dielectric constant dielectric layer located on the first support layer is greater than the thickness of the portion of the low dielectric constant dielectric layer located on the first electrode.

2. The semiconductor structure as claimed in claim 1, wherein the thickness of the portion of the low dielectric constant dielectric layer located on the first electrode is 72% to 88% of the thickness of the portion of the low dielectric constant dielectric layer located on the first support layer.

3. The semiconductor structure as claimed in claim 1, wherein the material of the high dielectric constant dielectric layer includes zirconium oxide (ZrO), aluminum oxide (AlO), or a combination thereof.

4. The semiconductor structure as claimed in claim 1, wherein the material of the low dielectric constant dielectric layer comprises silicon oxide.

5. The semiconductor structure as described in claim 1, further comprising: A second support layer is located directly above the first support layer, wherein the low dielectric constant dielectric layer is located on the second support layer.

6. The semiconductor structure as claimed in claim 5, wherein the low dielectric constant dielectric layer is further located between the second support layer and the high dielectric constant dielectric layer.

7. The semiconductor structure of claim 5, wherein the thickness of the portion of the low dielectric constant dielectric layer on the second support layer is greater than the thickness of the portion of the low dielectric constant dielectric layer on the first electrode.

8. The semiconductor structure of claim 5, wherein the thickness of the portion of the low dielectric constant dielectric layer on the first electrode is 72% to 88% of the thickness of the portion of the low dielectric constant dielectric layer on the second support layer.

9. The semiconductor structure of claim 1, wherein the material of the first electrode comprises titanium nitride, the material of the first support layer comprises nitride, and the material of the second electrode comprises titanium nitride.

10. A method for manufacturing a semiconductor structure, comprising: Provide a base; A first electrode is formed on the substrate, wherein the first electrode is columnar; A first support layer is formed on the sidewall of the first electrode; A low-dielectric-constant dielectric layer is formed on the first electrode and the first support layer; a high-dielectric-constant dielectric layer is formed on the low-dielectric-constant dielectric layer, wherein the low-dielectric-constant dielectric layer is located between the first support layer and the high-dielectric-constant dielectric layer and between the first electrode and the high-dielectric-constant dielectric layer; and a second electrode is formed on the high-dielectric-constant dielectric layer, wherein the thickness of the portion of the low-dielectric-constant dielectric layer located on the first support layer is greater than the thickness of the portion of the low-dielectric-constant dielectric layer located on the first electrode.

11. A method for manufacturing a semiconductor structure as claimed in claim 10, wherein the method for forming the low dielectric constant dielectric layer includes atomic layer deposition.

12. The method for manufacturing a semiconductor structure as described in claim 10, further comprising: A second support layer is formed on the sidewall of the first electrode, wherein the second support layer is located directly above the first support layer, and the low dielectric constant dielectric layer is further formed on the second support layer.

13. A method of manufacturing a semiconductor structure as claimed in claim 12, wherein the low dielectric constant dielectric layer is further located between the second support layer and the high dielectric constant dielectric layer.

14. A method of manufacturing a semiconductor structure as claimed in claim 12, wherein the thickness of the portion of the low dielectric constant dielectric layer located on the second support layer is greater than the thickness of the portion of the low dielectric constant dielectric layer located on the first electrode.

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