Semiconductor device and method for fabricating the same

Abstract

A method of fabricating a semiconductor device, including: forming a well region in a substrate, in which the substrate has a junction field effect transistor region adjacent to the well region; forming a source region in the well region; performing an implantation process to form a surface doped region in a portion of the well region between the source region and the junction field effect transistor region; forming a dielectric layer along an upper surface of the surface doped region and an upper surface of the junction field effect transistor region; and forming a gate structure on the dielectric layer.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. [Previous Technology]

[0002] SiC (silicon carbide) performs superiorly under extreme conditions such as high power, high frequency, and high temperature. Its main advantages over Si (silicon) in the semiconductor field include: 1. High bandgap: SiC has a wider bandgap (2.3–3.26 eV), enabling it to operate at higher voltages and temperatures; 2. High thermal conductivity: SiC's thermal conductivity is approximately three times that of Si, allowing for effective heat dissipation and making it suitable for high power density applications; 3. High operating temperature: SiC can operate at higher temperatures (up to over 600°C), suitable for extreme conditions; 4. Higher switching efficiency: SiC has faster switching speeds, enabling higher efficiency and lower losses in high-frequency switching applications; 5. High voltage resistance: SiC can withstand higher voltages, making it suitable for high-voltage and high-power applications such as electric vehicles and power electronic equipment.

[0003] However, SiC (silicon carbide) typically has a high defect density, primarily due to challenges in its crystal structure and growth process. Common defects include dislocations, stacking faults, and vacancies. These defects affect the electronic properties and reliability of SiC, leading to higher leakage current, poorer switching characteristics, and lower device reliability, especially in high-temperature and high-efficiency applications. Therefore, a semiconductor device and manufacturing method is needed to address these issues. [Summary of the Invention]

[0004] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: forming a well region in a substrate, wherein the substrate has a junction field-effect transistor region adjacent to the well region; forming a source region in the well region; performing an implantation process to form a surface-doped region in a portion of the well region located between the source region and the junction field-effect transistor region; forming a dielectric layer along an upper surface of the surface-doped region and an upper surface of the junction field-effect transistor region; and forming a gate structure on the dielectric layer.

[0005] In some embodiments, one of the dopants used in the implantation process is silicon (Si).

[0006] In some embodiments, the dopant species for performing the implantation process is germanium (Ge), boron (B) or gallium (Ga).

[0007] In some embodiments, the dielectric layer extends to an upper surface of the source region.

[0008] In some embodiments, the thickness of the surface doped region is less than the thickness of the source region.

[0009] A semiconductor device includes: a substrate including a junction field-effect transistor region; a well region located in the substrate and adjacent to the junction field-effect transistor region; a source region located in the well region; a surface-doped region located in the well region and located between the junction field-effect transistor region and the source region; a dielectric layer along an upper surface of the surface-doped region and an upper surface of the junction field-effect transistor region; and a gate structure located on the dielectric layer.

[0010] In some embodiments, the surface doped region has a higher proportion of silicon (Si) atoms compared to the substrate, well region or source region.

[0011] In some embodiments, the surface doped region has a higher proportion of germanium (Ge), boron (B), or gallium (Ga) atoms compared to the substrate, well region, or source region.

[0012] In some embodiments, the dielectric layer extends to an upper surface of the source region.

[0013] In some embodiments, the thickness of the surface doped region is less than the thickness of the source region.

Implementation Method

[0014] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another element or feature. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, “about,” “approximately,” “roughly,” or “substantially” can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “about,” “approximately,” “roughly,” or “substantially” can be inferred. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits are scaled down.

[0017] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit this disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including," when used in this specification, designate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence of said features, integrals, steps, operations, elements, and / or components.

[0018] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection area illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection area to the non-injection area. Similarly, a buried area formed through injection can result in some injection in the area between the buried area and the surface through which injection is carried out. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of this disclosure.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0020] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.

[0021] Figures 1 through 7 are cross-sectional views of different steps in a method for forming a semiconductor device according to embodiments of this disclosure. The manufacturing methods in Figures 1 through 7 are used to form a semiconductor device. Various operations of the embodiments are provided herein. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood to benefit from this description. Furthermore, it should be understood that not all operations must be present in every embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.

[0022] Referring to Figure 1, a substrate 100 is illustrated, wherein the substrate 100 includes a substrate region 105 and a drift region 110 located above the substrate region 105. In some embodiments, the substrate 100 may be made of a semiconductor material, such as silicon carbide, silicon, the like, or combinations thereof. In some embodiments, the substrate region 105 and the drift region 110 may include a type-1 dopant. For example, the substrate region 105 and the drift region 110 may include an N-type dopant, such as nitrogen, arsenic, or phosphorus. In some embodiments, the substrate region 105 is a heavily doped region, while the drift region 110 is a lightly doped region. For example, the dopant concentration of the type-1 dopant in the substrate region 105 is higher than the dopant concentration of the type-1 dopant in the drift region 110.

[0023] Next, a well region 120 is formed in the drift region 110. First, the well region 120 is formed on the drift region 110. In some embodiments, a first patterned photoresist layer with an opening may be formed on the drift region 110. Then, an ion implantation process may be performed on the drift region 110 through the opening of the first patterned photoresist layer to implant ions into the drift region 110 to form the well region 120. The location of the well region 120 is defined by the opening of the first patterned photoresist layer. Next, the first patterned photoresist layer is removed.

[0024] In some embodiments, well regions 120 are located on the upper surfaces of the left and right sides of drift regions 110, and do not cover the middle upper surface of drift regions 110. In some embodiments, well regions 120 may contain a second type dopant different from the first type dopant. For example, well regions 120 may contain P-type dopant, such as boron, aluminum, or gallium. In some embodiments, drift regions 110 have a portion extending into the well regions 120, which may be referred to as JFET regions 115 (Junction field effect transistor).

[0025] Referring to Figure 2, a first doped region 130 and a second doped region 140 are formed. For example, a second patterned photoresist layer may be formed on a portion of the well region 120 and the drift region 110, and an ion implantation process is performed to implant ions into the well region 120 to form the first doped region 130. The location of the first doped region 130 is defined by the second patterned photoresist layer. Then, the second patterned photoresist layer is removed. In some embodiments, the first doped region 130 is located on the upper surface of the left and right sides of the well region 120.

[0026] In some embodiments, the first doped region 130 may contain a type 1 dopant. In some embodiments, the first doped region 130 may contain an N-type dopant, such as nitrogen, arsenic, or phosphorus. In some embodiments, the first doped region 130 may also be referred to as a source region or a drain region.

[0027] Next, a second doped region 140 is formed in the well region 120. In some embodiments, a third patterned photoresist layer may be formed on a portion of the first doped region 130, the well region 120, and the drift region 110, and an ion implantation process is performed to implant ions into the well region 120 to form the second doped region 140. In some embodiments, the second doped region 140 may contain a type II dopant. In some embodiments, the second doped region 140 may contain a p-type dopant, such as boron, aluminum, or gallium. In some embodiments, the second doped region 140 may contain a higher concentration of type II dopant than the well region 120. In some embodiments, the second doped region 140 is located on the left and right sides of the first doped region 130. The position of the second doped region 140 is defined by the third patterned photoresist layer. Next, the third patterned photoresist layer is removed.

[0028] As discussed above, in this embodiment, the first doped region 130 is formed first, followed by the formation of the second doped region 140. However, in other embodiments, the second doped region 140 may be formed first, followed by the formation of the first doped region 130.

[0029] Referring to Figure 3, a masking layer MA1 is formed to expose the well region 120. Specifically, the masking layer MA1 may be formed on the first doped region 130, the second doped region 140, and the drift region 110. More specifically, the masking layer MA1 exposes the portion of the well region 120 located between the first doped region 130 and the JFET region 115. In some embodiments, the masking layer MA1 exposes the upper surface of the well region 120. In some embodiments, the masking layer MA1 may be a photoresist layer. In other embodiments, the masking layer MA1 may be a hard mask formed of a dielectric material, such as silicon nitride, silicon oxide, the like, or combinations thereof.

[0030] Referring to Figure 4, an implantation process is performed on the exposed well region 120. Specifically, using a masking layer MA1 as a mask, dopant species can be implanted onto the upper surface of the exposed well region 120. Specifically, the implantation process implants dopant species onto the upper surface of the well region 120. In some embodiments, the masking layer MA1 is configured to prevent dopant species from being implanted into the first doped region 130, the second doped region 140, and the JFET region 115. In some embodiments, the implantation process forms a surface doped region 121 on the exposed surface of the well region 120. The surface doped region 121 can serve as a channel region in subsequent structures, and therefore the surface doped region 121 can also be referred to as a channel region.

[0031] In some embodiments, the dopant species implanted onto the upper surface of well region 120 is a dopant species that can reduce the defect density in the region to improve mobility. In some embodiments, the dopant species implanted onto the upper surface of well region 120 may include silicon (Si) ions, germanium (Ge), boron (B), or gallium (Ga) ions. In some embodiments, the surface doped region 121 is located on the upper surface of well region 120, and its vertical thickness is less than the vertical thickness of the first doped region 130 or the second doped region 140. In some embodiments, the upper surface of the surface doped region 121 is substantially flush with the upper surfaces of JFET region 115, the first doped region 130, and the second doped region 140.

[0032] In embodiments where the dopant species of the surface doped region 121 is silicon (Si) ions, the material of the surface doped region 121 can be silicon carbide with a high silicon concentration. That is, the surface doped region 121 has a higher silicon atom ratio compared to other parts of the substrate 100, such as the substrate region 105, drift region 110, well region 120, first doped region 130, and second doped region 140. In other words, the surface doped region 121 has a lower carbon atom ratio compared to other parts of the substrate 100, such as the substrate region 105, drift region 110, well region 120, first doped region 130, and second doped region 140. In some embodiments, since the surface doped region 121 is formed on the upper surface of the well region 120, the surface doped region 121 also has the same type II dopant as the well region 120, such as a p-type dopant.

[0033] In embodiments where the dopant species of the surface doped region 121 is germanium (Ge), boron (B), or gallium (Ga) ions, the material of the surface doped region 121 may sequentially have silicon germanium carbide (SiGeC), silicon boron carbide (SiC:B), or silicon gallium carbide (SiC:Ga). That is, the surface doped region 121 has a higher proportion of germanium, boron, or gallium atoms compared to other parts of the substrate 100, such as substrate region 105, drift region 110, well region 120, first doped region 130, and second doped region 140. In some embodiments, other parts of the substrate 100, such as substrate region 105, drift region 110, well region 120, first doped region 130, and second doped region 140, do not have germanium, boron, or gallium, or have extremely low concentrations of germanium, boron, or gallium. In some embodiments, since the surface doped region 121 is formed on the upper surface of the well region 120, the surface doped region 121 also has the same type II dopant as the well region 120, such as a P-type dopant.

[0034] Referring to Figure 5, the masking layer MA1 is removed. Specifically, the masking layer MA1 can be removed to expose the upper surfaces of the JFET region 115, the surface doped region 121, the first doped region 130, and the second doped region 140 in the drift region 110.

[0035] Referring to Figure 6, the dielectric layer 160 and the gate structure 200 can be formed on the exposed surfaces of the surface doped region 121 and the drift region 110. First, the dielectric layer 160 can be deposited on the substrate 100. Next, the gate structure 200 is deposited on the dielectric layer 160. Finally, the gate dielectric layer 160 and the gate structure 200 are patterned.

[0036] In some embodiments, the dielectric layer 160 has the same width as the gate structure 200. In some embodiments, the dielectric layer 160 covers the upper surfaces of the JFET region 115, the surface-doped region 121, and the drift region 110. In some embodiments, the dielectric layer 160 also covers a portion of the upper surface of the well region 120. In some embodiments, the dielectric layer 160 comprises a dielectric material, such as silicon oxide, silicon nitride, the like, or combinations thereof. In some embodiments, the dielectric layer 160 may serve as a gate dielectric and be disposed to electrically isolate the gate from other conductive materials, such as the drift region 110, the surface-doped region 121, and / or the first doped region 130. In some embodiments, the vertical thickness of the dielectric layer 160 is greater than the vertical thickness of the surface-doped region 121. In some embodiments, the gate structure 200 may be made of a conductive material, such as polysilicon, metal, or other suitable conductive material.

[0037] Referring to Figure 7, a source electrode 300 is formed on a portion of the first doped region 130 and the second doped region 140, and a drain electrode 400 is formed below the first doped region 130 below the drift region 110.

[0038] In some embodiments, the source electrode 300 can be formed by deposition of a fifth patterned photoresist layer. The location of the source electrode 300 is defined by the fifth patterned photoresist layer. Then, the first patterned photoresist layer is removed. In some embodiments, the source electrode 300 covers the upper surface of the second doped region 140 and a portion of the upper surface of the first doped region 130.

[0039] Next, the drain electrode 400 can be formed by vertically flipping the drift region 110 and depositing it on the back side of the first doped region 130 below the drift region 110. After the drain electrode 400 is formed, it can be vertically flipped back to its original position. The source electrode 300 and the drain electrode 400 can be made of conductive materials, such as metal.

[0040] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0041] The nature of this disclosure is best understood from the following detailed description when read with reference to the accompanying drawings. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1 through 7 are cross-sectional views of different steps in a method for forming a semiconductor device according to some embodiments of this disclosure. [Biomaterial Storage]

[0043] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a semiconductor device, comprising: A well region is formed in a substrate, wherein the substrate has a junction field-effect transistor region adjacent to the well region; A source region is formed in the well region; an implantation process is performed to form a surface-doped region in a portion of the well region between the source region and the junction field-effect transistor region, wherein the thickness of the surface-doped region is less than the thickness of the source region; a dielectric layer is formed along an upper surface of the surface-doped region and an upper surface of the junction field-effect transistor region; and a gate structure is formed on the dielectric layer.

2. The method as described in claim 1, wherein one of the doped species performing the implantation process is silicon (Si).

3. The method as described in claim 1, wherein a dopant species performing the implantation process is germanium (Ge), boron (B), or gallium (Ga).

4. The method as described in claim 1, wherein the dielectric layer extends to an upper surface of the source region.

5. A semiconductor device, comprising: A substrate includes a junction field-effect transistor region; a well region located in the substrate and adjacent to the junction field-effect transistor region; a source region located in the well region; a surface-doped region located in the well region and between the junction field-effect transistor region and the source region, wherein a thickness of the surface-doped region is less than a thickness of the source region; a dielectric layer along an upper surface of the surface-doped region and an upper surface of the junction field-effect transistor region; and a gate structure located on the dielectric layer.

6. The semiconductor device as claimed in claim 5, wherein the surface doped region has a higher silicon (Si) atom ratio than the substrate, the well region, or the source region.

7. The semiconductor device as claimed in claim 5, wherein the surface doped region has a higher proportion of germanium (Ge), boron (B), or gallium (Ga) atoms compared to the substrate, the well region, or the source region.

8. The semiconductor device as claimed in claim 5, wherein the dielectric layer extends to an upper surface of the source region.

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