Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first element, first and second dielectric layers, first and second metal layers, and a functional portion, and the first element includes gate, source, and drain electrodes. The first dielectric layer is disposed on the first element. The first metal layer is disposed on the first dielectric layer, is electrically connected to the first element, and includes a first conductive portion. The first conductive portion is electrically connected to the source electrode of the first element. The second dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the second dielectric layer and includes a second conductive portion corresponding to the first conductive portion. The functional portion is located between the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion, and the functional portion together serve as a second element, and the second element is electrically connected to the source electrode of the first element.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device comprising a first element and a second element. [Previous Technology]

[0002] Gallium nitride (GaN) materials are widely used due to their wide bandgap and strong polarization effect. For example, GaN semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures. When a HEMT is in normally-on mode, it is often integrated with other components, such as metal oxide semiconductor field-effect transistors (MOSFETs), to enable the HEMT to have a normally-off function for practical applications.

[0003] However, in integrated manufacturing processes, to avoid damage to MOSFETs from high-voltage, high-speed switching operations or to obtain other functions, additional external components may be required, making it difficult to miniaturize the semiconductor device and compromising its reliability. Therefore, although existing semiconductor devices have gradually met their intended uses, they still do not completely meet the requirements in all aspects. Thus, there are still some problems to be overcome regarding semiconductor devices. [Summary of the Invention]

[0004] The semiconductor device disclosed herein includes a first element and a second element, which are integrated within the semiconductor device prior to subsequent packaging processes. For example, after providing the first element, a redistribution structure can be provided on the first element, and the redistribution structure may include interleaved stacked dielectric and metal layers, thereby allowing the second element to be disposed within the redistribution structure. That is, at least a portion of the second element may be shared with or formed simultaneously with at least a portion of the redistribution structure. The second element may be a passive element, such as a capacitor, resistor, or diode. While diodes are not typically defined as passive elements, they may be defined as such in some cases. Accordingly, the embedded device disclosed herein, which embeds a passive element (second element) into an active element (first element), can simultaneously possess the functions of both the first and second elements, thereby reducing the size of the semiconductor device, improving the electrical performance of the semiconductor device, improving the reliability of the semiconductor device, and / or reducing manufacturing costs.

[0005] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first element, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a functional portion. The first element includes a gate electrode, a source electrode, and a drain electrode. The first dielectric layer is disposed on the first element. The first metal layer is disposed on the first dielectric layer, electrically connected to the first element, and includes a first conductive portion. The first conductive portion is electrically connected to the source electrode of the first element. The second dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the second dielectric layer and includes a second conductive portion corresponding to the first conductive portion. The functional portion is located between the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion, and the functional portion together serve as a second element, and the second element is electrically connected to the source electrode of the first element.

Implementation Method

[0006] The semiconductor devices of various embodiments of this disclosure will be described in detail below. It should be understood that the following description provides many different embodiments for implementing some embodiments of this disclosure in different ways. The specific elements and arrangements described below are only for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not for limiting this disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements in order to clearly describe this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any relationship between the different embodiments and / or structures discussed.

[0007] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element of the diagram to another. It is understood that if the arrangement of the diagrams is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0008] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include a situation where the first material layer and the second material layer are in direct contact, or a situation where the first material layer and the second material layer are not in direct contact, that is, a situation where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0009] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that (or those) element, nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0010] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms may also include situations where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0011] In this text, the terms "approximately," "about," and "substantially" generally indicate a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The terms "range between the first value and the second value" or "first value ~ second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first value and the second value within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0012] Certain terms are used throughout this disclosure and in the claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, the terms "comprise," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Therefore, when the terms "comprise," "containing," and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0013] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0014] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, for example, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and shall not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0015] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the normal direction of the substrate is the third direction D3.

[0016] Referring to Figure 1, which is a schematic cross-sectional view of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 1, in some embodiments, a first element 10 may be provided. In some embodiments, the first element 10 may be a high electron mobility transistor (HEMT). For example, the first element 10 may be a depletion mode (D-type) high electron mobility transistor. In some embodiments, the first element 10 may include a substrate 100, a channel layer 102, a barrier layer 104, a gate electrode 112, a source electrode 114, and a drain electrode 116, but the present disclosure is not limited thereto. In some embodiments, the first element 10 may further include a compound semiconductor layer 111.

[0017] As shown in Figure 1, in some embodiments, substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The SOI substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polycrystalline silicon, the like, or combinations thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), the like, or combinations thereof, but this disclosure is not limited thereto. Substrate 100 may be an undoped or doped substrate. Substrate 100 may include a multi-layered substrate or a gradient substrate. Substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. For example, substrate 100 may be a silicon substrate.

[0018] As shown in Figure 1, in some embodiments, a channel layer 102 may be formed on the substrate 100. In some embodiments, the channel layer 102 may include a III-V compound semiconductor material, such as a III-nitride, but this disclosure is not limited thereto. For example, the channel layer 102 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like, or combinations thereof, but this disclosure is not limited thereto. For example, the channel layer 102 may be gallium nitride. In some embodiments, the channel layer 102 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments (not shown), a buffer layer may be formed between the substrate 100 and the channel layer 102. In other embodiments, the buffer layer may be omitted.

[0019] As shown in Figure 1, in some embodiments, a barrier layer 104 may be formed on the channel layer 102. In some embodiments, the barrier layer 104 may include a III-V compound semiconductor material, such as a III-V nitride, but this disclosure is not limited thereto. For example, the barrier layer 104 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the likes thereof, or combinations thereof, but this disclosure is not limited thereto. For example, the barrier layer 104 may be aluminum gallium nitride. In some embodiments, the barrier layer 104 may be formed by a deposition process. Due to the heterogeneous interface between the channel layer 102 and the barrier layer 104, and the difference in lattice constant between the channel layer 102 and the barrier layer 104, a two-dimensional electron gas (2DEG) can be formed near the top surface of the channel layer 102 and serve as a current path.

[0020] As shown in Figure 1, in some embodiments, a compound semiconductor layer 111 may be formed on the barrier layer 104. In some embodiments, the compound semiconductor layer 111 may be a p-type doped compound semiconductor. In some embodiments, the compound semiconductor layer 111 may include p-type doped gallium nitride. In some embodiments, a gate electrode 112 may be formed on the compound semiconductor layer 111 and on the barrier layer 104. In some embodiments, a source electrode 114 and a drain electrode 116 may be formed on the barrier layer 104. In some embodiments, the gate electrode 112, the source electrode 114, and the drain electrode 116 may each include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, the like thereof, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like thereof, or a combination thereof. In some embodiments, the metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), the like, or combinations thereof. In some embodiments, the semiconductor material may include polycrystalline silicon or polycrystalline germanium, the like, or combinations thereof. In some embodiments, the conductive material may be formed by deposition processes, sputtering processes, evaporation processes, similar processes, or combinations thereof, but this disclosure is not limited thereto.

[0021] Referring to Figure 2, which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 2, in some embodiments, a first dielectric layer 200 may be formed on the first element 10 in a blanket manner. In some embodiments, the first dielectric layer 200 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, the like, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the first dielectric layer 200 may be formed by a deposition process. In some embodiments, a first gate via 202 may be formed in the first dielectric layer 200, and the first gate via 202 may be electrically connected to a gate electrode 112. In some embodiments, first source vias 204, 205 may be formed in the first dielectric layer 200, and the first source vias 204, 205 may be electrically connected to a source electrode 114. In some embodiments, a first drain via 206 may be formed in the first dielectric layer 200, and the first drain via 206 may be electrically connected to the drain electrode 116. In some embodiments, the materials and forming methods of the first gate via 202, the first source vias 204 and 205, and the first drain via 206 may be the same as or different from the materials and forming methods of the gate electrode 112.

[0022] As shown in Figure 2, in some embodiments, a first metal layer 210 may be formed on the first dielectric layer 200, and the first metal layer 210 may be electrically connected to the first element 10. In some embodiments, the material and formation method of the first metal layer 210 may be the same as or different from the material and formation method of the gate electrode 112. In some embodiments, the first metal layer 210 may include a first gate contact 212, a first source contact 214, a first conductive portion 215, and a first drain contact 216. In some embodiments, the first metal layer 210 may be formed on the first dielectric layer 200, and then the first metal layer 210 may be patterned to simultaneously form the first gate contact 212, the first source contact 214, the first conductive portion 215, and the first drain contact 216. In other words, the first conductive portion 215 may be formed in the same process as the first gate contact 212, the first source contact 214, and the first drain contact 216, thereby eliminating the need for an additional process to form the first conductive portion 215. Therefore, the reliability of semiconductor devices can be improved and / or manufacturing costs can be reduced.

[0023] As shown in Figure 2, in some embodiments, the first gate contact 212 may be electrically connected to the gate electrode 112 via the first gate via 202. In some embodiments, the first source contact 214 may be electrically connected to the source electrode 114 via the first source via 204. In some embodiments, the first conductive portion 215 may be electrically connected to the source electrode 114 via the first source via 205. In some embodiments, the first drain contact 216 may be electrically connected to the drain electrode 116 via the first drain via 206.

[0024] Referring to Figure 3, which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 3, in some embodiments, a second dielectric layer 300 may be formed on a first metal layer 210 in a blanket manner. In some embodiments, the material and formation method of the second dielectric layer 300 may be the same as or different from the material and formation method of the first dielectric layer 200. In some embodiments, a second gate via 302, a second source via 304, and a second drain via 306 may be formed in the second dielectric layer 300, and the second gate via 302, the second source via 304, and the second drain via 306 may be electrically connected to a first gate contact 212, a first source contact 214, and a first drain contact 216, respectively.

[0025] Referring to Figure 4, which is a schematic cross-sectional view of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 4, in some embodiments, a second metal layer 310 may be formed on a second dielectric layer 300 to obtain the semiconductor device 1. In some embodiments, the material and formation method of the second metal layer 310 may be the same as or different from the material and formation method of the first metal layer 210. In some embodiments, the second metal layer 310 may include a second gate contact 312, a second source contact 314, a second conductive portion 315, and a second drain contact 316. In some embodiments, the second metal layer 310 may be formed on the second dielectric layer 300, and then the second metal layer 310 may be patterned to simultaneously form the second gate contact 312, the second source contact 314, the second conductive portion 315, and the second drain contact 316. In other words, the second conductive portion 315 can be formed in the same process as the second gate contact 312, the second source contact 314, and the second drain contact 316, thus eliminating the need for an additional process to form the second conductive portion 315. Therefore, the reliability of the semiconductor device can be improved and / or the manufacturing cost can be reduced.

[0026] In some embodiments, the first dielectric layer 200, the first metal layer 210, the second dielectric layer 300, and the second metal layer 310 located on the first element 10 may be collectively referred to as a redistribution structure RDLS, and the redistribution structure RDLS may further include other dielectric layers and / or other metal layers. In some embodiments, the semiconductor device 1 may be connected to an external device via the redistribution structure RDLS.

[0027] As shown in Figure 4, in some embodiments, the second conductive portion 315 may correspond to the first conductive portion 215. In some embodiments, the projected area and projection position of the second conductive portion 315 on the substrate 100 may be substantially the same as the projected area and projection position of the first conductive portion 215 on the substrate 100. In some embodiments, the projected area of ​​the second conductive portion 315 on the substrate 100 may be 0.8 to 1.2 times that of the projected area of ​​the first conductive portion 215 on the substrate 100 to improve alignment accuracy. In some embodiments, a portion of the second dielectric layer 300 located between the first conductive portion 215 and the second conductive portion 315 may serve as a functional portion 401.

[0028] That is, the first conductive portion 215, the second conductive portion 315, and the functional portion 401 can collectively serve as the second element 21, and the second element 21 can be electrically connected to the source electrode 114 of the first element 10. In this embodiment, the second element 21 can be a capacitor. In this embodiment, the material of the functional portion 401 can be substantially the same as the material of the second dielectric layer 300. In this embodiment, there can be substantially no interface between the functional portion 401 and the second dielectric layer 300, so the functional portion 401 and the second dielectric layer 300 can be integrally formed. In some embodiments, the channel layer 102 and the barrier layer 104 in the first element 10 and the second element 21 can be disposed on the same surface of the substrate 100. In some embodiments, the bottom surface of the functional portion 401 can be higher than the top surfaces of the gate electrode 112, the source electrode 114, and the drain electrode 116, so that the functional portion 401 and the gate electrode 112, the source electrode 114, and the drain electrode 116 are disposed in different layers.

[0029] In detail, since the redistribution structure RDLS located on the first element 10 may include multiple dielectric layers and multiple metal layers, and the capacitor can be regarded as having a dielectric layer sandwiched in the metal layers, the first conductive portion 215 of the first metal layer 210 in the redistribution structure RDLS can serve as the lower electrode of the capacitor, the second conductive portion 315 of the second metal layer 310 in the redistribution structure RDLS can serve as the upper electrode of the capacitor, and a portion (functional portion 401) of the second dielectric layer 300 in the redistribution structure RDLS can serve as the dielectric material of the capacitor, so as to additionally provide a capacitor in the empty space of the redistribution structure RDLS. Therefore, the second element 21 can be formed in the redistribution structure RDLS on the first element 10.

[0030] In other words, this disclosure allows for the additional placement of a second element, such as a capacitor, in the spaces between interconnects (e.g., vias, contacts) on the first element for providing electrical interconnection. Compared to external capacitors, placing the capacitor in the spaces of the redistribution structure RDLS can reduce the size of the semiconductor device, improve the reliability of the semiconductor device (e.g., avoid limitations imposed by alignment process accuracy), and / or reduce manufacturing costs (e.g., omit additional forming processes for forming the second element, omit additional wire bonding processes). Compared to placing the capacitor in the same layer as the gate electrode 112, source electrode 114, and drain electrode 116, placing the capacitor in the spaces of the redistribution structure RDLS can prevent leakage current or interference between components.

[0031] Referring to Figure 5, which is a circuit diagram of a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 5, in some embodiments, the first element 10 may have a gate terminal G, a source terminal S, and a drain terminal D, and the second element 21 may be electrically connected to the source electrode of the first element 10. That is, the second element 21 may be equivalently electrically connected to the source terminal S of the first element 10.

[0032] Referring to Figure 6, which is a circuit diagram of a semiconductor device 1' according to an embodiment of the present disclosure. As shown in Figure 6, in some embodiments, the semiconductor device 1' may further include a third element 30. In some embodiments, the third element 30 may be a metal oxide semiconductor field-effect transistor (MOSFET). For example, the third element 30 may be an N-type laterally diffused metal oxide semiconductor MOSFET. Therefore, the first element 10 and the third element 30 can jointly form a cascode structure to improve the versatility of the first element 10. Furthermore, since the second element 21 can be equivalently electrically connected to the source terminal S of the first element 10, the second element 21 can reduce the voltage value through the third element 30 to avoid damage to the third element 30 by high-voltage, high-speed switching operations.

[0033] In some embodiments, the second element 21 may be an embedded capacitor, and the capacitance of the second element 21 may be greater than or equal to 0.1 nF and less than or equal to 10 nF, but this disclosure is not limited thereto. For example, the capacitance of the second element 21 may be 0.1 nF, 0.5 nF, 1 nF, 1.2 nF, 1.5 nF, 2 nF, 5 nF, 10 nF, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. Accordingly, the embedded device of this disclosure can improve the electrical performance of semiconductor devices.

[0034] Referring to Figures 7 to 9, which are perspective views of a semiconductor device 1 according to an embodiment of the present disclosure. For ease of explanation, the connection methods corresponding to the gate electrode 112, source electrode 114, and drain electrode 116 are shown in Figures 7 to 9 respectively. As shown in Figure 7, in some embodiments, the gate electrode 112 and the second gate contact 312 are connected via a first gate via 202. As shown in Figure 8, in some embodiments, the source electrode 114 and the second source contact 314 are connected via a first source via 204, and the source electrode 114 and the second element 21 are connected via a first source via 205. As shown in Figure 9, in some embodiments, the drain electrode 116 and the second drain contact 316 are connected via a first drain via 206.

[0035] Referring to Figure 10, which is a schematic diagram of the electrodes of a semiconductor device according to an embodiment of the present disclosure. The aforementioned Figure 4 shows a cross-sectional view taken along line segment I-I' in Figure 10. As shown in Figure 10, in some embodiments, the gate electrode 112 may be disposed between the source electrode 114 and the drain electrode 116. In some embodiments, the source electrode 114 and the drain electrode 116 may be corresponding comb-shaped electrodes, and the gate electrode 112 may be an S-shaped electrode, but the present disclosure is not limited thereto.

[0036] In the following text, the same or similar component symbols and descriptions may be omitted.

[0037] Referring to Figure 11, which is a schematic cross-sectional view of a semiconductor device 2 according to an embodiment of the present disclosure. As shown in Figure 11, in some embodiments, a portion of the second dielectric layer 300 located on the first conductive portion 215 may be removed to expose the top surface of the first conductive portion 215. A functional portion 402 may then be formed on the top surface of the first conductive portion 215, such that the functional portion 402 is located between the first conductive portion 215 and the second conductive portion 315. In some embodiments, the functional portion 402 may be formed by a deposition process or a three-dimensional (3D) printing process. In some embodiments, the top surface of the functional portion 402 may be lower than or flush with the top surface of the second dielectric layer 300. Wherein, when the top surface of the functional portion 402 is lower than the top surface of the second dielectric layer 300, the capacitance of the second element 22 may be increased. Accordingly, the capacitance of the second element 22 formed by the first conductive portion 215, the functional portion 402 and the second conductive portion 315 can be adjusted by adjusting the thickness of the functional portion 402.

[0038] As shown in Figure 11, in some embodiments, the material of the functional portion 402 may be different from the material of the second dielectric layer 300. In some embodiments, the functional portion 402 may be an oxide such as silicon oxide, a nitride such as silicon nitride, a oxynitride such as silicon oxynitride, a polymer such as polyimide (PI), other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric constant of the material of the functional portion 402 may be greater than the dielectric constant of the material of the second dielectric layer 300. In some embodiments, the difference between the dielectric constant of the material of the functional portion 402 and the dielectric constant of the material of the second dielectric layer 300 may be greater than 0 and less than 5. For example, the difference between the dielectric constant of the material of the functional portion 402 and the dielectric constant of the material of the second dielectric layer 300 may be 0.1, 0.2, 0.3, 0.5, 1, 1.5, 2, 2.5, 3, 4, 5, or any value or range of values ​​between the foregoing values, but this disclosure is not limited thereto. For example, the material of the functional portion 402 may be a dielectric material with a high dielectric constant (high-k). In some embodiments, the capacitance of the second element 22 may be greater than the capacitance of the second element 21. Accordingly, the capacitance of the second element 22 formed by the first conductive portion 215, the functional portion 402, and the second conductive portion 315 can be adjusted by adjusting the material of the functional portion 402.

[0039] Referring to Figures 12, 13, and 14, which are respectively a cross-sectional view, a circuit diagram, and a perspective view of a semiconductor device 3 according to an embodiment of the present disclosure. As shown in Figure 12, in some embodiments, a portion of the second dielectric layer 300 located on the first conductive portion 215 may be removed to expose the top surface of the first conductive portion 215. Then, a functional portion 403 may be formed on the top surface of the first conductive portion 215, such that the functional portion 403 may be located between the first conductive portion 215 and the second conductive portion 315. In some embodiments, the functional portion 403 may be a conductive material. In some embodiments, the functional portion 403 may be formed simultaneously during the formation of the second gate via 302, the second source via 304, and the second drain via 306. In some embodiments, the functional portion 403 may be formed by a deposition process, a sputtering process, a vapor deposition process, similar processes, or combinations thereof. In other words, the first conductive portion 215, the second conductive portion 315, and the functional portion 403 can collectively serve as the second element 23, and the second element 23 can be electrically connected to the source electrode 114 of the first element 10. In this embodiment, the second element 23 can be a resistor.

[0040] As shown in Figure 13, in some embodiments, the second element 23 may be an embedded resistor, and the equivalent resistance of the second element 23 may be greater than or equal to 0.1 Ω and less than or equal to 10 kΩ, but this disclosure is not limited thereto. For example, the equivalent resistance of the second element 23 may be 0.1 Ω, 0.5 Ω, 1 Ω, 5 Ω, 10 Ω, 100 Ω, 500 Ω, 1 kΩ, 5 kΩ, 10 kΩ, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. Accordingly, the embedded device of this disclosure can improve the electrical performance of the semiconductor device. In detail, the second element 23 as an embedded resistor can improve the switching speed.

[0041] As shown in Figure 14, in some embodiments, the functional portion 403 in the second element 23 may have an S-shaped form to increase the resistance value of the second element 23, but this disclosure is not limited thereto. The functional portion 403 may be Z-shaped, spiral-shaped, or other suitable shapes. In other embodiments, the height of one end of the functional portion 403 may be higher than the height of the other end of the functional portion 403. In other words, the functional portion 403 may be a three-dimensional S-shaped shape. In some embodiments, the functional portion 403 may be closer to the second source via 304 than to the second drain via 306. In some embodiments, the distance s1 between the functional portion 403 and the second drain via 306 may be greater than the distance s2 between the functional portion 403 and the second source via 304 to prevent high voltage from the second drain contact 316 from breaking down the second dielectric layer 300.

[0042] Referring to Figures 15, 16, and 17, which are respectively a cross-sectional view, a circuit diagram, and a perspective view of a semiconductor device 4 according to an embodiment of the present disclosure. As shown in Figure 15, in some embodiments, a portion of the second dielectric layer 300 located on the first conductive portion 215 may be removed to expose the top surface of the first conductive portion 215. Then, a functional portion 404 may be formed on the top surface of the first conductive portion 215, such that the functional portion 404 may be located between the first conductive portion 215 and the second conductive portion 315. In some embodiments, the functional portion 404 may be a doped semiconductor material. For example, the functional portion 404 may be N-type doped silicon. In some embodiments, the functional portion 404 may be formed by a deposition process or a three-dimensional printing process.

[0043] That is, the first conductive portion 215, the second conductive portion 315, and the functional portion 404 can collectively serve as the second element 24, and the second element 24 can be electrically connected to the source electrode 114 of the first element 10. In this embodiment, the second element 24 can be a Schottky diode. In some embodiments, in order to form a Schottky diode, the first conductive portion 215 and the second conductive portion 315 in the second element 24 can include different conductive materials to form an ohmic contact and a Schottky contact, respectively.

[0044] As shown in Figure 16, in some embodiments, the second element 24 may be an embedded Schottky diode, and the voltage of the second element 24 may be greater than or equal to 20V and less than or equal to 40V, but this disclosure is not limited thereto. For example, the voltage of the second element 24 may be 20V, 22V, 24V, 26V, 28V, 30V, 35V, 40V, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. Accordingly, the embedded device of this disclosure can improve the electrical performance of a semiconductor device. In detail, the second element 24, as an embedded Schottky diode, can improve switching speed. As shown in Figure 17, in some embodiments, the functional portion 404 in the second element 24 may be disposed on the same layer as the second dielectric layer 300. In some embodiments, the top surface of the functional portion 404 in the second element 24 may be flush with the top surface of the second dielectric layer 300.

[0045] Figures 18, 19, and 20 are respectively a cross-sectional view, a circuit diagram, and a perspective view of a semiconductor device 5 according to an embodiment of the present disclosure. As shown in Figure 18, in some embodiments, a portion of the second dielectric layer 300 located on the first conductive portion 215 may be removed to expose the top surface of the first conductive portion 215. Then, a functional portion 405 may be formed on the top surface of the first conductive portion 215, such that the functional portion 405 may be located between the first conductive portion 215 and the second conductive portion 315. In some embodiments, the functional portion 405 may be a doped semiconductor material. In some embodiments, the functional portion 405 may be formed by a deposition process or a three-dimensional printing process.

[0046] As shown in Figure 18, in some embodiments, the functional portion 405 may include a first sublayer 405a and a second sublayer 405b. In some embodiments, the first sublayer 405a may be disposed on the first conductive portion 215 and has a first conductivity type. In some embodiments, the second sublayer 405b may be disposed on the first sublayer 405a and has a second conductivity type different from the first conductivity type. In some embodiments, the second sublayer 405b may be disposed between the first sublayer 405a and the second conductive portion 315. For example, the first conductivity type may be N-type and the second conductivity type may be P-type. For example, the first sublayer 405a may be N-type doped silicon and the second sublayer 405b may be P-type doped silicon.

[0047] That is, the first conductive portion 215, the second conductive portion 315, and the functional portion 405 can collectively serve as the second element 25, and the second element 25 can be electrically connected to the source electrode 114 of the first element 10. In this embodiment, the second element 25 can be a PN junction diode. In other embodiments (not shown), the functional portion 405 may include a third sublayer, and the third sublayer may be located between the first sublayer 405a and the second sublayer 405b, and the third sublayer may be an intrinsic semiconductor. In this embodiment, the second element 25 can be a PIN junction diode.

[0048] As shown in Figure 19, in some embodiments, the second element 25 may be an embedded PN junction diode, and the voltage of the second element 25 may be greater than or equal to 20V and less than or equal to 40V, but this disclosure is not limited thereto. Accordingly, the embedded device of this disclosure can improve the electrical performance of a semiconductor device. In detail, the second element 25, as an embedded PN junction diode, can improve switching speed. As shown in Figure 20, in some embodiments, the functional portion 405 in the second element 25 may be disposed on the same layer as the second dielectric layer 300. In some embodiments, the top surface of the functional portion 405 in the second element 25 may be flush with the top surface of the second dielectric layer 300.

[0049] This disclosure forms an embedded semiconductor device by setting a second element in a redistribution structure on a first element. Therefore, external bonding can be omitted. Furthermore, the first and second elements can be simultaneously disposed on the same side of the chip. Accordingly, the embedded device of this disclosure can simultaneously possess the functions of the first and second elements, while reducing the size of the semiconductor device, improving the reliability of the semiconductor device, and / or reducing manufacturing costs. For example, the first element can be a high electron mobility transistor, and the second element can be a capacitor (semiconductor devices 1 and 2), a resistor (semiconductor device 3), a Schottky diode (semiconductor device 4), or a PN junction diode (semiconductor device 5). When the second element is a capacitor, the voltage across a third element, such as a MOSFET, can be reduced to below the MOSFET's breakdown voltage to prevent damage to the MOSFET from high-voltage, high-speed switching operations. When the second element is a resistor or a diode, the switching speed can be increased. Accordingly, the embedded device of this disclosure can improve the electrical performance of the semiconductor device.

[0050] The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand from the content of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same result in the embodiments described herein, and can be used according to this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0051] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0052] This disclosure can be more fully understood from the following detailed description when read in conjunction with the drawings. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced. Figures 1 to 4 are schematic cross-sectional views of different stages of a method for forming a semiconductor device according to an embodiment of this disclosure. Figures 5 and 6 are schematic circuit diagrams of a semiconductor device according to an embodiment of this disclosure. Figures 7 to 9 are perspective views of a semiconductor device according to an embodiment of this disclosure. Figure 10 is an electrode diagram of a semiconductor device according to an embodiment of this disclosure. Figure 11 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure. Figures 12, 13, and 14 are a schematic cross-sectional view, a schematic circuit diagram, and a perspective view of a semiconductor device according to an embodiment of this disclosure, respectively. Figures 15, 16, and 17 are a schematic cross-sectional view, a schematic circuit diagram, and a perspective view of a semiconductor device according to an embodiment of this disclosure, respectively. Figures 18, 19, and 20 are respectively a cross-sectional view, a circuit diagram, and a perspective view of a semiconductor device according to an embodiment of the present disclosure.

Claims

1. A semiconductor device, comprising: A first element includes a gate electrode, a source electrode, and a drain electrode; A first dielectric layer is disposed on the first element; a first metal layer is disposed on the first dielectric layer, electrically connected to the first element, and includes a first conductive portion, wherein the first conductive portion is electrically connected to the source electrode of the first element; a second dielectric layer is disposed on the first metal layer; a second metal layer is disposed on the second dielectric layer and includes a second conductive portion corresponding to the first conductive portion; and a functional portion is located between the first conductive portion and the second conductive portion, wherein the first conductive portion, the second conductive portion, and the functional portion together constitute a second element, and the second element is electrically connected to the source electrode of the first element, wherein the first metal layer further includes a first source contact, and the first source contact is electrically connected to the source electrode; and the second metal layer further includes a second source contact, and the second source contact is electrically connected to the first source contact.

2. The semiconductor device as claimed in claim 1, wherein the functional portion is a portion of the second dielectric layer between the first conductive portion and the second conductive portion.

3. The semiconductor device as claimed in claim 1, wherein the dielectric constant of the functional portion is greater than the dielectric constant of the second dielectric layer.

4. The semiconductor device as claimed in claim 1, wherein the functional portion is made of a conductive material, and the equivalent resistance of the second element is greater than or equal to 0.1 Ω and less than or equal to 10 kΩ.

5. The semiconductor device as claimed in claim 1, wherein the functional portion is a doped semiconductor material.

6. The semiconductor device as claimed in claim 5, wherein the functional portion further includes: A first sublayer is disposed on the first conductive portion and has a first conductivity type; And a second sublayer disposed on the first sublayer, and having a second conductivity type different from the first conductivity type.

7. The semiconductor device as claimed in claim 1, wherein the top surface of the functional portion is coplanar with the top surface of the second dielectric layer.

8. The semiconductor device as claimed in claim 1, wherein the first element further comprises: One substrate; A channel layer is disposed on the substrate; A barrier layer is disposed on the channel layer; wherein the gate electrode, the source electrode and the drain electrode are disposed on the barrier layer.

9. The semiconductor device as claimed in claim 1, wherein: The first metal layer further includes a first gate contact and a first drain contact, the first gate contact being electrically connected to the gate electrode and the first drain contact being electrically connected to the drain electrode; and the second metal layer further includes a second gate contact and a second drain contact, the second gate contact being electrically connected to the first gate contact and the second drain contact being electrically connected to the first drain contact.

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