Semiconductor device and method for forming the same

Abstract

A semiconductor device includes an epitaxial layer, a gate structure, a well, and a source. The epitaxial layer has a first conductivity type. The gate structure is disposed in the epitaxial layer. The well is disposed in the epitaxial layer. The well has a second conductivity type that is different from the first conductivity type. The well has a first bottom surface and a second bottom surface that are connected to each other. The first bottom surface is adjacent to the gate structure. The second bottom surface is disposed on a side of the first bottom surface that is away from the gate structure. A depth of the second bottom surface is greater than a depth of the first bottom surface. The source is disposed above the epitaxial layer and electrically connected to the well.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Previous Technology]

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in electronic devices due to their advantages such as fast switching speed, good high-frequency characteristics, high input impedance, and low drive power. Generally, the on-state resistance of a MOSFET is a crucial parameter affecting its power consumption. MOSFETs with trench gate structures can help reduce on-resistance and decrease device size, increasing chip density and reducing costs. However, the gate structure of trench-gate MOSFETs can lead to a large electric field accumulation effect, reducing the device's breakdown voltage and causing reliability issues. Therefore, developing a semiconductor device and a method for manufacturing such a device to solve these problems is one of the issues that the industry urgently needs to address through research and development. [Summary of the Invention]

[0003] In view of this, one of the objectives of this disclosure is to provide a semiconductor device that can solve the above problems and a method for manufacturing the semiconductor device.

[0004] To achieve the above objectives, according to some embodiments of the present disclosure, a semiconductor device includes an epitaxial layer, a gate structure, a well region, and a source. The epitaxial layer has a first conductivity type. The gate structure is located in the epitaxial layer. The well region is located in the epitaxial layer. The well region has a second conductivity type different from the first conductivity type. The well region has a first bottom surface and a second bottom surface connected together. The first bottom surface is adjacent to the gate structure. The second bottom surface is located on the side of the first bottom surface away from the gate structure. The depth of the second bottom surface is greater than the depth of the first bottom surface. The source is located above the epitaxial layer and electrically connected to the well region.

[0005] According to other embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: forming an epitaxial layer over a substrate, wherein the epitaxial layer has a first conductivity type; performing a first placement process through a hard mask to form a well region in the epitaxial layer, wherein the hard mask has a cross-sectional profile that is narrower at the top and wider at the bottom, such that the well region has a first bottom surface and a second bottom surface connected together, and the depth of the second bottom surface is greater than the depth of the first bottom surface, wherein the well region has a second conductivity type different from the first conductivity type; removing a portion of the epitaxial layer to form a groove to expose the sidewalls of the well region; and forming a gate structure in the groove.

Implementation Method

[0006] Please refer to Figure 1, which is a partial cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. As shown in Figure 1, the semiconductor device 10 includes a substrate 100, an epitaxial layer 110, a well region 120, a source region 130, a heavily doped region 140, a gate structure 150, a source 160, and a drain 170.

[0007] As shown in Figure 1, the epitaxial layer 110 is located on the substrate 100. The well region 120 is located within the epitaxial layer 110. The source doped region 130 and the heavily doped region 140 are located within the epitaxial layer 110 and above the well region 120. The gate structure 150 includes a dielectric layer 152, a gate electrode 154, and a dielectric layer 156, all located within the epitaxial layer 110. The source doped region 130 is adjacent to the gate structure 150. The heavily doped region 140 is located on the side of the source doped region 130 away from the gate structure 150.

[0008] Source 160 is formed above the top surface 110a of epitaxial layer 110. Source 160 is in contact with source doped region 130 and is located above heavily doped region 140. Source 160 is electrically connected to well region 120. Drain 170 is formed below substrate 100. Source 160 and drain 170 comprise conductive metal.

[0009] In some embodiments, the substrate 100, the epitaxial layer 110, and the source doped region 130 have a first conductivity type. For example, the substrate 100, the epitaxial layer 110, and the source doped region 130 include an n-type semiconductor layer. In some embodiments, the doping concentration of the source doped region 130 is greater than the doping concentration of the epitaxial layer 110. For example, the doping concentration of the substrate 100 is between 10 × 14 g / cm³ and 10 × 15 g / cm³, the doping concentration of the epitaxial layer 110 is between 10 × 15 g / cm³ and 5 × 10 × 16 g / cm³, and the doping concentration of the source doped region 130 is between 10 × 19 g / cm³ and 10 × 21 g / cm³. The epitaxial layer 110 may be formed as a drift region of the semiconductor device 10.

[0010] In some embodiments, well region 120 and heavily doped region 140 have a second conductivity type different from the first conductivity type. For example, well region 120 and heavily doped region 140 include a p-type semiconductor layer. The doping concentration of heavily doped region 140 is greater than that of well region 120. Well region 120 is also referred to as a lightly doped region. For example, the doping concentration of well region 120 is between 10 11 μm / cm³ and 10 14 μm / cm³, and the doping concentration of heavily doped region 140 is between 10 19 μm / cm³ and 10 21 μm / cm³. The maximum depth of well region 120 is depth D1, and the heavily doped region 140 has a depth D2. Depth D1 is greater than depth D2. In some embodiments, depth D1 is greater than 1 micrometer. It is worth noting that the term "depth" here is based on the top surface 110a of epitaxial layer 110.

[0011] As previously described, the gate structure 150 includes a dielectric layer 152, a gate electrode 154, and a dielectric layer 156. In some embodiments, the dielectric layer 152 and dielectric layer 156 may include, for example, silicon dioxide (SiO2). The gate electrode 154 may include a polycrystalline silicon gate or a conductive metal. In some embodiments, the depth D3 of the gate structure 150 is greater than 1 micrometer, and the width W3 of the gate structure 150 is between 0.6 micrometers and 1 micrometer. In some embodiments, the thickness T1 of the dielectric layer 152 is 0.5 micrometers.

[0012] In order to improve the reliability of semiconductor devices, in some embodiments disclosed herein, the doping depth of the well region 120 is increased to prevent electric field accumulation at the edge of the gate structure 150 (the corner of the bottom surface 150a), thereby increasing the breakdown voltage and reducing the on-resistance.

[0013] Therefore, as shown in Figure 1, well region 120 has a first portion 122 and a second portion 124 connected together. The first portion 122 is adjacent to and in contact with gate structure 150. The first portion 122 has a first bottom surface 122a. The first bottom surface 122a is adjacent to gate structure 150. As shown in Figure 1, the first bottom surface 122a is inclined relative to the top surface of substrate 100. In some embodiments, the first bottom surface 122a extends downward from one edge (or corner point) of bottom surface 150a of gate structure 150 in a direction away from gate structure 150. In some embodiments, the width W2 of the first bottom surface 122a is less than 0.3 micrometers. In some embodiments, the first portion 122 and the first bottom surface 122a are located below source doped region 130.

[0014] The second portion 124 is located on the side of the first portion 122 away from the gate structure 150. The second portion 124 has a second bottom surface 124a connected to the first bottom surface 122a. The second bottom surface 124a is located on the side of the first bottom surface 122a away from the gate structure 150. The depth D1 of the second bottom surface 124a is greater than the depth of the first bottom surface 122a. In some embodiments, the width W1 of the second bottom surface 124a is between 0.4 micrometers and 1 micrometer. As shown in Figure 1, the second bottom surface 124a is a horizontal plane parallel to the top surface of the substrate 100. In some embodiments, the second portion 124 and the second bottom surface 124a are located below the heavily doped region 140.

[0015] In some embodiments, the minimum depth of the first bottom surface 122a is equal to the depth D3 of the bottom surface 150a, and the maximum depth of the first bottom surface 122a is equal to the depth D1 of the second bottom surface 124a. In other words, the depth D1 of the second bottom surface 124a and the depth of the first bottom surface 122a are both greater than the depth D3 of the bottom surface 150a, and the gate structure 150 is laterally surrounded by the well area 120.

[0016] Please refer to Figures 2 and 3, which are partial cross-sectional views of an intermediate stage of the method for manufacturing semiconductor element 10.

[0017] First, as shown in Figure 2, an epitaxial layer 110 is formed above the substrate 100. Next, a first ion implantation process is performed using a hard mask 200 to form a well region 120 in the epitaxial layer 110. The hard mask 200 has a cross-sectional profile that is narrower at the top and wider at the bottom, such that the well region 120 has a first portion 122 and a second portion 124, wherein the depth of the first bottom surface 122a of the first portion 122 is less than the depth of the second bottom surface 124a of the second portion 124.

[0018] For example, the hard mask 200 has a trapezoidal cross-sectional profile as shown in Figure 2. Portion 200a of the hard mask 200 has a uniform thickness, while the thickness of portion 200b of the hard mask 200 gradually decreases away from portion 200a. In some embodiments, the lower base length of the trapezoidal cross-sectional profile of the hard mask 200 is between 0.5 micrometers and 5 micrometers. The thickness of the hard mask 200 is set such that the ion beam can be blocked by portion 200a and partially blocked by portion 200b. Therefore, after the first ion implantation process, the portion of the epitaxial layer 110 below portion 200a remains unchanged, the portion of the epitaxial layer 110 below portion 200b forms the first portion 122, and the portion of the epitaxial layer 110 not covered by the hard mask 200 forms the second portion 124. In some embodiments, the doping concentration of the first portion 122 is less than the doping concentration of the second portion 124.

[0019] Further, as shown in the inset of Figure 2, the hard mask 200, which is narrower at the top and wider at the bottom, can be formed by overlapping multiple material layers of different widths and comprising different materials. For example, the hard mask 200 includes, from bottom to top, material layer 202a, material layer 204a, material layer 202b, material layer 204b, material layer 202c, material layer 204c, material layer 202d, material layer 204d, material layer 202e, material layer 204e, material layer 202f, and material layer 204f. Among them, material layers 202a, 202b, 202c, 202d, 202e, and 202f comprise oxides, while material layers 204a, 204b, 204c, 204d, 204e, and 204f comprise nitrides. In some embodiments, two adjacent material layers may have flush end faces. For example, material layer 204e and material layer 202f have flush end faces, material layer 204d and material layer 202e have flush end faces, and so on. Adjacent non-flush end faces may have the same spacing d, for example, the end faces of material layer 204f and material layer 202f have a spacing d, and the end faces of material layer 204e and material layer 202e have a spacing d, as shown in the inset of Figure 2. In some embodiments, the spacing d is between 0.08 micrometers and 0.1 micrometers.

[0020] Since the hard mask 200 has a stepped portion 200b, the first bottom surface 122a of the formed first portion 122 is also stepped. The smaller the spacing d, the closer the first bottom surface 122a is to a smooth slope or arc surface. Specifically, the first bottom surface 122a is formed by multiple connected horizontal and vertical portions, as shown in the illustration in Figure 2. The depth of these horizontal portions is less than the depth of the second bottom surface 124a of the second portion 124. For example, as shown in the illustration in Figure 2, the depths of the horizontal portions 122a1 and 122a2 of the first bottom surface 122a are both less than the depth of the second bottom surface 124a of the second portion 124.

[0021] After forming the well region 120, as shown in Figure 3, a second ion implantation process is performed to form a source doped region 130 in the epitaxial layer 110 and above the first portion 122 and the first bottom surface 122a of the well region 120. Next, a third ion implantation process is performed to form a heavily doped region 140 in the epitaxial layer 110 and above the second portion 124 and the second bottom surface 124a of the well region 120.

[0022] Next, a portion of the epitaxial layer 110 is removed to form a groove T that exposes the sidewall 122b of the first portion 122 of the well region 120. In some embodiments, the groove T further exposes the sidewall 130b of the source doped region 130. It is worth noting that the bottom depth of the groove T may be equal to the minimum depth of the first bottom surface 122a. For example, the bottom depth of the groove T is equal to the depth of the horizontal portion 122a1 of the first bottom surface 122a (see the illustration in Figure 2).

[0023] Next, a gate structure 150 is formed in the recess T. For example, in some embodiments, a dielectric material is first conformally deposited in the recess T and on the top surface of the source doped region 130 and the heavily doped region 140. Next, a gate electrode material is deposited to further fill the recess T and completely cover the dielectric material. Next, a planarization process is performed, for example by chemical mechanical polishing (CMP), to remove the portions of the dielectric material and the gate electrode material above the source doped region 130 and the heavily doped region 140, so as to expose the top surfaces of the source doped region 130 and the heavily doped region 140, and to make the top surfaces of the formed dielectric layer 152 and the gate electrode 154 flush with the top surfaces of the source doped region 130 and the heavily doped region 140. Next, dielectric material is deposited again to cover the source doped region 130, the heavily doped region 140, the dielectric layer 152, and the gate electrode 154, so as to encapsulate the gate electrode 154. Next, multiple portions of the dielectric material are removed to form a dielectric layer 156, at least partially exposing the top surfaces of the source doped region 130 and the heavily doped region 140. Dielectric layers 152 and 156 can be collectively referred to as the gate dielectric layer. The gate structure 150 formed in the recess T contacts the first portion 122 of the well region 120 and the source doped region 130.

[0024] Finally, a source 160 is formed above the source doped region 130 and the heavily doped region 140. The source 160 is electrically connected to the well region 120. At the same time, a drain 170 is formed below the substrate 100. The resulting semiconductor device structure, as shown in semiconductor device 10 in Figure 1, is a vertical MOSFET with a trench gate structure and bilateral symmetry.

[0025] Please refer to Figure 4, which is a partial cross-sectional view of a semiconductor element 20 according to some other embodiments of the present disclosure. As shown in Figure 4, the difference between semiconductor element 20 and semiconductor element 10 is that the first bottom surface 122a of the first portion 122 of semiconductor element 20 extends from the sidewall 150b of gate structure 150 to a bottom surface 150a below gate structure 150 and connects to the second bottom surface 124a of the second portion 124. Meanwhile, the first bottom surface 122a is concave upward arc-shaped. This can shorten the longitudinal channel region below gate structure 150 and improve electron mobility. In some embodiments, the width W2 of the first bottom surface 122a is less than 0.3 micrometers, and the width W1 of the second bottom surface 124a is between 0.2 micrometers and 0.5 micrometers. The depth and contour variations of the first bottom surface 122a and the second bottom surface 124a of the semiconductor element 20 can be achieved by adjusting the spacing d and thickness between the end faces of the material layer of the hard mask 200. In some embodiments, the first bottom surface 122a is at least partially higher than the bottom surface 150a of the gate structure 150. In other words, the epitaxial layer 110 is partially located between the first portion 122a and the gate structure 150.

[0026] Please refer to Figures 5 and 6, which are partial cross-sectional views of a semiconductor element 30 according to some other embodiments of the present disclosure and a partial cross-sectional view of an intermediate stage of a method for manufacturing the semiconductor element 30, respectively. As shown in Figure 5, the difference between semiconductor element 30 and semiconductor element 20 is that semiconductor element 30 further includes a heavily doped region 180 having a second conductivity type. The heavily doped region 180 is located below the gate structure 150 and contacts the bottom surface 150a of the gate structure 150. The depth D4 of the bottom surface 180a of the heavily doped region 180 is greater than the depth D1 of the second bottom surface 124a. In some embodiments, the thickness T2 of the heavily doped region 180 is greater than 0.5 micrometers. In some embodiments, the thickness T2 of the heavily doped region 180 is greater than the thickness T1 of the dielectric layer 152. In some embodiments, the doping concentration of the heavily doped region 180 is greater than the doping concentration of the well region 120. For example, the doping concentration of the heavily doped region 180 is between 1019 / cm3 and 1021 / cm3. By setting the heavily doped region 180 as a shielding region, the on-resistance can be further reduced. In some embodiments, the heavily doped region 180 is separated from the well region 120, as shown in Figure 5. In other embodiments, the heavily doped region 180 is in contact with the well region 120. In some embodiments, the heavily doped region 180 may also be disposed below the gate structure 150 of the semiconductor element 10 to achieve a similar purpose.

[0027] Accordingly, the method of manufacturing semiconductor device 30 further includes performing a fourth ion implantation process to form a heavily doped region 180. Next, as shown in Figure 6, a recess T is formed to expose the sidewalls 110b of the epitaxial layer 110, the sidewalls 122b of the first portion 122, the sidewalls 130b of the source doped region 130, and the top surface 180b of the heavily doped region 180. Therefore, the gate structure 150 formed in the recess T contacts the epitaxial layer 110, the first portion 122, the source doped region 130, and the heavily doped region 180.

[0028] Please refer to Figure 7, which is a partial cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor element 10 according to some embodiments of the present disclosure. Figure 7 illustrates a schematic diagram of forming a hard mask 200. The process of forming the hard mask 200 will be described in detail below.

[0029] First, a plurality of material layers, including material layers 202a to 202f and material layers 204a to 204f, are alternately and completely cover the epitaxial layer 110. In some embodiments, material layers 202a to 202f comprise oxides, while material layers 204a to 204f comprise nitrides.

[0030] Next, the photoresist 300 is positioned to completely cover the material layer, such as material layer 204f. Then, a mask 400 is positioned above the photoresist 300 with its end face at position P1. Next, exposure and development are performed so that the end face of the retained photoresist 300 is aligned with the end face of the mask 400 at the dashed line at position P1 in Figure 7. In this way, the portion of material layer 204f to the right of the dashed line at position P1 is exposed through the photoresist 300.

[0031] Next, etching is performed using photoresist 300 to remove the exposed portions of material layer 204f. In some embodiments, process conditions with a high etch selectivity for nitrides and oxides are selected to use material layer 202f as an etch stop layer. The etched end face of material layer 204f is aligned with the dashed line at position P1. Simultaneously, the portion of material layer 202f to the right of the dashed line at position P1 is exposed.

[0032] Next, etching is performed using photoresist 300 to remove the exposed portions of material layer 202f. Similarly, process conditions with a high etch selectivity for nitrides and oxides are selected to use material layer 204e as an etch stop layer. The end face of the etched material layer 202f is flush with the end face of material layer 204f at the dashed line at position P1. At the same time, the portion of material layer 204e to the right of the dashed line at position P1 is exposed.

[0033] Next, the mask 400 is moved to the left by a distance d. Then, exposure and development are performed so that the end face of the retained photoresist 300 is aligned with the end face of the moved mask 400. At the same time, a portion of the material layer 204f is exposed through the photoresist 300 and has a length equivalent to the distance d.

[0034] Next, etching is performed using photoresist 300 to remove the exposed portions of material layers 204f and 204e. The end face of the etched material layer 204f is aligned with the end face of the moved mask 400. The end face of the etched material layer 204e is aligned with the end face of material layer 202f. Meanwhile, material layer 202f has a portion exposed with a length equivalent to the spacing d, while material layer 202e is exposed to the right of the dashed line at position P1.

[0035] Next, etching is performed using photoresist 300 to remove the exposed portions of material layers 202f and 202e. The end face of the etched material layer 202f is flush with the end face of material layer 204f. The end face of the etched material layer 202e is flush with the end face of material layer 204e. Meanwhile, material layer 204e has a portion exposed with a length equivalent to the spacing d, while material layer 204d is exposed to the right of the dashed line at position P1.

[0036] Next, the mask 400 is moved to the left by a distance d again. Then, exposure and development are performed so that the end face of the retained photoresist 300 is aligned with the end face of the moved mask 400. At the same time, the material layer 204f again has a portion exposed through the photoresist 300 with a length equivalent to the distance d.

[0037] Next, etching is performed using photoresist 300 to remove the exposed portions of material layers 204f, 204e, and 204d. The end face of the etched material layer 204f is aligned with the end face of the moved mask 400. The end face of the etched material layer 204e is aligned with the end face of material layer 202f. The end face of the etched material layer 204d is aligned with the end face of material layer 202e. Meanwhile, material layers 202f and 202e each have a portion exposed with a length equivalent to the spacing d, while material layer 202d is exposed to the right of the dashed line at position P1.

[0038] Next, etching is performed using photoresist 300 to remove the exposed portions of material layers 202f, 202e, and 202d. The end face of the etched material layer 202f is aligned with the end face of material layer 204f. The end face of the etched material layer 202e is aligned with the end face of material layer 204e. The end face of the etched material layer 202d is aligned with the end face of material layer 204d. Meanwhile, material layers 204e and 204d each have an exposed portion with a length equivalent to the spacing d, while material layer 204c is exposed to the right of the dashed line at position P1.

[0039] Similarly, by moving the mask 400 and alternately etching nitrides and oxides, the underlying material layer is gradually exposed, forming a stepped shape. Since the distance the mask 400 moves each time is a spacing d, there will also be a spacing d between adjacent uneven end faces.

[0040] Thus, when the end face of the mask 400 is moved to position P2, the end face of the etched material layer 202f is aligned with the end face of the etched material layer 204f. The end face of the etched material layer 202e is aligned with the end face of the etched material layer 204e. The end face of the etched material layer 202d is aligned with the end face of the etched material layer 204d. The end face of the etched material layer 202c is aligned with the end face of the etched material layer 204c. The end face of the etched material layer 202b is aligned with the end face of the etched material layer 204b. The end face of the etched material layer 202a is aligned with the end face of the etched material layer 204a. Meanwhile, material layers 204e, 204d, 204c, 204b and 204a each have a portion exposed with a length equivalent to the spacing d, while the epitaxial layer 110 is exposed to the right of the dashed line at position P1.

[0041] Next, after moving the mask 400 to position P2, exposure and development are performed so that the end face of the retained photoresist 300 is aligned with the end face of the moved mask 400 at the dashed line of position P2. At the same time, the material layer 204f again has a portion exposed with a length equivalent to the spacing d.

[0042] Finally, etching is performed using photoresist 300 to remove the exposed portions of material layers 204f, 204e, 204d, 204c, 204b, and 204a, thus forming the structure shown in Figure 7. Performing the aforementioned operation on the other end of the material layers yields a hard mask 200 that is narrower at the top and wider at the bottom, as shown in Figure 2.

[0043] From the detailed description of the specific embodiments disclosed above, it is evident that in the semiconductor device and the method for manufacturing the semiconductor device disclosed herein, by increasing the doping depth of the well region, the electric field accumulation at the edge of the gate structure can be reduced. Furthermore, by performing ion implantation through a hard mask that is narrow at the top and wide at the bottom, the formed well region has a first bottom surface and a second bottom surface, wherein the first bottom surface extends downward from the gate structure and connects to the deeper second bottom surface, so that the sidewalls of the gate structure are surrounded by the well region. Therefore, the breakdown voltage of the semiconductor device can be improved, and the on-resistance can be reduced. [Simplified Explanation of the Diagram]

[0044] The figures illustrate one or more embodiments of the present disclosure and, together with the written description, serve to explain the principles of the present disclosure. Wherein: Figure 1 is a partial cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figures 2 and 3 are partial cross-sectional views illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 4 is a partial cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure. Figure 5 is a partial cross-sectional view illustrating a semiconductor device according to yet another embodiment of the present disclosure. Figure 6 is a partial cross-sectional view illustrating an intermediate stage of a method for manufacturing a semiconductor device according to yet another embodiment of the present disclosure. Figure 7 is a partial cross-sectional view illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Biomaterial Storage]

[0046] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device comprising: an epitaxial layer having a first conductivity type; a gate structure located in the epitaxial layer; a well region located in the epitaxial layer and having a second conductivity type different from the first conductivity type, wherein the well region has a first bottom surface and a second bottom surface connected together, the first bottom surface being adjacent to the gate structure, the second bottom surface being located on the side of the first bottom surface away from the gate structure, and a depth of the second bottom surface being greater than a depth of the first bottom surface, wherein the depth of the first bottom surface is greater than a depth of a bottom surface of the gate structure; and a source located above the epitaxial layer and electrically connected to the well region.

2. The semiconductor device as claimed in claim 1 further comprises: a source doped region located in the epitaxial layer, adjacent to the gate structure and in contact with the source; and a first heavily doped region located in the epitaxial layer and on the side of the source doped region away from the gate structure, wherein the first bottom surface of the well region is located below the source doped region, and the second bottom surface of the well region is located below the first heavily doped region.

3. The semiconductor device as claimed in claim 1 further comprises: a second heavily doped region located below the gate structure and in contact with the bottom surface of the gate structure, wherein a depth of a bottom surface of the second heavily doped region is greater than the depth of the second bottom surface of the well region.

4. A semiconductor device comprising: an epitaxial layer having a first conductivity type; a gate structure located in the epitaxial layer; a well region located in the epitaxial layer and having a second conductivity type different from the first conductivity type, wherein the well region has a first bottom surface and a second bottom surface connected together, the first bottom surface being adjacent to the gate structure, the second bottom surface being located on the side of the first bottom surface away from the gate structure, and a depth of the second bottom surface being greater than a depth of the first bottom surface, wherein the first bottom surface extends from an edge of a bottom surface of the gate structure; and a source located above the epitaxial layer and electrically connected to the well region.

5. The semiconductor device as claimed in claim 4 further comprises: a source doped region located in the epitaxial layer, adjacent to the gate structure and in contact with the source; and a first heavily doped region located in the epitaxial layer and on the side of the source doped region away from the gate structure, wherein the first bottom surface of the well region is located below the source doped region, and the second bottom surface of the well region is located below the first heavily doped region.

6. The semiconductor device as claimed in claim 4 further comprises: a second heavily doped region located below the gate structure and in contact with the bottom surface of the gate structure, wherein a depth of a bottom surface of the second heavily doped region is greater than the depth of the second bottom surface of the well region.

7. A method of manufacturing a semiconductor device, comprising: forming an epitaxial layer over a substrate, wherein the epitaxial layer has a first conductivity type; performing a first placement process through a hard mask to form a well region in the epitaxial layer, wherein the hard mask has a cross-sectional profile that is narrower at the top and wider at the bottom, such that the well region has a first bottom surface and a second bottom surface connected together, and a depth of the second bottom surface is greater than a depth of the first bottom surface, wherein the well region has a second conductivity type different from the first conductivity type; removing a portion of the epitaxial layer to form a groove to expose a sidewall of the well region; and forming a gate structure in the groove, wherein the depth of the first bottom surface is greater than a depth of a bottom surface of the gate structure.

8. The method as described in claim 7, further comprising: performing a second implantation process to form a source doped region having the first conductivity type in the epitaxial layer and located above the first bottom surface of the well region; and performing a third implantation process to form a first heavily doped region having the second conductivity type in the epitaxial layer and located above the second bottom surface of the well region.

9. The method as described in claim 7, further comprising: performing a fourth implantation process to form a second heavily doped region having the second conductivity type below the gate structure and in contact with the bottom surface of the gate structure, wherein a depth of a bottom surface of the second heavily doped region is greater than the depth of the second bottom surface of the well region.

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