Semiconductor device and method of forming the same

Abstract

One aspect of the present pertains to a semiconductor device including a substrate, a first well and a second well adjacently disposed in the substrate and having opposite doping types, a gate structure spanning the first well and the second well, a source structure disposed in the first well, a drain structure disposed in the second well, and an ohmic contact layer disposed on the second well to form an ohmic contact with the second well. The ohmic contact layer is disposed between the gate structure and the drain structure. A method for forming the semiconductor device is also provided.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a semiconductor device having an ohmic contact layer and a method for forming the same. Prior Technology

[0002] Laterally diffused metal-oxide semiconductor (LDMOS) devices are metal-oxide semiconductor power transistors that contain a drift region between the gate and drain regions. The drift region is a lightly doped region with a lower doping concentration than the source and drain regions, used to avoid or suppress the high electric field between the source and drain regions. Because LDMOS devices are suitable for transmitting high-frequency and high-power electrical signals, they are widely used in high-voltage power applications.

[0003] On-state resistance (Ron) is a crucial parameter for LDMOS devices, directly proportional to their power consumption. With increasing demands for energy efficiency and improved performance in electronic devices, manufacturers continuously seek methods to reduce leakage current and on-state resistance in LDMOS devices. While it has been observed that increasing the doping concentration in the drift region reduces the on-state resistance of conventional LDMOS devices, this reduction typically also lowers the off-state breakdown voltage (VBD), improving the reliability of the semiconductor device. Therefore, although existing LDMOS devices generally meet various requirements, they are not entirely satisfactory and require further improvement. Summary of the Invention

[0004] In view of this, it is necessary to provide an improved semiconductor device and its fabrication method to reduce on-resistance without adversely affecting breakdown voltage.

[0005] One aspect disclosed herein relates to a semiconductor device. The semiconductor device includes: a substrate; a first well region and a second well region, adjacent to each other and disposed in the substrate and having opposite doping modes; a gate structure spanning the first well region and the second well region; a source structure disposed in the first well region; a drain structure disposed in the second well region; and an ohmic contact layer disposed on the second well region and forming an ohmic contact with the second well region, wherein the ohmic contact layer is disposed between the gate structure and the drain structure.

[0006] Another aspect of this disclosure relates to a method for forming a semiconductor device. The method includes: providing a substrate having adjacent, juxtaposed first and second well regions with opposite doping patterns; forming a gate structure spanning the first and second well regions; forming a source structure in the first well region; forming a drain structure in the second well region; and forming an ohmic contact layer on the second well region to form an ohmic contact with the second well region, wherein the ohmic contact layer is disposed between the gate structure and the drain structure. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. It should also be noted that the accompanying drawings only illustrate typical embodiments of this disclosure and should not be considered as limiting its scope; this disclosure is equally applicable to other embodiments. Figure 1 is a cross-sectional view illustrating the formation of a semiconductor device according to some embodiments disclosed herein. Figure 2 shows the current-voltage (IV) curve obtained by electrical simulation using computer-aided design (TCAD). Figures 3 through 10 are flowcharts illustrating a method for forming a semiconductor device according to some embodiments of the present disclosure. Implementation

[0008] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements so that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0011] The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0012] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. The packaging structure may add additional components. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0013] For ease of explanation, embodiments of the present invention will be described below using a laterally diffused metal oxide semiconductor (LDMOS) device, but the embodiments of the present invention are not limited thereto. Some embodiments of the present invention can also be applied to other types of metal oxide semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) devices, extended-drain metal oxide semiconductor (EDMOS) devices, or similar metal oxide semiconductor devices. Furthermore, the present invention can also be applied to other types of semiconductor devices, such as diodes, insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), or other similar semiconductor devices.

[0014] To address the shortcomings of prior art, this disclosure provides a semiconductor device and a method for forming the same. This semiconductor device includes an ohmic contact layer located between a gate structure and a drain structure. The ohmic contact layer is situated on a second well region (e.g., a drift region) and forms an ohmic contact with the second well region, causing current in the second well region to concentrate near the surface, thereby reducing the on-resistance (Ron) and maintaining or increasing the off-state breakdown voltage (VBD), thus improving the reliability of the semiconductor device.

[0015] Figure 1 is a cross-sectional view illustrating the formation of a semiconductor device 100 according to some embodiments of the present disclosure. Referring to Figure 1, the semiconductor device 100 includes a substrate 110. The substrate 110 may be a semiconductor substrate, the material of which includes elemental semiconductors, such as silicon (Si) and / or germanium (Ge); compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP), or combinations thereof. Furthermore, the substrate 110 may also be a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 110 may have a first conductivity type, such as a P-type substrate.

[0016] Furthermore, the semiconductor device 100 includes a first well region 112 and a second well region 114. These well regions are adjacent to each other and disposed in the substrate 110 and close to the top surface of the substrate 110. The first well region 112 and the second well region 114 have opposite doping types; for example, when the substrate 110 has a first conductivity type (e.g., P-type), the first well region 112 has a first conductivity type (e.g., P-type), and the second well region 114 has a second conductivity type (e.g., N-type). The first well region 112 may be referred to as the body region, and the second well region 114 may be referred to as the drift region. In some embodiments, the first well region 112 (body region) is adjacent to the second well region 114 (drift region), and the first well region 112 and the second well region 114 are in direct contact.

[0017] In some other embodiments, the first conductivity type may be N-type, and the second conductivity type may be P-type. The P-type dopant may contain boron (B), gallium (Ga), aluminum (Al), indium (In), boron trifluoride (BF3) ions, or combinations thereof. The N-type dopant may contain phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb) ions, or combinations thereof. Since the doping concentration of the first well region 112 (body region) is at least 100 times that of the second well region 114 (drift region), the depletion region at the junction of the first well region 112 and the second well region 114 primarily extends into the second well region 114 (drift region) and does not diffuse into the channel region formed within the first well region 112 (body region). In some embodiments, the doping concentration of the first well region 112 is approximately 1E16 atoms / cm3 to approximately 1E18 atoms / cm3. The doping concentration in the second well region 114 is approximately 1E15 atoms / cm³ to approximately 1E17 atoms / cm³.

[0018] Referring again to Figure 1, the semiconductor device 100 includes a gate structure 120. The gate structure 120 is disposed across a first well region 112 and a second well region 114. In some embodiments, the gate structure 120 may include a gate dielectric layer 120a located on the first well region 112 and the second well region 114, and a gate electrode 120b located on the gate dielectric layer 120a.

[0019] In some embodiments, the gate dielectric layer 120a may comprise one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In other embodiments, the gate dielectric layer 120a may comprise metal oxides, metal nitrides, metal silicates, metal aluminates, zirconium silicates, zirconium aluminates, or combinations thereof, but this disclosure is not limited thereto. The material of the gate electrode 120b may include conductive materials, such as doped semiconductors, metals, or metal nitrides. For example, the doped semiconductor may be doped polycrystalline silicon or doped polycrystalline germanium; the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or the aforementioned multilayer structure; the metal nitride may be molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), or similar materials.

[0020] In some embodiments, the gate structure 120 further includes sidewall spacers 121. As shown in Figure 1, the sidewall spacers 121 are disposed on the sidewalls on both sides of the gate dielectric layer 120a and the gate electrode 120b. The sidewall spacers 121 include one or more layers of insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), or silicon oxycarbide (SiCN).

[0021] Referring again to Figure 1, the semiconductor device 100 includes a source structure 124 located in a first well region 112 and a drain structure 122 located in a second well region 114. The drain structure 122 and the second well region 114 have the same doping type of dopant, and the doping concentration of the drain structure 122 is greater than that of the second well region 114. In some embodiments, the doping concentration of the drain structure 122 is about 1E20 atoms / cm³ to about 1E22 atoms / cm³. The source structure 124 may include a first doped region 124a and a second doped region 124b adjacent to each other and having opposite doping types; for example, the first doped region 124a may be N-type and the second doped region 124b may be P-type. In some other embodiments, the first doped region 124a may be P-type and the second doped region 124b may be N-type. The doping concentrations of the first doped region 124a and the second doped region 124b are approximately 1E20 atoms / cm³ to approximately 1E22 atoms / cm³.

[0022] Furthermore, the semiconductor device 100 also includes an ohmic contact layer 132. As shown in Figure 1, the ohmic contact layer 132 is disposed on the second well region 114 and located between the gate structure 120 and the drain structure 122. An ohmic contact is formed between the ohmic contact layer 132 and the second well region 114, which allows the current in the second well region 114 to concentrate near the surface of the second well region 114, thereby reducing the on-resistance (Ron). Moreover, since the surface electric field can be more uniformly distributed, a better charge balance can be obtained, thus maintaining or increasing the off-state breakdown voltage (VBD), thereby improving the reliability of the semiconductor device 100. It should be noted that in this embodiment, the ohmic contact layer 132 does not contact the gate structure 120 or the drain structure 122. If the ohmic contact layer 132 contacts the gate structure 120, it may cause a short circuit in the gate structure 120, thereby reducing the breakdown voltage. On the other hand, if the ohmic contact layer 132 contacts the drain structure 122, it may form a Schottky contact, also resulting in a reduction in the breakdown voltage. In some embodiments, the width W of the ohmic contact layer 132 may be from about 2 micrometers to about 80 micrometers, but this disclosure is not limited to this, as long as the ohmic contact layer 132 does not contact the gate structure 120 or the drain structure 122.

[0023] As shown in Figure 1, the ohmic contact layer 132 may include a silica layer 132a in direct contact with the second well region 114 and a metal layer 132b stacked on the silica layer 132a. The silica layer 132a is made of a metal material that forms an ohmic contact with semiconductor materials, thus the silica layer 132a can form an ohmic contact with the second well region 114. In some embodiments, the metal layer 132b may be a floating metal layer; in other words, the ohmic contact layer 132 is not connected to any potential or circuit node, thereby avoiding affecting the voltage difference between the gate structure 120 and the drain structure 122.

[0024] In some embodiments, the silicate layer 132a may include a metal silicate, such as tungsten silicate, titanium silicate, cobalt silicate, nickel silicate, platinum silicate, erbium silicate, or a combination thereof. The metal layer 132b may include a metallic material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or the aforementioned multilayer structure. In some embodiments, the ohmic contact layer 132 has a thickness of about 1 nanometer to 20 nanometers, within which the on-resistance can be effectively reduced and the current density increased.

[0025] Referring again to Figure 1, the semiconductor device 100 may include an interlayer dielectric layer 140. The interlayer dielectric layer 140 is disposed on the substrate 110 and covers the gate structure 120, the source structure 124, the drain structure 122, and the ohmic contact layer 132. The interlayer dielectric layer 140 may contain one or more dielectric materials, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), tetraethoxysilane (TES) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, or other suitable dielectric materials.

[0026] Furthermore, the semiconductor device 100 may include a drain contact 142 and a source contact 144 (including a first source contact 144a and a second source contact 144b) that pass through the interlayer dielectric layer 140 and are electrically connected to the drain structure 122 and the source structure 124, respectively. In some embodiments, the first source contact 144a and the second source contact 144b are each electrically connected to the first doped region 124a and the second doped region 124b. The drain contact 142 and the source contact 144 may each include a barrier layer (not shown) and a conductive material surrounded by the barrier layer. The barrier layer can be used to prevent the conductive material from diffusing into the interlayer dielectric layer 140. The material of the barrier layer may include titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), nitride (WN), other suitable materials, or combinations thereof. Conductive materials include metals (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh)), alloys of the aforementioned metals, polycrystalline silicon, other suitable conductive materials, or combinations thereof.

[0027] In some embodiments, as shown in Figure 1, the gate structure 120 and the drain contact 142 are separated by a first minimum distance D1, and the gate structure 120 and the ohmic contact layer 132 are separated by a second minimum distance D2. The ratio of the second minimum distance D2 to the first minimum distance D1 is greater than about 0.3. If the ratio is less than about 0.3, the gate structure 120 may be short-circuited, resulting in a decrease in breakdown voltage. On the other hand, if the ratio is greater than about 0.3, the ohmic contact layer 132 may cover and contact the drain structure 122, forming a Schottky contact, which also leads to a decrease in breakdown voltage. In some embodiments, the first minimum distance D1 is less than about 3 micrometers, which allows for miniaturization of the semiconductor device 100. The first minimum distance D1 is greater than the width W of the ohmic contact layer 132, which prevents the ohmic contact layer 132 from contacting the gate structure 120 and / or the drain structure 122.

[0028] In some embodiments, the semiconductor device 100 may include a self-aligned metal silicide 134 disposed on the surfaces of the gate structure 120, the source structure 124, and the drain structure 122, respectively. The self-aligned metal silicide 134 is formed on the surfaces of the gate structure 120, the source structure 124, and the drain structure 122 in a self-aligned manner to improve conductivity and reduce contact resistance. According to some embodiments of this disclosure, the self-aligned metal silicide 134 is made of a metallic material that forms ohmic contacts with the semiconductor material, thus forming ohmic contacts with the gate structure 120, the source structure 124, and the drain structure 122.

[0029] In some embodiments, the semiconductor device 100 optionally includes a resist protective oxide (RPO) layer 130. The resist protective oxide layer 130 extends between the gate structure 120 and the drain structure 122, and an ohmic contact layer 132 is disposed on the second well region 114 through the resist protective oxide layer 130. As shown in Figure 1, the resist protective oxide layer 130 further extends to cover the sidewall spacers 121, but this disclosure is not limited thereto. In other embodiments, the resist protective oxide layer 130 does not cover the sidewall spacers 121. The resist protective oxide layer 130 may serve as a silicide barrier layer to protect the region beneath (e.g., the second well region 114 and the drain structure 122) from silicide formation during the formation of the self-aligned metal silicide 134. In some embodiments, the material of the resist protective oxide layer 130 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0030] The following describes the test results of some semiconductor devices disclosed herein. Electrical simulations were performed on a comparative example (without an ohmic contact layer) and an experimental example (with an ohmic contact layer 132) of the semiconductor devices using Synopsys' technology computer-aided design (TCAD) software suite, Sentaurus. The experimental example is an illustration of the semiconductor device 100 shown in Figure 1. Design features and simulated electrical parameters are shown in Table 1, and the simulated current-voltage curves are shown in Figure 2. In Figure 2, curve 202 represents the current-voltage curve of the comparative example, and curve 204 represents the current-voltage curve of the experimental example.

[0031] [Table 1] Comparative example Experimental Example Distance A (μm) 1.6 1.6 Distance B (μm) X 0.5 Width C (μm) X 0.5 Critical voltage (V) 1.27 1.27 On-resistance (mOhm*mm²) 11.69 10.51 Shutdown crash voltage (V) 21.8 22.4

[0032] In Table 1, distance A is defined as the shortest distance (e.g., first shortest distance D1) between the gate structure (e.g., gate structure 120) and the drain contact (e.g., drain contact 142), distance B is defined as the shortest distance (e.g., second shortest distance D2) between the gate structure (e.g., gate structure 120) and the ohmic contact layer (e.g., ohmic contact layer 132), and width C is defined as the width of the ohmic contact layer (e.g., ohmic contact layer 132). It should be noted that, for effective comparison, some parameters (e.g., distance A) will be kept consistent between the comparative examples and the experimental examples.

[0033] Based on the current-voltage curves in Table 1 and Figure 2, it can be confirmed that, compared to the comparative example (without an ohmic contact layer), the experimental example showed a reduction in on-resistance of approximately 10% and an increase in off-state breakdown voltage of approximately 3% while maintaining the critical voltage. Furthermore, electrical simulation results show that by providing an ohmic contact layer 132 between the gate structure 120 and the drain structure 122, the current in the second well region 114 can be concentrated near the surface, thereby reducing the on-resistance (Ron). Moreover, since the surface electric field can be more uniformly distributed, a better charge balance is achieved, thereby increasing the off-state breakdown voltage (VBD). Therefore, according to the embodiments disclosed herein, by providing an ohmic contact layer 132, the on-resistance of the semiconductor device can be reduced, and the off-state breakdown voltage of the semiconductor device 100 can also be increased, thereby improving the reliability of the semiconductor device 100.

[0034] Figures 3 through 10 are flowcharts illustrating a method for forming a semiconductor device 100 according to some embodiments of the present disclosure.

[0035] Referring to Figure 3, a substrate 110 is first provided. The substrate 110 has adjacent, juxtaposed first well regions 112 and second well regions 114 with opposite doping patterns. The formation method of the first well region 112 includes, but is not limited to, forming a patterned mask layer (not shown) on the substrate 110 using lithography and etching processes. This patterned mask layer exposes the area of ​​the substrate 110 where the first well region 112 is to be formed and covers other areas of the substrate 110. Then, dopants are implanted into the area where the first well region 112 is to be formed, and the patterned mask layer is then removed. The aforementioned patterned mask layer can be a hard mask or a photoresist. Next, the second well region 114 can be formed using a similar method.

[0036] Next, referring to Figure 4, a gate structure 120 (including a gate dielectric layer 120a and a gate electrode 120b) is formed across the first well region 112 and the second well region 114. In some embodiments, a dielectric material (not shown) can be formed using spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), other suitable methods, or combinations thereof. Then, a conductive material (not shown) can be formed through a deposition process, such as CVD, ALD, or physical vapor deposition (PVD) (e.g., sputtering or evaporation). Subsequently, the dielectric and conductive materials are patterned to form the gate dielectric layer 120a and the gate electrode 120b. The aforementioned illustrative method for patterning dielectric and conductive materials may include forming a photoresist layer on a conductive material using a suitable process (e.g., spin coating), and then patterning the photoresist layer using a suitable lithography process to form a patterned photoresist mask. The pattern of the photoresist mask may then be transferred to the underlying dielectric and conductive materials using a dry etching process to form a gate dielectric layer 120a and a gate electrode 120b. The photoresist may subsequently be stripped. In some embodiments, sidewall spacers 121 may be formed on the sidewalls of the gate dielectric layer 120a and the gate electrode 120b using a deposition and etching (anisotropic etching) process.

[0037] Next, referring to Figure 5, source structure 124 and drain structure 122 are formed in the first well region 112 and the second well region 114, respectively. The formation method of the doped regions of drain structure 122 and source structure 124 can be referred to the first well region 112 described in Figure 3, and will not be repeated here for the sake of simplicity.

[0038] Next, referring to Figure 6, a barrier protective oxide layer 130 is formed extending between the gate structure 120 and the drain structure 122. Then, a portion of the barrier protective oxide layer 130 is etched to form an opening 131 in the region where the ohmic contact layer 132 is to be formed, exposing a portion of the surface of the second well region 114. It should be noted that the location of the opening 131 will determine the subsequent location of the ohmic contact layer 132; therefore, the opening 131 should be located between the gate structure 120 and the drain structure 122. In some embodiments, the etching process for removing the barrier protective oxide layer 130 may include dry etching, wet etching (e.g., oxide wet etching), or a combination thereof.

[0039] Next, referring to Figure 7, an ohmic contact layer 132 is formed in the opening 131. In some embodiments, a self-aligned silicide process is first performed on the surface of the second well region 114 exposed by the opening 131 to form a silica layer 132a. The self-aligned silicide process can form silica elements by silicide formation, for example, forming a metallic material on a silicon structure (e.g., the second well region 114), and then annealing at a higher temperature to allow the underlying silicon and metallic material to undergo a silicide reaction, thereby forming a metal silicate. For example, a metallic material (e.g., nickel (Ni)) that will form an ohmic contact with the second well region 114 (e.g., silicon carbide (SiC)) can be used. Then, a rapid thermal processing (RTP) silicide process is used to allow Ni and SiC to undergo a silicide reaction to form a metal silicate (e.g., nickel silicate (NiSi)).

[0040] After the metal silicate is formed, unreacted metal material can be etched away. In some embodiments, the self-aligned silicate process forms self-aligned metal silicate 134 on the surfaces of the gate structure 120, source structure 124, and drain structure 122 simultaneously with the formation of silicate layer 132a. In other embodiments, the self-aligned metal silicate 134 and silicate layer 132a are formed in different process steps. As previously described, during the self-aligned silicate process, the barrier protective oxide layer 130 can protect the areas beneath it (e.g., the second well region 114 and drain structure 122) from silicate formation.

[0041] Referring to Figure 8, a metal layer 132b is formed and stacked on the silicate layer 132a. In this way, the ohmic contact layer 132 is formed on the second well region 114 and forms an ohmic contact with the second well region 114. The formation method of the metal layer 132b can be referred to the gate electrode 120b in Figure 4, and for the sake of simplicity, it will not be described again here.

[0042] Referring to Figure 9, an interlayer dielectric layer 140 is formed on the substrate 110 using a blanket coating. As shown, the interlayer dielectric layer 140 is formed to cover the gate structure 120, the source structure 124, the drain structure 122, and the ohmic contact layer 132. The interlayer dielectric layer 140 can be formed by CVD (e.g., HDPCVD, atmospheric pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD)), PVD, ALD, spin-on coating, other suitable processes, or combinations thereof.

[0043] Referring to Figure 10, a drain contact 142 is formed to pass through the interlayer dielectric layer 140 and be electrically connected to the drain structure 122, and a source contact 144 (including a first source contact 144a and a second source contact 144b) is formed to pass through the interlayer dielectric layer 140 and be electrically connected to the source structure 124, so as to form a semiconductor device 100 as shown in Figure 1. Patterning processes can be performed on the interlayer dielectric layer 140 to form openings in the interlayer dielectric layer 140. Conductive material is then deposited to fill the openings using PVD, electroplating, ALD, other suitable processes, or combinations thereof. A planarization process (e.g., chemical mechanical polishing (CMP)) or etching back process is then performed to remove the conductive material outside the openings, forming drain contacts 142 and source contacts 144. The first source contact 144a and the second source contact 144b are each electrically connected to the first doped region 124a and the second doped region 124b, respectively. It should be understood that after forming the drain contacts 142 and the source contacts 144, subsequent processes can be performed as needed to complete the fabrication of the semiconductor device 100. Since this is not the focus of this disclosure, it will not be elaborated here.

[0044] In summary, this disclosure provides a semiconductor device and a method for forming the same. This semiconductor device includes an ohmic contact layer located between a gate structure and a drain structure. The ohmic contact layer is situated on and forms an ohmic contact with a second well region (e.g., a drift region), causing the current in the second well region to concentrate near the surface, thereby reducing the on-resistance (Ron). Furthermore, because the surface electric field can be more uniformly distributed, a better charge balance can be achieved, maintaining or increasing the off-state breakdown voltage, thus improving the reliability of the semiconductor device.

[0045] The components of several embodiments are summarized above to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0046] 100: Semiconductor devices 110: Base 112: First Well Area 114: Second Well Area 120: Gate structure 120a: Gate dielectric layer 120b: Gate electrode 121: Sidewall spacers 122: Drain structure 124: Source Structure 124a: First doped region 124b: Second doped region 130: Barrier protective oxide layer 131: Opening 132: Ohmic contact layer 132a: Silicon layer 132b: Metal layer 134: Self-aligned metal silicides 140: Interlayer dielectric layer 142: Drain contact 144: Source contact 144a: First source contact 144b: Second source contact 202, 204: Curves D1, D2: Shortest distance W: Width

Claims

1. A semiconductor device, comprising: One base; A first well region and a second well region are placed adjacently in the substrate and have opposite doping modes; A gate structure is disposed across the first well region and the second well region; a source structure is disposed in the first well region; a drain structure is disposed in the second well region; and an ohmic contact layer is disposed on the substrate and forms an ohmic contact with the second well region, wherein the ohmic contact layer is disposed between the gate structure and the drain structure, and wherein the ohmic contact layer includes a silicate layer that is in direct contact with the second well region.

2. The semiconductor device as claimed in claim 1, wherein the ohmic contact layer further includes a metal layer stacked on the silicate layer.

3. The semiconductor device as claimed in claim 1, wherein the ohmic contact layer includes a floating metal layer.

4. The semiconductor device as claimed in claim 1, wherein the ohmic contact layer has a thickness of about 1 nanometer to 20 nanometers.

5. The semiconductor device as described in claim 1, further comprising: An interlayer dielectric layer is disposed on the substrate and covers the gate structure, source structure, drain structure, and ohmic contact layer; a drain contact passes through the interlayer dielectric layer and is electrically connected to the drain structure; and a source contact passes through the interlayer dielectric layer and is electrically connected to the source structure.

6. The semiconductor device as claimed in claim 5, wherein in a cross-sectional view, the gate structure is separated from the drain contact by a first minimum distance, and the gate structure is separated from the ohmic contact layer by a second minimum distance, the ratio of the second minimum distance to the first minimum distance being greater than about 0.

3.

7. The semiconductor device as claimed in claim 6, wherein the first shortest distance is less than about 3 micrometers.

8. The semiconductor device as claimed in claim 6, wherein the first shortest distance is greater than the width of the ohmic contact layer.

9. The semiconductor device as claimed in claim 1, wherein the source structure includes a first doped region and a second doped region that are adjacent to each other and have opposite doping patterns.

10. The semiconductor device of claim 1, wherein the drain structure and the second well region have the same doping type of dopant, and the doping concentration of the drain structure is greater than the doping concentration of the second well region.

11. The semiconductor device as claimed in claim 1 further includes a self-aligned metal silicide disposed on the surfaces of the gate structure, the source structure, and the drain structure, respectively.

12. The semiconductor device as claimed in claim 1 further includes a barrier protective oxide layer extending between the gate structure and the drain structure, and the ohmic contact layer is disposed on the second well region through the barrier protective oxide layer.

13. A method for forming a semiconductor device, comprising: A substrate is provided in which a first well region and a second well region are arranged adjacent to each other and have opposite doping modes; A gate structure is formed across the first well region and the second well region; a source structure is formed in the first well region; a drain structure is formed in the second well region; and an ohmic contact layer is formed on the substrate to form an ohmic contact with the second well region, wherein the ohmic contact layer is disposed between the gate structure and the drain structure, and wherein forming the ohmic contact layer includes performing a self-aligned siliconization process on the surface of the second well region to form a silicon layer.

14. The method of forming a semiconductor device as claimed in claim 13, wherein forming the ohmic contact layer further comprises forming a metal layer stacked on the silicate layer.

15. A method of forming a semiconductor device as claimed in claim 13, wherein performing the self-aligned siliconization process further includes forming a self-aligned metal siliconization on the surfaces of the gate structure, the source structure, and the drain structure, respectively.

16. A method of forming a semiconductor device as claimed in claim 13, wherein forming the ohmic contact layer comprises: A barrier protective oxide layer is formed extending between the gate structure and the drain structure; the barrier protective oxide layer is etched to form an opening that exposes part of the surface of the second well area; And to form the ohmic contact layer in the opening.

17. A method of forming a semiconductor device as claimed in claim 13, wherein the ohmic contact layer includes a floating metal layer.

18. The method of forming a semiconductor device as described in claim 13 further includes: An inter-dielectric layer is formed on the substrate and covers the gate structure, source structure, drain structure, and ohmic contact layer; A drain contact is formed through the interlayer dielectric layer and electrically connected to the drain structure; and a source contact is formed through the interlayer dielectric layer and electrically connected to the source structure.

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