Vertical gallium nitride transistors

Abstract

Vertical gallium nitride (GaN) field effect transistors (FETs) are presented herein. A vertical GaN FET includes cylindrical trench gates arranged in a hexagonal array to form vertical FET channels. At the surface of the vertical GaN FET is a source layer formed in a GaN epitaxial layer and over a GaN substrate. A channel may be formed between the cylindrical gates in the form of a “GaN pillar”; and FET characteristics, including threshold voltage, may be determined, at least in part by a trench nearest neighbor distance. Accordingly, the trench nearest neighbor distance may be selected so that the vertical GaN FET operates as either an enhancement mode or a depletion mode transistor.

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