Trench power semiconductor device and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2025-02-18
- Publication Date
- 2026-08-01
AI Technical Summary
Conventional trench power semiconductor manufacturing processes face challenges in further miniaturization of source width and require complex masking steps to remove the anti-reflective layer, while also needing improvements for power saving.
A trench power semiconductor device design with a substrate and buried gate structure, featuring a groove on the source region that lowers its surface below the substrate contact region, eliminating the need for complex masking steps and enabling miniaturization.
The design achieves a relatively low on-resistance, reducing power consumption and facilitating miniaturization of the device.
Smart Images
Figure TWG2TA001070001_001 
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Abstract
Description
[Technical Field]
[0001] This invention relates to a semiconductor element and a method for manufacturing the same, and more particularly to a trench power semiconductor element and a method for manufacturing the same. [Previous Technology]
[0002] Power semiconductors are used to handle high-power voltages and currents and are frequently used in power converters, sensors, radio frequency components, automotive electronic components, and more. Compared to planar power semiconductors, trench power semiconductor devices are more advantageous for portable or micro-device applications. Currently, trench power semiconductor technology continues to strive for miniaturization of device size; however, conventional trench power semiconductor manufacturing processes have reached a point where further miniaturization of the source width is difficult. Furthermore, in order to remove the anti-reflective layer after source formation, complex masking steps are required to protect the formed source. In addition, considering the need for power saving, conventional trench power semiconductor devices still require improvement. Therefore, improving trench power semiconductor devices and their manufacturing methods is one of the important issues that must be addressed. [Summary of the Invention]
[0003] This disclosure provides a trench power semiconductor device and a method for manufacturing the same, which is beneficial for miniaturizing the source width and eliminates the need for the aforementioned complex masking steps.
[0004] The trench-type power semiconductor device disclosed herein includes a substrate and a buried gate structure. The substrate includes a substrate region, a substrate contact region formed on the substrate region, and a source region formed on the substrate region and located adjacent to the substrate contact region. The source region and the substrate contact region have different conductivity types. The buried gate structure is formed in the substrate region and is located on one side of the substrate contact region and the source region. The substrate has a groove formed on the source region, such that the surface of the source region located at the bottom of the groove is lower than the top surface of the substrate contact region.
[0005] The method for manufacturing a trench-type power semiconductor device disclosed herein includes the following steps: forming a substrate region in a substrate; forming a substrate contact region in the substrate region; forming a source region on the substrate region and located next to the substrate contact region, wherein the source region and the substrate contact region have different conductivity types; forming a trench on the source region such that the surface of the source region located at the bottom of the trench is lower than the top surface of the substrate contact region; forming a buried gate structure in the substrate region, wherein the buried gate structure is located on one side of the substrate contact region and the source region.
[0006] Based on the above, in the trench power semiconductor device disclosed herein, by forming a groove on the source region, the top surface of the source region is lower than the top surface of the substrate contact region. This design enables the trench power semiconductor device provided herein to have a relatively low on-resistance, thereby reducing the power consumption of the trench power semiconductor device.
Implementation Method
[0007] In the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type; however, this disclosure is not limited thereto. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. The P-type dopant is, for example, boron, and the N-type dopant is, for example, phosphorus or arsenic. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, the schematic diagrams herein are merely illustrative of embodiments of parts of the invention.
[0008] The following describes an embodiment of the trench power semiconductor device 10a and its manufacturing method with reference to Figures 1 to 3.
[0009] Referring to FIG1, a substrate region 104 is formed in the substrate 100. The substrate 100 may be a suitable semiconductor material. For example, the material of the substrate 100 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), silicon germanium (SiGe), other suitable materials or combinations of the above materials, and this disclosure is not limited thereto.
[0010] In some embodiments, an epitaxial layer 102 may be formed in the substrate 100 before the substrate region 104 is formed. In other words, the substrate region 104 is located on the epitaxial layer 102. The epitaxial layer 102 may be formed by a metal-organic chemical vapor deposition (MOCVD) process, but this disclosure is not limited thereto. In other embodiments, the epitaxial layer 102 may be formed by a hydride vapor phase epitaxy (HVPE) process or a molecular beam epitaxy (MBE) process. In some embodiments, the epitaxial layer 102 has a first conductivity type; for example, the epitaxial layer 102 may be an N-type epitaxial layer, but this disclosure is not limited thereto. In other embodiments, the epitaxial layer 102 may have a second conductivity type.
[0011] In some embodiments, the substrate region 104 may be formed in the epitaxial layer 102 by an ion implantation process, but this disclosure is not limited thereto. In other embodiments, the substrate region 104 may be formed on the epitaxial layer 102 by a suitable epitaxial growth process. In some embodiments, the substrate region 104 may have a different conductivity type than the epitaxial layer 102.
[0012] Next, a substrate contact region 106 may be formed in the substrate region 104, for example, by an ion implantation process. In some embodiments, the substrate contact region 106 has the same conductivity as the substrate region 104, and the substrate contact region 106 has a higher dopant concentration.
[0013] Next, a source region 108 is formed on the substrate region 104 and located next to the substrate contact region 106, wherein the top surface 108T of the source region 108 disclosed herein is lower than the top surface 106T of the substrate contact region 106. Forming the source region 108 may include the following steps.
[0014] First, an implantation blocking layer PL, a hard mask layer LI, and a patterned photoresist layer PR are sequentially formed on the substrate region 104. In some embodiments, the implantation blocking layer PL may be formed on the epitaxial layer 102 by a coating process. The material of the implantation blocking layer PL may include, for example, a suitable organic material. In some embodiments, the thickness PLT of the implantation blocking layer PL may be greater than the thickness of the patterned photoresist layer PR, thereby providing a good implantation blocking effect and improving the accuracy of patterning.
[0015] In some embodiments, the hard mask layer LI may be formed on the implantation barrier layer PL by a chemical vapor deposition process, a thermal oxidation process, or a combination thereof, and this disclosure is not limited thereto. The material of the hard mask layer LI may include oxides, such as silicon oxide. The thickness of the hard mask layer LI may be less than the thickness of the implantation barrier layer PL and the thickness of the patterned photoresist layer PR.
[0016] In some embodiments, the patterned photoresist layer PR can be formed on the rigid mask layer LI through a coating process, but this disclosure is not limited thereto. The material of the patterned photoresist layer PR may be different from that of the implanted barrier layer PL.
[0017] Subsequently, a patterned photoresist layer PR can be used as a mask to perform a patterning process on the hard mask layer LI and the implanted barrier layer PL, forming a plurality of vias TV in the implanted barrier layer PL to expose the locations on the surface of the substrate region 104 where the source region 108 is to be formed. Specifically, in this embodiment, the plurality of vias TV expose the locations on the surface of the substrate contact region 106 where the source region 108 is to be replaced. However, in some embodiments not shown, since the substrate contact region 106 is formed after the source region 108 is formed, the plurality of vias TV expose the locations on the surface of the substrate region 104 where the source region 108 is to be formed. In some embodiments, the aspect ratio of the vias TV can be greater than or equal to 7, thereby facilitating process miniaturization.
[0018] Then, corresponding to the via TV of the implanted barrier layer PL, an ion implantation process is performed on the exposed surface of the substrate contact region 106 to form the source region 108. In this embodiment, the width 108W of the source region 108 may not exceed 200 nanometers. In this embodiment, the source region 108 has a different conductivity type than the substrate contact region 106. In other embodiments, the dopant concentration of the source region 108 may be greater than the dopant concentration of the substrate contact region 106. In some embodiments not shown, since the substrate contact region 106 is formed after the source region 108 is formed, the ion implantation process is performed on the exposed surface of the substrate region 104 according to the via TV of the implanted barrier layer PL to form the source region 108.
[0019] According to this embodiment, by using an implantation barrier layer PL with a thickness greater than that of the patterned photoresist layer PR, the influence of ion implantation on adjacent areas (e.g., substrate contact area 106) can be effectively blocked during the formation of the source region 108, which is beneficial for more precise control of the width 108W of the source region 108. In addition, by using vias TV with an aspect ratio greater than or equal to 7, the width 108W of the source region 108 can be miniaturized.
[0020] Subsequently, an etching process is performed to remove the hard mask layer LI and form a groove Re (marked in FIG2A) on the source region 108.
[0021] In some embodiments, the hard mask layer LI can be removed by a dry etching process. For example, the hard mask layer LI can be removed using fluoride ion plasma. It is worth noting that during the removal of the hard mask layer LI, a portion of the source region 108 exposed by the via TV is also removed. As a result, the top surface 108T of the source region 108 disclosed herein is lower than the top surface 106T of the substrate contact region 106.
[0022] In a preferred embodiment, by using an implanted barrier layer PL with a via TV having an aspect ratio greater than or equal to 7 and by using fluoride ion plasma to perform the above-mentioned etching process, the depth of the groove Re formed on the source region 108 can be precisely controlled, which is beneficial to improving the yield.
[0023] Then, the implantation barrier layer PL is removed. In some embodiments, the implantation barrier layer PL can be removed by a stripping process. After the implantation barrier layer PL is removed, a cleaning process can be performed to remove any impurities that may remain.
[0024] In this embodiment, as shown in FIG2A, before forming the source region 108, for example after forming the substrate contact region 106 and before forming the implantation barrier layer PL, a buried gate structure 200 may be formed in the substrate region 104, such that the buried gate structure 200 is located on one side of the substrate contact region 106 and the subsequently formed source region 108. The buried gate structure 200 includes a gate insulating layer 202, a buried gate electrode 204, and an insulating capping layer 206. In this embodiment, forming the buried gate structure 200 may include the following steps.
[0025] First, a plurality of gate trenches GT are formed in the substrate region 104. In some embodiments, the aspect ratio of the gate trenches GT may be at least 2.5, but this disclosure is not limited thereto. In some embodiments, the gate trenches GT may penetrate the substrate region 104 and extend into the epitaxial region 102. In some embodiments, the bottom surface of the gate trenches GT may be located between the bottom surface of the substrate region 104 and the bottom surface of the epitaxial region 102.
[0026] Subsequently, a gate insulating layer 202 is formed on the surface of the gate trench GT. In some embodiments, the gate insulating layer 202 may be conformally formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or thermal oxidation processes. The material of the gate insulating layer 202 may include, for example, a suitable dielectric material. For example, the material of the gate insulating layer 202 may include silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), zinc oxide (ZnO2), hafnium oxide (HfO2), or combinations thereof.
[0027] Then, a buried gate electrode 204 is formed on the gate insulating layer 202. In some embodiments, the buried gate electrode 204 may be formed by first forming a gate electrode material layer (not shown) through a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a combination thereof, and then by performing an etch-back process on the gate electrode material layer, but this disclosure is not limited thereto. The material of the buried gate electrode 204 may include, for example, polycrystalline silicon, but this disclosure is not limited thereto. In other embodiments, the material of the buried gate electrode 204 may include metal or metal alloy. For example, the material of the buried gate electrode 204 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), or a combination thereof, but this disclosure is not limited thereto.
[0028] In detail, referring to FIG3, in some embodiments, in order to further improve the yield and electrical performance of the trench power semiconductor device 10a, the buried gate electrode 204 may include a non-porous conformal gate layer 204a and a gate filling layer 204b having pores V, and the pores V are at least 10 nanometers away from the gate insulating layer 202. Specifically, the buried gate electrode 204 of this embodiment can be formed by the following steps: A non-porous conformal gate layer 204a is formed on the gate insulating layer 202, and then a first annealing process is performed sequentially to remove the oxide of the conformal gate layer 204a, forming a gate filling layer 204b having pores V, and a second annealing process is performed to etch back the conformal gate layer 204a and the gate filling layer 204b, so that the top surface 204T of the buried gate electrode 204 is lower than the top surface 106T of the substrate contact region 106. This effectively prevents problems such as leakage current, abnormal gate control force (Vt shift), or abnormal reliability due to shortened lifespan of the gate insulation layer 202 caused by the V-hole contacting the gate insulation layer 202.
[0029] Subsequently, an insulating capping layer 206 is formed on the buried gate electrode 204. The insulating capping layer 206 is formed, for example, in a plurality of gate trenches GT to cover the buried gate electrode 204. Based on this, the insulating capping layer 206 and the gate insulating layer 202 can together cover the buried gate electrode 204. The method of forming the insulating capping layer 206 and its material can be the same as or similar to the method of forming the gate insulating layer 202 and its material, and will not be described again here. In this embodiment, as shown in FIG2A, the surface 108T of the source region 108 exposed at the bottom of the groove Re is not lower than the top surface 206T of the insulating capping layer 206.
[0030] Additionally, in this embodiment, the method of manufacturing the trench power semiconductor device 10a may further include forming an isolation structure 400 in the epitaxial layer 102 to isolate the buried gate structure 200 from peripheral circuitry (not shown), but this disclosure is not limited thereto. In some embodiments, the isolation structure 400 may include a shallow trench isolation structure. The material of the isolation structure 400 may be, for example, silicon oxide, silicon nitride, or a combination thereof.
[0031] As shown in FIG2B, in this embodiment, the method for manufacturing the trench power semiconductor device 10a further includes forming a source electrode 500 on the source region 108 and the substrate contact region 106, wherein the source electrode 500 is electrically connected to the source region 108 and the substrate contact region 106. The source electrode 500 may include a plurality of extensions 500L filled in the groove Re, such that the bottom surface 500B of each extension 500L is lower than the top surface 106T of the substrate contact region 106.
[0032] In some embodiments, the source electrode 500 may be formed by a CVD process, a PVD process, or an ALD process. The material of the source electrode 500 may include, for example, a suitable metal or metal alloy. For example, the material of the source electrode 500 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), or combinations thereof.
[0033] In addition, in this embodiment, the method of manufacturing trench power semiconductor device 10a may further include forming a drain electrode (not shown) on the surface of substrate 100 away from epitaxial layer 102.
[0034] In this embodiment, by forming a via TV in the implanted barrier layer PL, a portion of the source region 108 can be removed during the process of removing the hard mask layer LI, such that the top surface 108T of the source region 108 is lower than the top surface 106T of the substrate contact region 106. Furthermore, the source electrode 500 may include a plurality of extensions 500L filled into the groove Re. This facilitates the miniaturization of the source width and eliminates the need for the complex masking steps described in the prior art. Furthermore, the trench power semiconductor device 10a of this embodiment can have a relatively low on-resistance, thereby reducing the power consumption of the trench power semiconductor device 10a.
[0035] The trench power semiconductor device 10a of this embodiment will be briefly described below with reference to Figures 2A to 2D and Figure 3. The remaining details of the trench power semiconductor device 10a of this embodiment can be understood with reference to the above description, and will not be repeated here.
[0036] Referring to Figures 2A to 2D, the trench power semiconductor device 10a of this embodiment includes a substrate 100 and an embedded gate structure 200.
[0037] The substrate 100 has, for example, a first conductivity type, such as an N-type substrate, but this disclosure is not limited thereto. In this embodiment, the substrate 100 includes a substrate region 104, a substrate contact region 106, and a source region 108.
[0038] The substrate region 104 may be disposed in the substrate 100. In some embodiments, the substrate region 104 may have a second conductivity type. For example, the substrate region 104 may include a p-type dopant, but this disclosure is not limited thereto.
[0039] The substrate contact region 106 may be disposed on the substrate region 104 and, for example, have a second conductivity type. For example, the substrate contact region 106 may include a P-type dopant, but this disclosure is not limited thereto.
[0040] The source region 108 may be disposed on the substrate region 104 and located adjacent to the substrate contact region 106. In this embodiment, the source region 108 may have a first conductivity type. For example, the source region 108 may include an N-type dopant, but this disclosure is not limited thereto. In other embodiments, the dopant concentration of the source region 108 may be greater than the dopant concentration of the substrate contact region 106. In this embodiment, the width 108W (indicated in FIG. 1) of the source region 108 may not be greater than 200 nanometers. In a preferred embodiment, the width 108W of the source region 108 may be less than or equal to 150 nanometers.
[0041] In detail, in this embodiment, the substrate 100 has a groove Re formed on the source region 108, such that the surface 108T of the source region 108 at the bottom of the groove Re is lower than the top surface 106T of the substrate contact region 106, thereby the trench power semiconductor device 10a can have a relatively low on-resistance, and the power consumption of the trench power semiconductor device 10a can be reduced.
[0042] In addition to the groove Re shape shown in FIG2A, in other embodiments, the groove Re may have a variation shape as shown in FIG4A to FIG4F, but this disclosure is not limited thereto. In this way, the strong electric field generated by the sharp corner structure between the source region 108 and the substrate contact region 106 can be avoided from affecting each other and causing unpredictable effects on the device characteristics.
[0043] Referring to Figure 4A, a groove Re1 may be formed within the source region 108, such that a portion of the surface 108T of the source region 108 may be flush with the top surface 106T of the substrate contact region 106. The source electrode 500 may have an extension corresponding to the shape of the groove Re1.
[0044] Referring to Figure 4B, the groove Re2 may span the source region 108 and a portion of the substrate contact region 106, such that the substrate contact region 106 may have a cross-sectional shape that is narrower at the top and wider at the bottom. The source electrode 500 may have an extension corresponding to the shape of the groove Re2.
[0045] Referring to Figure 4C, the groove Re3 may span a portion of the source region 108 and a portion of the substrate contact region 106, such that both the source region 108 and the substrate contact region 106 have a cross-sectional shape that is narrower at the top and wider at the bottom, and both are asymmetrical. The source electrode 500 may have an extension corresponding to the shape of the groove Re3.
[0046] Referring to Figure 4D, the sidewalls of the groove Re4 have a tapered profile. Specifically, the size of the groove Re4 decreases from the top to the bottom (in the direction opposite to direction Z) and has an inclined profile. The upper sidewall Re41 and the lower sidewall Re42 of the groove Re4 each have different conductivity types, and the lower sidewall Re42 of the groove Re4 has the same conductivity type as the bottom Re43 of the groove Re4. The source electrode 500 may have an extension corresponding to the shape of the groove Re4.
[0047] Referring to Figure 4E, preferably, the sidewalls of the groove Re5 also have a tapered profile. Specifically, the size of the groove Re5 decreases from the top side to the bottom side (in the direction opposite to direction Z) and has a smooth profile. Therefore, in this embodiment, the top surface 106T of the substrate contact area 106 includes a convex surface, and the top surface 108T of the source region 108 includes a concave surface. The upper sidewall Re51 and the lower sidewall Re52 of the groove Re5 each have different conductivity types, and the lower sidewall Re52 of the groove Re5 has the same conductivity type as the bottom Re53 of the groove Re5. The source electrode 500 may have an extension corresponding to the shape of the groove Re5.
[0048] Referring to Figure 4F, the sidewalls of the groove Re6 have a stepped profile. This stepped profile exposes the substrate contact area 106. Therefore, in this embodiment, the substrate contact area 106 may have a cross-sectional shape that is narrower at the top and wider at the bottom. The source electrode 500 may have an extension corresponding to the shape of the groove Re6.
[0049] In some embodiments, the substrate 100 further includes an epitaxial layer 102. The substrate region 104 may be located between the epitaxial region 102 and the source region 108 or the substrate contact region 106.
[0050] The embedded gate structure 200 is formed in the substrate region 104 and is located on one side of the substrate contact region 106 and the source region 108. In other words, the substrate contact region 106 and the source region 108 are alternately arranged on one side of the embedded gate structure 200. In this embodiment, the embedded gate structure 200 is formed in the gate trench GT located in the substrate region 104 and the epitaxial region 102, and includes a gate insulating layer 202, an embedded gate electrode 204, and an insulating capping layer 206. In this embodiment, the surface 108T of the source region 108 located at the bottom of the trench Re is not lower than the top surface 206T of the insulating capping layer 206.
[0051] In addition, the trench power semiconductor element 10a of this embodiment may also include the isolation structure 400 shown in FIG1 and the source electrode 500 shown in FIG2B or any of FIG4A to 4F, but this disclosure is not limited thereto.
[0052] The trench power semiconductor device 10b of another embodiment of the present disclosure will be described below with reference to Figures 5A to 5D. It should be noted that the embodiments of Figures 5A to 5D may each use the component reference numerals and some contents of the embodiments of Figures 2A to 2D, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted.
[0053] Referring to Figures 5A and 5B, in the trench power semiconductor device 10b of this embodiment, the insulating capping layer 206 has a recess 206R located between a plurality of source regions 108 on both sides of the buried gate structure 200. The top surface 206RT of the recess 206R is lower than the top surface 206T of the insulating capping layer 206 located between a plurality of substrate contact regions 106 on both sides of the buried gate structure 200.
[0054] Referring to FIG5A, in this embodiment, the insulating cover layer 206 has a plurality of recesses 206R arranged along the extension direction (direction Y) of the embedded gate structure 200, and the plurality of recesses 206R and the plurality of grooves Re have the same period and phase.
[0055] Refer to Figure 5A. In this embodiment, the depth D1 of the recess 206R is less than the depth D2 of the groove Re.
[0056] Refer to Figures 5A and 5D. In this embodiment, the surface 206T of the insulating capping layer 206 located between the multiple source regions 108 on both sides of the embedded gate structure 200 is lower than the surface 108T of the source region 108 located at the bottom of the groove Re.
[0057] In detail, in the manufacturing method of the trench power semiconductor device 10b of this embodiment, referring to FIG1, the vias TV of the embedded barrier layer PL also expose a portion of the insulating capping layer 206. In other words, each via TV extends along a direction (direction X) perpendicular to the extension direction (direction Y) of the buried gate structure 200. As a result, the etching process forming the groove Re also removes the portion of the insulating capping layer 206 exposed by the via TV. Since the insulating capping layer 206 has a larger etch rate relative to the source region 108, the amount of removal of the insulating capping layer 206 is greater than the amount of removal of the source region 108. Based on this, in this embodiment, the top surface 108T of the source region 108 may be higher than the top surface 206T of the insulating capping layer 206. Furthermore, as shown in FIG5A and FIG5B, the top surface 206T of the insulating capping layer 206 located between the substrate contact regions 106 may be higher than the top surface 206RT of the insulating capping layer 206 located between the source regions 108. In other words, the top surface of the insulating cover layer 206 of each embedded gate structure 200 is a concave-convex surface.
[0058] In addition, as shown in FIG5B, the source electrode 500 can be electrically isolated from the gate electrode 202 through the insulating capping layer 206.
[0059] Refer to Figures 5B to 5D. In this embodiment, the source electrode 500 may include a base 500M, a first extension 500L1, a second extension 500L2, and a third extension 500L3.
[0060] The base 500M is disposed above the source region 108 and the substrate contact region 106, and covers the source region 108 and the substrate contact region 106, for example. As shown in FIG5C, in some embodiments, the base 500M is in contact with the substrate contact region 106, but this disclosure is not limited thereto.
[0061] The first extension 500L1 is, for example, filled into the groove Re such that the bottom surface 500L1B of the first extension 500L1 is lower than the top surface 106T of the substrate contact area 106. From another perspective, the first extension 500L1 is located between adjacent substrate contact areas 106 in the Y direction.
[0062] The second extension 500L2 is located, for example, on the embedded gate structure 200 and is adjacent to the first extension 500L1 in the X direction. Therefore, in this embodiment, the bottom surface 500L2B of the second extension 500L2 is lower than the bottom surface 500L1B of the first extension 500L1. From another perspective, the second extension 500L2 is located between adjacent source regions 108 in the X direction.
[0063] The third extension 500L3 is located, for example, on the embedded gate structure 200 and adjacent to the second extension 500L2 in the Y direction. From another perspective, the third extension 500L3 is located between adjacent substrate contact areas 106 in the X direction.
[0064] The trench power semiconductor device 10c of this disclosure will be described below with reference to Figures 6A to 6C. It should be noted that the embodiments of Figures 6A to 6C may each use the component reference numerals and some contents of the embodiments of Figures 2A to 2D, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted.
[0065] Referring to Figures 6A to 6C, in this embodiment, the trench power semiconductor element 10c has a substrate 100 having a plurality of grooves Re on a first side of the buried gate structure 200 and a substrate contact area 106 on a second side of the buried gate structure 200, wherein the plurality of grooves Re and the substrate contact area 106 are alternately arranged along a direction (direction X) perpendicular to the extension direction (direction Y) of the buried gate structure.
[0066] In summary, in the manufacturing method of the trench power semiconductor device disclosed herein, by forming vias in the implantation barrier layer, a portion of the source region exposed by the vias can be removed during the etching process that removes the hard mask layer disposed on the implantation barrier layer, thus forming a trench, and the surface of the source region at the bottom of the trench is lower than the top surface of the substrate contact area. Therefore, the trench power semiconductor device disclosed herein can have a relatively low on-resistance, thereby reducing the power consumption of the trench power semiconductor device. In other words, this disclosure provides a green semiconductor technology.
[0067] In addition, in the trench power semiconductor device disclosed herein, the width of the source region is no greater than 200 nanometers, or even less than or equal to 150 nanometers. Therefore, the miniaturization of the trench power semiconductor device can be achieved through this design. [Simplified Explanation of the Diagram]
[0068] FIG1 is a schematic flow diagram of a method for manufacturing a trench power semiconductor device according to an embodiment of the present disclosure. FIG2A is a partial perspective view of a trench power semiconductor device according to an embodiment of the present disclosure. FIG2B is a partial cross-sectional view drawn according to section line A-A' in FIG2A. FIG2C is a partial cross-sectional view drawn according to section line B-B' in FIG2A. FIG2D is a partial cross-sectional view drawn according to section line C-C' in FIG2A. FIG3 is a cross-sectional view of an intermediate manufacturing process of an embedded gate structure in a trench power semiconductor device according to an embodiment of the present disclosure. FIG4A to FIG4F are cross-sectional views of grooves formed on the source region according to various embodiments of the present disclosure. FIG5A is a partial perspective view of a trench power semiconductor device according to another embodiment of the present disclosure. FIG5B is a partial cross-sectional view drawn according to section line D-D' in FIG5A. FIG5C is a partial cross-sectional view drawn according to section line B-B' in FIG5A. Figure 5D is a partial cross-sectional view drawn according to section line C-C' in Figure 5A. Figure 6A is a partial perspective view of a trench power semiconductor device according to another embodiment of the present disclosure. Figure 6B is a partial cross-sectional view drawn according to section line A-A' in Figure 6A. Figure 6C is a partial cross-sectional view drawn according to section line E-E' in Figure 6A.
Claims
1. A trench-type power semiconductor device, comprising: A substrate includes a substrate region, a substrate contact region formed on the substrate region, and a source region formed on the substrate region and located adjacent to the substrate contact region, the source region and the substrate contact region having different conductivity types; and an embedded gate structure formed in the substrate region and located on one side of the substrate contact region and the source region, wherein the substrate has a groove formed on the source region such that the surface of the source region at the bottom of the groove is lower than the top surface of the substrate contact region.
2. The trench power semiconductor device as claimed in claim 1, wherein the source region comprises an N-type dopant and the substrate contact region comprises a P-type dopant.
3. The trench power semiconductor device as described in claim 1, further comprising: A source electrode covers the source region and the substrate contact region, and includes a plurality of extensions filled into the groove, such that the bottom surface of each extension is lower than the top surface of the substrate contact region, wherein the substrate further includes an epitaxial region, and the substrate region is located between the epitaxial region and the source region or the substrate contact region.
4. The trench power semiconductor device as claimed in claim 3, wherein the buried gate structure is formed in a gate trench located in the substrate region and the epitaxial region, and comprises: A gate insulation layer is formed on the surface of the gate trench; An embedded gate electrode is formed on the gate insulating layer; An insulating capping layer is disposed on the embedded gate electrode, and the surface of the source region located at the bottom of the groove is higher than or at the same level as the top surface of the insulating capping layer.
5. The trench power semiconductor device as claimed in claim 4, wherein the aspect ratio of the gate trench is greater than or equal to 2.5, the embedded gate electrode comprises a non-porous conformal gate layer and a porous gate filling layer, and the pores are at least 10 nanometers away from the gate insulating layer.
6. The trench power semiconductor device as claimed in claim 4, wherein the insulating cap layer has a recess located between a plurality of source regions on both sides of the buried gate structure, the top surface of the recess being lower than the top surface of the insulating cap layer located between a plurality of substrate contact regions on both sides of the buried gate structure.
7. The trench power semiconductor device as claimed in claim 6, wherein the insulating cap layer has a plurality of said recesses arranged along the extension direction of said buried gate structure, and the plurality of said recesses have the same period and phase as the plurality of said grooves.
8. The trench power semiconductor device as claimed in claim 6, wherein the depth of the recess is less than the depth of the groove.
9. The trench power semiconductor device as claimed in claim 1, further comprising a source electrode, wherein the source electrode comprises: The base layer covers the source region and the substrate contact region; A first extension is inserted into the groove such that the bottom surface of the first extension is lower than the top surface of the substrate contact area; And a second extension, located on the embedded gate structure and adjacent to the first extension, wherein the bottom surface of the second extension is lower than the bottom surface of the first extension.
10. The trench power semiconductor device as claimed in claim 1, wherein the trench is formed within the source region.
11. The trench power semiconductor device as claimed in claim 1, wherein the trench spans a portion of the source region and a portion of the substrate contact region.
12. The trench power semiconductor device of claim 1, wherein the upper sidewall and the lower sidewall of the trench each have different conductivity types, and the lower sidewall of the trench has the same conductivity type as the bottom of the trench.
13. The trench power semiconductor device as claimed in claim 1, wherein the sidewalls of the trench have a tapered profile.
14. The trench power semiconductor device of claim 1, wherein the top surface of the substrate contact region includes a convex surface, and the surface of the source region includes a concave surface.
15. The trench power semiconductor device as claimed in claim 1, wherein the sidewalls of the trench have a stepped profile.
16. The trench power semiconductor device of claim 1, wherein the substrate has a plurality of grooves on a first side of the buried gate structure and a substrate contact area on a second side of the buried gate structure, wherein the plurality of grooves and the substrate contact area are alternately arranged in a direction perpendicular to the extension direction of the buried gate structure.
17. The trench power semiconductor device as claimed in claim 1, wherein the width of the source region is less than or equal to 200 nanometers.
18. The trench power semiconductor device as claimed in claim 1, wherein the width of the source region is less than or equal to 150 nanometers.
19. A method for manufacturing a trench-type power semiconductor device, comprising: The matrix region is formed in the substrate; A substrate contact region is formed in the substrate region; A source region is formed on the substrate region and located next to the substrate contact region, wherein the source region and the substrate contact region have different conductivity types; a groove is formed on the source region such that the surface of the source region at the bottom of the groove is lower than the top surface of the substrate contact region; And forming an embedded gate structure in the substrate region, wherein the embedded gate structure is located on one side of the substrate contact region and the source region.
20. A method of manufacturing a trench power semiconductor device as claimed in claim 19, wherein the source region comprises an N-type dopant and the substrate contact region comprises a P-type dopant.
21. A method for manufacturing a trench power semiconductor device as claimed in claim 19, wherein the step of forming the source region comprises: An implantation barrier layer, a hard mask layer, and a patterned photoresist layer are sequentially formed on the substrate region, wherein the thickness of the implantation barrier layer is greater than the thickness of the patterned photoresist layer; through-holes are formed in the implantation barrier layer to expose the surface of the substrate region. An ion implantation process is performed on the surface of the substrate region that is exposed to form the source region; an etching process is performed to remove the hard mask layer and form the groove. And remove the implanted barrier layer.
22. A method for manufacturing a trench power semiconductor device as claimed in claim 20, wherein the step of forming the buried gate structure comprises: A gate trench is formed in the substrate region; A gate insulation layer is formed on the surface of the gate trench; An embedded gate electrode is formed on the gate insulating layer; An insulating capping layer is formed on the embedded gate electrode, wherein the surface of the source region located at the bottom of the groove is higher than or at the same level as the top surface of the insulating capping layer.
23. A method of manufacturing a trench power semiconductor device as claimed in claim 21, wherein a portion of the insulating capping layer is also removed during the etching process.
24. A method for manufacturing a trench power semiconductor device as claimed in claim 20, wherein the etching process is a dry etching process using fluoride ion plasma.
25. A method for manufacturing a trench power semiconductor device as claimed in claim 20, wherein the aspect ratio of the via is greater than or equal to 7.
26. A method for manufacturing a trench power semiconductor device as claimed in claim 19, wherein the step of forming the buried gate structure includes: A gate trench is formed in the substrate region; A gate insulation layer is formed on the surface of the gate trench; An embedded gate electrode is formed on the gate insulating layer; An insulating capping layer is formed on the embedded gate electrode, wherein the surface of the source region located at the bottom of the groove is higher than or at the same level as the top surface of the insulating capping layer.
27. A method of manufacturing a trench power semiconductor device as claimed in claim 26, wherein the aspect ratio of the gate trench is greater than or equal to 2.5, the embedded gate electrode comprises a non-porous conformal gate layer and a porous gate filling layer, and the pores are at least 10 nanometers away from the gate insulating layer.