Three-dimension semiconductor device

Abstract

The present disclosure is related to a three-dimension semiconductor device comprising a first circuit layer and a second circuit layer. The first circuit layer comprises a first circuit block. The second circuit layer is disposed on the first circuit layer and comprises a second circuit block. The first circuit block and the second circuit block establish an electrical connection relationship through connecting pillars. By increasing the wiring dimension of the wiring, the present disclosure allows the first circuit block and the second circuit block, which were originally only electrically connected in two dimensions, to establish electrical connections through the third dimension. Therefore, the length of a signal transmission path is reduced. The purpose of reducing wiring length and signal delay is achieved.

Description

Technical Field

[0001] This application relates to a semiconductor device, and more particularly to a three-dimensional semiconductor device. Prior Technology

[0002] As the computing demands of electronic products increase dramatically, the number of circuit blocks inside these products also increases accordingly, leading to a significant rise in the complexity and compactness of wiring, as well as increased trace length and signal delay.

[0003] At the same time, in order to improve the performance of chip devices without increasing their size or area, three-dimensional packaging processes that integrate bare dies of different processes and properties have been proposed, such as WoW (Wafer-on-Wafer), CoWoS (Chip-on-Wafer-on-Substrate), and SoIC (Small-Outline Integrated Circuit).

[0004] Therefore, how to apply 3D packaging processes to reduce wiring trace length and signal delay is one of the problems that needs to be solved in this field. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a three-dimensional semiconductor device that increases the routing dimension of wiring through the application of a three-dimensional packaging process, thereby reducing the routing length and signal delay.

[0006] To achieve the above objectives, this application proposes a three-dimensional semiconductor device comprising a first circuit layer and a second circuit layer. The first circuit layer includes a first switching block. The second circuit layer is disposed on the first circuit layer and includes a second switching block. The second switching block and the first switching block are electrically connected through connecting posts. The vertical projections of the second switching block, the first switching block, and the connecting posts at least partially overlap on the first circuit layer.

[0007] In one embodiment, the topology of the first switch block is the same as or different from that of the second switch block.

[0008] In one embodiment, the topology includes a split type, a general type, and a Wilton type.

[0009] In one embodiment, the first switch block and the second switch block include a plurality of connection terminals, and the connection terminals of the first switch block are electrically connected to the connection terminals of the second switch block through a plurality of connection posts.

[0010] In one embodiment, the first circuit layer includes a configuration memory and a first logic block, and the second circuit layer includes a second logic block. The second logic block is electrically connected to the configuration memory through a connection post, and the configuration memory and the second logic block are located in different circuit layers.

[0011] In one embodiment, the first circuit layer and the second circuit layer are implemented by a field-programmable logic gate array.

[0012] In one embodiment, the first circuit layer includes a first circuit block, and the second circuit layer includes a second circuit block. The first circuit block and the second circuit are functional circuit blocks that are the same or different.

[0013] In one embodiment, the first circuit block and the second circuit block include a logic block, a digital signal processor block, a memory block, and a hard silicon intellectual property.

[0014] In one embodiment, the manufacturing process of the first circuit layer and the manufacturing process of the second circuit layer may be the same or different.

[0015] To achieve the above objectives, this application proposes a three-dimensional semiconductor device comprising a first circuit layer and a second circuit layer. The first circuit layer includes configuration memory. The second circuit layer is disposed on the first circuit layer. The second circuit layer includes a circuit block electrically connected to the configuration memory. The configuration memory and the circuit block are located on different circuit layers.

[0016] In one embodiment, the configuration memory stores a lookup table corresponding to a circuit block.

[0017] In one embodiment, the circuit block is a logic block.

[0018] In one embodiment, the circuit block is not configured with the configuration memory.

[0019] Based on the above, the three-dimensional semiconductor device of this application enables signal transmission in the third dimension through connecting pillars between different circuit layers, thereby reducing wiring length and signal delay. Simple Explanation of the Diagram

[0020] Figure 1 is a schematic diagram of a three-dimensional semiconductor device embodiment according to an embodiment of this application; Figure 2 is a schematic diagram of another embodiment of a three-dimensional semiconductor device according to an embodiment of this application; Figure 3 is a schematic diagram of yet another embodiment of a three-dimensional semiconductor device according to an embodiment of this application; Figure 4 is a schematic diagram of the topological structure of the switch block according to an embodiment of this application; Figure 5 is a schematic diagram of the topological structure of the switch block according to an embodiment of this application, in a second embodiment. Figure 6 is a schematic diagram of the topological structure of the switch block according to an embodiment of this application, in the third embodiment. Figure 7 is a schematic diagram of a combined embodiment of the switch block according to an embodiment of this application. Implementation

[0021] Please refer to Figure 1, which is a schematic diagram of an embodiment of the three-dimensional semiconductor device of this application. The three-dimensional semiconductor device 1 includes a first circuit layer 110 and a second circuit layer 120. The three-dimensional semiconductor device 1 can be implemented using WoW, CoWoS, or SoIC packaging processes. In one embodiment, the first circuit layer 110 and the second circuit layer 120 are field-programmable gate arrays. The first circuit layer 110 and the second circuit layer 120 can be implemented using a die.

[0022] The first circuit layer 110 includes configuration memory 111. Configuration memory 111 is arranged on the first circuit layer 110 along a first axis X and a second axis Y. Configuration memory 111 is used to store look-up tables (LUTs) for corresponding Configurable Logic Blocks (CLBs). In this embodiment, configuration memory 111 is, for example, static random-access memory (SRAM).

[0023] A second circuit layer 120 is disposed on the first circuit layer 110. The second circuit layer 120 includes circuit blocks 121. Circuit blocks 121 are arranged on the second circuit layer 120 along a first axis X and a second axis Y. Circuit blocks 121 are, for example, logic blocks. Logic blocks are, for example, circuit blocks containing multiplexers, shift registers, and logic gates. Circuit blocks 121 are electrically connected to a corresponding configuration memory 111 along a third axis Z through at least one connecting post 130. The first axis X is perpendicular to the second axis Y, and the third axis Z is perpendicular to both the first axis X and the second axis Y. The connecting post 130 can be implemented using hybrid bonding technology. Hybrid bonding is also known as direct bond interconnect (DBI). For example, two wafers (first circuit layer 110 and second circuit layer 120) are covered with a dielectric material such as silicon dioxide (SiO2). Dielectric material is embedded in copper contacts connected to the chips. Then, the two chip contacts are brought together face to face, and heat treatment is used to allow the copper contacts of the two chips to expand and connect. In one embodiment, the second circuit layer 120 may further include circuit blocks implemented with digital signal processor (DSP) blocks, memory blocks, hard silicon intellectual property (hard IP), connection blocks, and / or switch blocks.

[0024] By establishing a signal transmission path along the third axis Z between each configuration memory 111 and a corresponding circuit block 121 through at least one connection post 130, the circuit block 121 can read the lookup table in the configuration memory 111 to implement the expected logical function based on the lookup table. In this embodiment, there are multiple connection posts 130, and each circuit block 121 only reads the lookup table of the corresponding configuration memory 111.

[0025] In this embodiment, the configuration memory 111 and the circuit block 121 are located on different circuit layers, and the circuit block 121 does not include a lookup table. Compared to configuring the configuration memory 111 within the circuit block 121, by configuring the configuration memory array independently of the circuit block 121 and on a different circuit layer, the configuration memory array is not limited by the electronic components in the circuit block 121 and can be configured more compactly. This effectively utilizes the high-density characteristics of static random access memory, resulting in a smaller area for the configuration memory array, effectively reducing the overall area and wiring length of the configuration memory array. Furthermore, once the three-dimensional semiconductor device 1 is programmed, it remains in a read state, resulting in higher read tolerance and suitability for wiring implemented with hybrid bonding. Simultaneously, the signal transmission capability of the hybrid bonding wiring allows the three-dimensional semiconductor device 1 to transmit signals at a higher read frequency. Even with increased transmission load from the hybrid bonding wiring, the read capability of the configuration memory 111 is not affected. Therefore, this application can achieve the purpose of reducing the wiring length and signal delay.

[0026] Please refer to Figure 2, which is a schematic diagram of an embodiment of the three-dimensional semiconductor device of this application. The three-dimensional semiconductor device 2 includes a first circuit layer 210 and a second circuit layer 220. The first circuit layer 210 includes a plurality of first circuit blocks 211, a plurality of first connection areas 212, and a plurality of first switch blocks 213. The plurality of first circuit blocks 211 and the plurality of first connection areas 212 are arranged alternately. Each first circuit block 211 is electrically connected to at least one first switch block 213 through a trace of at least one adjacent first connection area 212, so as to establish an electrical connection on a two-dimensional plane between the plurality of first circuit blocks 211 through the electrically connected first switch blocks 213. The first switch block 213 is, for example, a circuit block including logic circuits and memory. The second circuit layer 220 is disposed on the first circuit layer 210. The second circuit layer 220 includes a plurality of second circuit blocks 221, a plurality of second connection areas 222, and a plurality of second switch blocks 223. The second switch block 223 of the second circuit layer 220 is connected to the first switch block 213 of the first circuit layer 210 through the connecting post 230. The second switch block 223 is, for example, a circuit block including logic circuits and memory.

[0027] The vertical projections of the first switch block 213 and the second switch block 223 connected by the connecting post 230 on the first circuit layer 210 overlap at least partially. For example, the second switch block 223a of the second circuit layer 220 is connected to the first switch block 213a of the first circuit layer 210 through the connecting post 230, and the vertical projections (on the third axis Z) of the first switch block 213a and the second switch block 223a on the first circuit layer 210 overlap. Therefore, in addition to signal transmission in a two-dimensional plane (first axis X and second axis Y) through the traces of the first switch block 213 of the first circuit block 211 and the second switch block 223 of the second circuit layer 220, signal transmission between the first switch block 213 and the second switch block 223 in the third dimension (third axis Z) can also be achieved through the connecting post 230. This effectively reduces the trace length between the first switch block 213 and the second switch block 223, thereby reducing the signal delay caused by the trace length, achieving the purpose of reducing the trace length and signal delay of the wiring, and increasing the flexibility and convenience of the wiring design.

[0028] In one embodiment, the first circuit block 211 and the second circuit block 221 may be implemented by a logic block, a digital signal processor (DSP) block, a memory block, or a hardened silicon intellectual property (HIP). In one embodiment, the first circuit block 211 and the second circuit block 221 may be the same or different. For example, the first circuit block 211 may be a logic block, and the second circuit block 221 may be a logic block and a memory block. In one embodiment, the first circuit block 211 may be implemented by a circuit including a configuration memory and a first logic block, and the second circuit block 221 may be implemented by a circuit including a second logic block. The second logic block of the second circuit block 221 is electrically connected to the configuration memory of the first circuit block 211 through at least one connection post 230 (as shown in the three-dimensional semiconductor device 3 in FIG3), wherein the configuration memory stores a lookup table corresponding to the second logic block. That is, the second circuit block 221 does not have a configuration memory for the second logic block. In this way, the configuration memory and the second logic block can establish signal transmission along the third axis Z. In other embodiments, the memory of the multiple second connection areas 222 and multiple second switch blocks 223 of the second circuit layer 220 can also be implemented in the first circuit block 211. By centrally configuring memory components (the configuration memory, memory, etc. mentioned above) in a single circuit layer (first circuit layer 210), the design flexibility of the first circuit layer 210 and the second circuit layer 220 can be further improved. At the same time, the first circuit block 211 and the second circuit block 221 can also establish signal transmission along the third axis Z through the first switch block 213 and the second switch block 223 according to design requirements. In this way, the first circuit layer 210 and the second circuit layer 220 can be configured with different functional circuit blocks according to different requirements, so as to optimize the wiring according to design requirements, improve the wiring feasibility, reduce the signal delay caused by the wiring length, and achieve the purpose of reducing the wiring length and signal delay. In one embodiment, the first circuit block 211 and the second circuit block 221 may be manufactured using the same or different processes. For example, the first circuit block 211 may be implemented using a 5-nanometer process, and the second circuit block 221 may be implemented using a 5-nanometer or 3-nanometer process. This allows the first circuit block 211 and the second circuit block 221 to be manufactured using appropriate processes according to product requirements, thereby further reducing the manufacturing cost of the three-dimensional semiconductor device.

[0029] Please refer to Figures 4 to 7. Figure 4 is a schematic diagram of a disjoint topology for the switch block. Figure 5 is an embodiment of a universal topology for the switch block. Figure 6 is a Wilton topology for the switch block. Figure 7 is a schematic diagram of a combined embodiment of the switch block. In Figures 4 to 6, each switch block can define a first side S1, a second side S2, a third side S3, and a fourth side S4. Each side has connection terminals T0 to T4. Connection terminals T0 to T4 on different sides are connected through a switch unit. Switch blocks with different topologies have different connection structures. For example, in the embodiment of Figure 4, the connection terminal T0 of the first side S1 of the switch block is individually connected to the connection terminals T0 of the second side S2, the third side S3, and the fourth side S4. In the embodiment of Figure 5, the connection terminal T0 of the first side S1 of the switch block is individually connected to the connection terminals T0 of the second side S2, the third side S3, and the fourth side S4. In the embodiment shown in Figure 6, the connection terminal T0 of the first side S1 of the switch block is individually connected to the connection terminal T1 of the second side S2, the connection terminal T0 of the third side S3, and the connection terminal T0 of the fourth side S4. In this embodiment, the connection terminals T0 to T4 of the two switch blocks (e.g., the first switch block 213 and the second switch block 223) located on the same side are connected through the connecting post 230. For example, the connection terminal T0 of the first side S1 of the first switch block 213 is connected to the connection terminal T0 of the first side S1 of the second switch block 223 through the connecting post 230. Thus, the first switch block 213 and the second switch block 223 can establish signal transmission in the third dimension through the connecting post 230. In one embodiment, the topology of the first switch block 213 and the topology of the second switch block 223 may be the same or different. For example, the topology of the first switch block 213 may be general-purpose, while the topology of the second switch block 223 may be general-purpose or Wilton-type. Therefore, as shown in Figure 7, the combination between the first switch block 213 and the second switch block 223 can be achieved through at least nine topological combinations (G0~G8). This increases the flexibility in switch block configuration and overall circuit design.

[0030] In summary, the three-dimensional semiconductor device embodiment of this application effectively reduces the area and wiring required for the configuration memory by centrally placing the configuration memory of the logic blocks on an independent circuit layer, and achieves signal transmission between the logic blocks and the configuration memory in the third dimension through connecting posts. Furthermore, another embodiment of the three-dimensional semiconductor device of this application effectively reduces the trace length between switch blocks on different circuit layers by using connecting posts to achieve signal transmission in the third dimension. Thus, this application achieves the goal of reducing trace length and signal delay.

[0031] 1, 2, 3: Three-dimensional semiconductor devices 110: First circuit layer 111: Configure memory 120: Second circuit layer 121: Circuit Block 130: Connecting Post 210: First circuit layer 211: First circuit block 212: First Connection Area 213, 213a: First switch block 220: Second circuit layer 221: Second Circuit Block 222: Second connection area 223, 223a: Second switch block 230: Connecting Post S1: First side S2: Second side S3: Third side S4: Fourth side T0~T4: Connection end G0~G8: Topology Combinations X: First axis Y: Second axis Z: Third axis

Claims

1. A three-dimensional semiconductor device, comprising: A first circuit layer, including a first switching block; A second circuit layer is disposed on the first circuit layer, including a second switch block, the second switch block being electrically connected to the first switch block through a connecting post, the vertical projections of the second switch block, the first switch block, and the connecting post at least partially overlapping on the first circuit layer; wherein the topology of the first switch block and the second switch block are the same or different.

2. The three-dimensional semiconductor device as claimed in claim 1, wherein, The topology includes a split type, a general type and a Wilton type.

3. The three-dimensional semiconductor device as claimed in claim 1, wherein, The first switch block and the second switch block include a plurality of connection terminals, and the connection terminals of the first switch block are electrically connected to the connection terminals of the second switch block through a plurality of connection posts.

4. The three-dimensional semiconductor device as claimed in claim 3, wherein, The connection terminals of the first switch block and the second switch block, which are located on the same side, are connected through the connection posts.

5. The three-dimensional semiconductor device as claimed in claim 1, wherein, The first circuit layer includes a configuration memory and a first logic block, and the second circuit layer includes a second logic block. The second logic block is electrically connected to the configuration memory through a connection post. The configuration memory and the second logic block are located in different circuit layers.

6. The three-dimensional semiconductor device as claimed in claim 1, wherein, The first circuit layer and the second circuit layer are implemented by a field-programmable logic gate array.

7. The three-dimensional semiconductor device as claimed in claim 1, wherein, The first circuit layer includes a first circuit block, and the second circuit layer includes a second circuit block. The first circuit block and the second circuit block may be functional circuit blocks that are the same or different from each other.

8. The three-dimensional semiconductor device as claimed in claim 7, wherein, The first circuit block and the second circuit block include a logic block, a digital signal processor block, a memory block, and a hard silicon intellectual property.

9. The three-dimensional semiconductor device as claimed in claim 1, wherein, The manufacturing process of the first circuit layer may be the same as or different from that of the second circuit layer.

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