Manufacturating method of back side illumination image sensor
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2025-01-22
- Publication Date
- 2026-08-01
AI Technical Summary
Back-illuminated image sensors suffer from optical crosstalk due to light reflection by deep trench isolation structures, and increasing trench depth to reduce crosstalk causes silicon damage, lowering yield and efficiency.
A manufacturing method that forms isolation structures with a zigzag configuration using wet etching, reducing light reflection and silicon damage by forming recesses with specific distance relationships and materials.
Improves sensing efficiency and yield by minimizing optical crosstalk and silicon damage through a zigzag substrate structure and wet etching process.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This disclosure relates to a method for manufacturing an image sensor, and more particularly to a method for manufacturing a back-illuminated image sensor. [Previous Technology]
[0002] Back-illuminated image sensors are widely used in many electronic devices. However, when using a back-illuminated image sensor to sense incident light, some of the incident light may be reflected by the deep trench isolation (DTI) structure formed in the substrate, causing optical crosstalk between adjacent photosensitive elements, which will affect the sensing efficiency of the back-illuminated image sensor.
[0003] Furthermore, since the deep trench structure is formed by a dry etching process, if the depth of the deep trench structure is increased in order to reduce the above-mentioned optical crosstalk, it will increase the occurrence of silicon damage on the substrate, resulting in a decrease in the yield of the back-illuminated image sensor. [Summary of the Invention]
[0004] This disclosure provides a method for manufacturing a back-illuminated image sensor, which produces a back-illuminated image sensor with relatively good sensing efficiency and / or yield.
[0005] The method for manufacturing a back-illuminated image sensor disclosed herein includes the following steps. First, a first isolation structure is formed on a first surface of a substrate, which includes the following steps: forming a first opening on the first surface of the substrate; performing a first etching process on the first opening of the substrate to form a first recess; and filling the first recess of the substrate with a first filler layer and filling the first opening of the substrate with a first dielectric layer. Next, a second isolation structure is formed on a second surface of the substrate, which includes the following steps: forming a second opening on the second surface of the substrate; performing a second etching process on the second opening of the substrate to form a second recess; and filling the second recess and the second opening of the substrate with a second filler layer. In the back-illuminated image sensor disclosed herein, the shortest distance between the tip of the second recess and the first surface of the substrate is less than the shortest distance between the tip of the first recess and the first surface of the substrate.
[0006] Based on the above, in the manufacturing method of the back-illuminated image sensor provided in this disclosure, by making the shortest distance between the tip of the second recess and the first surface of the substrate smaller than the shortest distance between the tip of the first recess and the first surface of the substrate, the level of the second isolation structure formed in the second recess can be lower than the level of the first isolation structure formed in the first recess, which makes the substrate between the second isolation structure and the first isolation structure have a zigzag structure. Based on this, the situation where incident light is reflected by the second isolation structure and enters adjacent photosensitive elements can be reduced, thereby reducing the phenomenon of optical crosstalk and improving the sensing efficiency of the back-illuminated image sensor disclosed in this disclosure.
[0007] Furthermore, in the manufacturing method of the back-illuminated image sensor disclosed herein, the first recess in the first trench and the second recess in the second trench are formed by performing a wet etching process, which can reduce silicon damage caused by etching the substrate, thereby increasing the yield of the back-illuminated image sensor disclosed herein, thereby improving the quantum efficiency of the back-illuminated image sensor disclosed herein.
Implementation Method
[0008] The following examples, in conjunction with the accompanying drawings, are provided to describe the present disclosure in detail, but the examples provided are not intended to limit the scope of the disclosure. Furthermore, the accompanying drawings are for illustrative purposes only, and certain elements in the drawings are not drawn to scale. For ease of understanding by the reader, the same elements will be identified using the same symbols in the following description.
[0009] Figures 1A to 1I are partial cross-sectional schematic diagrams of a method for manufacturing a back-illuminated image sensor according to an embodiment of the present disclosure.
[0010] Referring to Figures 1A to 1I, in this embodiment, the back-illuminated image sensor 10 can be formed by performing the following steps, but this disclosure is not limited thereto.
[0011] Step (1): Form an isolation structure IS1 in the substrate SB.
[0012] In this embodiment, the isolation structure IS1 can be formed by performing the following steps, but this disclosure is not limited thereto.
[0013] Proceed to step (1a): Provide substrate SB.
[0014] The substrate SB may be, for example, a semiconductor substrate. In some embodiments, the material of the substrate may include silicon, doped silicon, germanium, silicon-germanium, semiconductor compounds, other suitable semiconductor materials, or combinations thereof. In this embodiment, the substrate SB is an epitaxial silicon substrate, but this disclosure is not limited thereto. Additionally, referring to FIG1A, the substrate SB has a first surface S1 and a second surface S2 opposite thereto.
[0015] Step (1b): A hard mask layer HM1 is formed on the first surface S1 of the substrate SB.
[0016] Referring to FIG1A, the hard mask layer HM1 may be formed, for example, by performing a suitable deposition process, and this disclosure is not limited thereto. In some embodiments, the material of the hard mask layer HM1 may include silicon nitride.
[0017] It is worth noting that before forming the hard mask layer HM1, a dielectric layer IL1 and a conductive layer CL can be sequentially formed on the first surface S1 of the substrate SB.
[0018] The dielectric layer IL1 may be formed, for example, by performing a suitable deposition process or thermal oxidation process, and this disclosure is not limited thereto. In some embodiments, the material of the dielectric layer IL1 may include silicon oxide. A portion of the dielectric layer IL1 may serve, for example, as a gate dielectric layer (e.g., a gate dielectric layer for transferring a transistor) to be subsequently formed, but this disclosure is not limited thereto.
[0019] The conductive layer CL can be formed, for example, by performing a suitable deposition process, and this disclosure is not limited thereto. In some embodiments, the material of the conductive layer CL may include polycrystalline silicon. A portion of the conductive layer CL may serve, for example, as a gate (e.g., a gate for a transfer transistor) of a subsequently formed transistor (not shown), but this disclosure is not limited thereto.
[0020] It is worth noting that after the hard mask layer HM1 is formed, an anti-reflective layer ARC can be formed on the first surface S1 of the substrate SB.
[0021] The anti-reflective layer ARC can be formed, for example, by performing a suitable coating process, and this disclosure is not limited thereto. In some embodiments, the material of the anti-reflective layer ARC may include a suitable inorganic or organic material.
[0022] Step (1c): Patterning process is performed on the rigid mask layer HM1.
[0023] Referring to FIG1A, in this embodiment, a portion of the hard mask layer HM1 can be removed by first forming a photoresist layer PR1 on the hard mask layer HM1, and then using the photoresist layer PR1 to perform an etching process on the hard mask layer HM1. However, this disclosure is not limited thereto. The photoresist layer PR1 can be formed, for example, by performing a suitable coating process and / or lithography process. This disclosure is not limited thereto. It is worth noting that a portion of the substrate SB may be removed during this patterning process.
[0024] In addition, during the patterning process of the hard mask layer HM1, a portion of the anti-reflective layer ARC, dielectric layer IL1 and conductive layer CL are also removed in this patterning process to expose a portion of the substrate SB.
[0025] It is worth noting that after patterning the hard mask layer HM1 and the substrate SB, the photoresist layer PR1 is removed. The photoresist layer PR1 can be removed, for example, by performing a suitable stripping process, and this disclosure is not limited thereto.
[0026] Step (1d): Use patterned hard mask layer HM1 as a mask to perform an etching process on substrate SB to form opening OP1.
[0027] Referring to FIG1B, in this embodiment, the exposed substrate SB can be etched using a patterned hard mask layer HM1 as a mask to form an opening OP1. In some embodiments, the above-described etching process can be a wet etching process or a dry etching process, and this disclosure is not limited thereto.
[0028] Step (1e): A hard mask layer HM2 is formed on the first surface S1 of the substrate SB.
[0029] Referring to Figure 1B, the hard mask layer HM2 can be formed, for example, by performing a suitable deposition process, and this disclosure is not limited thereto. In some embodiments, the material of the hard mask layer HM2 may include silicon nitride.
[0030] In this embodiment, a portion of the rigid mask layer HM2 is formed in the opening OP1.
[0031] Step (1f): Patterning process is performed on the rigid mask layer HM2.
[0032] Referring to FIG1B, in this embodiment, a portion of the hard mask layer HM2 can be removed by first forming a photoresist layer PR2 on the hard mask layer HM2, and then using the photoresist layer PR2 to perform an etching process on the hard mask layer HM2. However, this disclosure is not limited thereto. The photoresist layer PR2 can be formed, for example, by performing a suitable coating process and / or lithography process. This disclosure is not limited thereto.
[0033] In this embodiment, the hard mask layer HM2 located on the sidewall of the opening OP1 and a portion of the hard mask layer HM2 located on the bottom of the opening OP1 are removed in this patterning process.
[0034] Step (1g): Use patterned hard mask layer HM2 as a mask to perform an etching process on substrate SB to form recessed IP1.
[0035] Referring to FIG1C, in this embodiment, a patterned hard mask layer HM2 can be used as a mask to first perform a dry etching process on the opening OP1 of the substrate SB, and then perform a wet etching process on the opening OP1 of the substrate SB to form a recess IP1. In some embodiments, the etching solution used in the above-mentioned wet etching process can be tetramethylammonium hydroxide (TMAH), but this disclosure is not limited thereto.
[0036] In this embodiment, the recessed IP1 may have vertical sidewalls and inclined sidewalls. Specifically, the vertical sidewalls of the recessed IP1 are formed by performing the aforementioned dry etching process, and the inclined sidewalls of the recessed IP1 are formed by performing the aforementioned wet etching process. In this embodiment, the bottom of the recessed IP1 may have a pointed tip t1. In other words, the recessed IP1 may, for example, have an inverted pyramid array (IPA) structure.
[0037] In this embodiment, the opening OP1 and the recess IP1 can form a ditch Tr1.
[0038] It is worth noting that after the recessed IP1 is formed, the patterned hard mask layer HM2 is removed. The patterned hard mask layer HM2 can be removed, for example, by performing an etch-back process, but this disclosure is not limited thereto.
[0039] Step (1h): A dielectric layer IL2 is formed on the first surface S1 of the substrate SB.
[0040] Referring to FIG1D, in this embodiment, the dielectric layer IL2 can be formed by in-situ vapor generation (ISSG), but this disclosure is not limited thereto. In some embodiments, the material of the dielectric layer IL2 may include silicon oxide, but this disclosure is not limited thereto.
[0041] In this embodiment, a portion of the dielectric layer IL2 is formed in the trench Tr1. Specifically, the dielectric layer IL2 is formed in the opening OP1 and the recess IP1.
[0042] Step (1i): A filling material layer FML is formed on the first surface S1 of the substrate SB.
[0043] Referring to FIG1D, the filler material layer FML can be formed, for example, by performing a suitable deposition process, and this disclosure is not limited thereto. In this embodiment, the material of the filler material layer FML includes silicon nitride.
[0044] In this embodiment, a portion of the filler material layer FML is filled into the trench Tr1. Specifically, the filler material layer FML is filled into the opening OP1 and the recess IP1.
[0045] Proceed to step (1j): Remove a portion of the filler material layer FML to form the filler layer FL1.
[0046] Referring to FIG1E, in this embodiment, a portion of the filler material layer FML is removed by a pull-back process. Specifically, the filler material layer FML located outside the recess IP1 can be removed by performing a wet etching process on the filler material layer FML to form the filler layer FL1. In some embodiments, the etchant used in the above-described wet etching process may be phosphoric acid, but this disclosure is not limited thereto.
[0047] It is worth noting that the filler layer FL1 formed by the pull-back process may have an arc shape. In detail, the top surface of the filler layer FL1 located in the recess IP1 may have an arc shape, but this disclosure is not limited thereto.
[0048] Step (1k): A dielectric layer IL3 is formed on the first surface S1 of the substrate SB.
[0049] Referring to Figure 1F, in this embodiment, the dielectric layer IL3 can be formed by first performing a high-density plasma (HDP) chemical vapor deposition process and then performing a planarization process, but this disclosure is not limited thereto. In some embodiments, the material of the dielectric layer IL3 may include silicon oxide, but this disclosure is not limited thereto.
[0050] In this embodiment, the dielectric layer IL3 is filled in the trench Tr1. Specifically, the dielectric layer IL3 may fill the opening OP1 and may fill a portion of the recess IP1, but this disclosure is not limited thereto.
[0051] Step (1l): Remove a portion of the dielectric layer IL3 to form an isolation structure IS1.
[0052] Referring to FIG1F, in this embodiment, a portion of the dielectric layer IL3 can be removed by performing a suitable etching process, but this disclosure is not limited thereto. It is worth noting that before removing a portion of the dielectric layer IL3, the conductive layer CL and the patterned hard mask layer HM1 are removed by performing a suitable etching process.
[0053] Thus, the step of forming the isolation structure IS1 is completed. In this embodiment, the isolation structure IS1 is a shallow trench isolation (STI) structure. Although the method for forming the isolation structure IS1 in this embodiment is described using the above method as an example, the method for forming the isolation structure IS1 disclosed herein is not limited thereto.
[0054] Step (2): Form an isolation structure IS2 in the substrate SB.
[0055] It is worth noting that, although not shown in the figures, a process for forming a photosensitive element (not shown) and an element layer (not shown) on the first surface S1 of the substrate SB may be performed between steps (1) and (2). The photosensitive element may be formed, for example, by performing an ion implantation process. In some embodiments, the photosensitive element may be a photodiode, but this disclosure is not limited thereto. In some embodiments, the element layer may include, for example, driving elements (e.g., transfer transistors) and / or wirings and other elements electrically connected to the photosensitive element, and this disclosure is not limited thereto.
[0056] In this embodiment, the isolation structure IS2 can be formed by performing the following steps, but this disclosure is not limited thereto.
[0057] Step (2a): Form an opening OP2 in the substrate SB.
[0058] Referring to FIG1G, firstly, a patterned hard mask layer HM3 is formed on the second surface S2 of the substrate SB. Next, the substrate SB is etched using this patterned hard mask layer HM3 as a mask to form an opening OP2. In some embodiments, the material of the patterned hard mask layer HM3 may be silicon oxide, and the above-described etching process may be a dry etching process, but this disclosure is not limited thereto.
[0059] In some embodiments, the opening OP2 is disposed corresponding to the isolation structure IS1 of the substrate SB in the Z direction. In this embodiment, the formation of the opening OP2 does not expose the isolation structure IS1.
[0060] Proceed to step (2b): Form a recess IP2 in the substrate SB.
[0061] Referring to FIG1H, in this embodiment, a wet etching process can be performed on the opening OP2 of the substrate SB by using a patterned hard mask layer HM3 as a mask to form a recess IP2. In some embodiments, the etching solution used in the above-described wet etching process may be tetramethylammonium hydroxide, but this disclosure is not limited thereto.
[0062] In this embodiment, the recessed IP2 may have sloping sidewalls, and the bottom of the recessed IP2 may have a pointed tip t2. In other words, the recessed IP2 may also have, for example, an inverted pyramid structure.
[0063] In this embodiment, the opening OP2 and the recess IP2 can form a trench Tr2. For example, the trench Tr2 does not contact the trench Tr1, that is, there is still a portion of the substrate SB between the trench Tr2 and the trench Tr1.
[0064] In this embodiment, the tip t2 of the recessed IP2 is located, for example, between the tips t1 of the adjacent recessed IP1 in a direction perpendicular to the direction Z, but this disclosure is not limited thereto.
[0065] Referring to FIG1H, in this embodiment, the distance D2 (i.e., the shortest distance) between the tip t2 of the recessed IP2 and the first surface S1 of the substrate SB in the Z direction is less than the distance D1 (i.e., the shortest distance) between the tip t1 of the recessed IP1 and the first surface S1 of the substrate SB in the Z direction. Specifically, the level of the tip t2 of the recessed IP2 is lower than the level of the tip t1 of the recessed IP1. Based on this, the substrate SB corresponding to the opening OP2 in the Z direction may have a zigzag structure, but this disclosure is not limited thereto.
[0066] It is worth noting that after the recessed IP2 is formed, the patterned hard mask layer HM3 is removed. The patterned hard mask layer HM3 can be removed, for example, by performing a suitable etching process, but this disclosure is not limited thereto.
[0067] Step (2c): A protective layer PL and a filling layer FL2 are sequentially formed on the second surface S2 of the substrate SB.
[0068] Referring to FIG1I, in this embodiment, the protective layer PL can be formed in the trench Tr2 by performing an atomic layer deposition process, but this disclosure is not limited thereto. In some embodiments, the material of the protective layer PL may include a dielectric material having a high dielectric constant, but this disclosure is not limited thereto.
[0069] In this embodiment, the filling layer FL2 can be formed in the trench Tr2 by performing a suitable deposition process, wherein the filling layer FL2 is filled in the trench Tr2, but this disclosure is not limited thereto. In some embodiments, the material of the filling layer FL2 may include silicon oxide, but this disclosure is not limited thereto.
[0070] Thus, the step of forming the isolation structure IS2 is completed. In this embodiment, the isolation structure IS2 is a deep trench isolation (DTI) structure. Although the method for forming the isolation structure IS2 in this embodiment is described using the above method as an example, the method for forming the isolation structure IS2 disclosed herein is not limited thereto.
[0071] In this embodiment, the recess IP1 in the trench Tr1 and the recess IP2 in the trench Tr2 are both formed by a wet etching process. Therefore, it can reduce the silicon damage caused by the dry etching process on the substrate SB.
[0072] It is worth noting that in some embodiments, after the isolation structure IS2 is formed, the well-known subsequent processes of the back-illuminated image sensor 10 can be performed (e.g., the processes of forming a color filter layer and a microlens are performed sequentially), but this disclosure is not limited thereto.
[0073] Thus, the fabrication of the back-illuminated image sensor 10 is completed. Although the manufacturing method of the back-illuminated image sensor 10 in this embodiment is described using the above method as an example, the manufacturing method of the back-illuminated image sensor disclosed herein is not limited thereto.
[0074] In the manufacturing method of the back-illuminated image sensor 10 provided in this embodiment, by making the distance D2 between the tip t2 of the recess IP2 located on the second surface S2 side of the substrate SB and the first surface S1 of the substrate SB in the Z direction smaller than the distance D1 between the tip t1 of the recess IP1 located on the first surface S1 side of the substrate SB and the first surface S1 of the substrate SB in the Z direction, the level of the isolation structure IS2 formed in the recess IP2 can be lower than the level of the isolation structure IS1 formed in the tip t1 of the recess IP1, which makes the substrate SB between the isolation structure IS2 and the isolation structure IS1 have a tortuous structure. Based on this, the situation where light filtered by the color filter layer is reflected by the isolation structure IS2 and enters a photosensitive element that is not corresponding to this color filter layer can be reduced, thereby reducing the phenomenon of optical crosstalk and improving the sensing efficiency of the back-illuminated image sensor 10 of this embodiment.
[0075] Furthermore, in the manufacturing method of the back-illuminated image sensor 10 provided in this embodiment, the recess IP1 in the trench Tr1 and the recess IP2 in the trench Tr2 are formed by performing a wet etching process, which can reduce the silicon damage caused by etching the substrate SB, thereby increasing the yield of the back-illuminated image sensor 10 in this embodiment and thereby improving the quantum efficiency of the back-illuminated image sensor 10 in this embodiment. [Simplified Explanation of the Diagram]
[0076] Figures 1A to 1I are partial cross-sectional schematic diagrams of a method for manufacturing a back-illuminated image sensor according to an embodiment of the present disclosure.
Claims
1. A method for manufacturing a back-illuminated image sensor, comprising: Forming a first isolation structure on a first surface of a substrate includes: forming a first opening on the first surface of the substrate; performing a first etching process on the first opening of the substrate to form a first recess; filling the first recess of the substrate with a first filler layer and filling the first opening of the substrate with a first dielectric layer; and forming a second isolation structure on a second surface of the substrate includes: forming a second opening on the second surface of the substrate; performing a second etching process on the second opening of the substrate to form a second recess; and filling the second recess and the second opening of the substrate with a second filler layer, wherein between the step of forming the first isolation structure and the step of forming the second isolation structure, a process of forming a photosensitive element and an element layer is performed on the first surface of the substrate, wherein the element layer is electrically connected to the photosensitive element, and wherein the shortest distance between the tip of the second recess and the first surface of the substrate is less than the shortest distance between the tip of the first recess and the first surface of the substrate.
2. The method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the second isolation structure is not in contact with the first isolation structure.
3. The method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the first etching process and the second etching process are wet etching processes.
4. A method for manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the step of forming the first opening on the first surface of the substrate comprises: A first rigid mask layer and a first photoresist layer are sequentially formed on the first surface of the substrate; The first patterned hard mask layer is patterned using the first photoresist layer to form the first patterned hard mask layer; and the substrate is patterned using the first patterned hard mask layer.
5. The method of manufacturing a back-illuminated image sensor as claimed in claim 4, wherein a second dielectric layer and a conductive layer are sequentially formed on the first surface of the substrate before the first hard mask layer is formed.
6. The method of manufacturing a back-illuminated image sensor as described in claim 4, wherein an anti-reflective layer is formed on the first rigid mask layer before the first photoresist layer is formed.
7. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the step of forming the first recess includes: A second rigid mask layer and a second photoresist layer are sequentially formed on the first surface of the substrate; The second hard mask layer is patterned using the second photoresist layer to form a second patterned hard mask layer, wherein the second patterned hard mask layer exposes a portion of the bottom surface of the first opening; and the substrate is patterned using the second patterned hard mask layer.
8. A method for manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the step of filling the first filler layer in the first recess of the substrate comprises: A filling material layer is formed in the first opening and the first recess of the substrate; And the filler material layer located outside the first recess is removed using a pull-back process.
9. A method of manufacturing a back-illuminated image sensor as claimed in claim 8, wherein the pull-back process includes a wet etching process of the filler material layer.
10. A method for manufacturing a back-illuminated image sensor as claimed in claim 8, wherein the filler material layer is formed using a near-field vapor generation method.
11. A method of manufacturing a back-illuminated image sensor as claimed in claim 10, wherein the material of the filling material layer comprises silicon nitride.
12. A method of manufacturing a back-illuminated image sensor as claimed in claim 8, wherein the top surface of the first filling layer has an arc shape.
13. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the step of filling the first dielectric layer into the first opening in the substrate includes performing a high-density plasma chemical vapor deposition process and a planarization process.
14. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the step of forming the second opening on the second surface of the substrate comprises: A third patterned hard mask layer is formed on the second surface of the substrate; And the substrate is patterned using the third patterned hard mask layer.
15. A method of manufacturing a back-illuminated image sensor as claimed in claim 14, wherein the step of forming the second recess includes: The second etching process is performed using the third patterned hard mask layer as a mask, wherein the third patterned hard mask layer exposes the bottom surface of the second opening.
16. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein, prior to forming the second filler layer, a protective layer is further formed on the second surface of the substrate.
17. A method of manufacturing a back-illuminated image sensor as claimed in claim 16, wherein the protective layer is formed by performing an atomic layer deposition process.
18. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the first isolation structure is a shallow trench isolation structure.
19. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein the second isolation structure is a deep trench isolation structure.
20. A method of manufacturing a back-illuminated image sensor as claimed in claim 1, wherein after forming the second isolation structure on the second surface of the substrate, the method further comprises: A color filter layer is formed on the filler layer; And microlenses are formed on the color filter layer.