Integrated circuit and forming method thereof

Abstract

A process forms alternating first and second metal lines in an interlevel dielectric layer. A first photolithography and etching process forms trenches in a patterning layer. A plurality of dielectric spacers are formed on sidewalls of the trenches. A second photolithography and etching process forms a pattern of the first metal lines in a hard mask layer between the interlevel dielectric layer and the patterning layer based on the dielectric spacers. A third photolithography and etching process forms a pattern of a second metal lines in the hard mask layer based on the dielectric spacers. The patterns of the first and second metal lines are then transferred by an etching process to the interlevel dielectric layer as trenches in the interlevel dielectric layer. The first and second groups of the metal lines are then formed simultaneously by depositing a metal material in the trenches in the interlevel dielectric layer.

Description

[Technical Field]

[0001] This disclosure relates to an integrated circuit, and more particularly to an integrated circuit and a method of forming the same. [Previous Technology]

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have led to the production of several generations of integrated circuits, each with smaller and more complex circuitry than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnects per wafer area) has generally increased, while geometry (i.e., the smallest element (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically benefits production efficiency and reduces associated costs. This miniaturization also increases the complexity of handling and fabricating integrated circuits.

[0003] One aspect of integrated circuit processing is forming metal lines in a dielectric layer. During miniaturization, the width of the metal lines is reduced to a desired size, increasing the density of the metal lines. However, miniaturization presents challenges when it comes to patterning and forming metal lines with continuously decreasing widths and spacing. These challenges can lead to metal line distortion. This distortion may include unintended widening of the metal lines, resulting in increased capacitance or even short circuits.

[0004] All topics discussed in the Background Art section are not necessarily prior art, and should not be considered prior art solely because of their discussion in the Background Art section. In this manner, unless explicitly stated as prior art, any knowledge of problems in or related to the prior art discussed in the Background Art section should not be considered prior art. In fact, the discussion of any topic in the Background Art section should be considered part of the inventor's method for solving a particular problem, which itself may also be novel. [Summary of the Invention]

[0005] In some embodiments, a method of forming an integrated circuit includes the following steps: forming a patterned layer over an interlayer dielectric layer of an integrated circuit; forming a plurality of first trenches in the patterned layer using a first photolithography process; conformally depositing a dielectric layer on the patterned layer and in the first trenches; forming a plurality of spacers from the dielectric layer by removing the dielectric layer from a top surface of the patterned layer, each of the spacers being lined with a plurality of sidewalls of each of the first trenches; forming a plurality of first metal lines in the interlayer dielectric layer, each of the first metal lines being laterally self-aligned with one of the spacers; and forming a plurality of second metal lines in the interlayer dielectric layer, the second metal lines being laterally intersecting with the first metal lines and each being laterally self-aligned with a gap between adjacent spacers.

[0006] In some embodiments, a plurality of first trenches are formed in a patterned layer above an interlayer dielectric layer using a first lithography and etching process; a plurality of spacers are formed, each of which is lined with a plurality of sidewalls of each of the first trenches and is isolated from each other; a plurality of second trenches are formed in a hard mask layer below the patterned layer using a second lithography process; and a plurality of third trenches are formed in the hard mask layer that are laterally alternating with the second trenches, the second trenches and the third trenches being laterally self-aligned with the spacers.

[0007] In some embodiments, an integrated circuit includes a plurality of transistors; an interlayer dielectric layer above the transistors; a plurality of first metal lines extending in the interlayer dielectric layer in a first lateral direction; and a plurality of second metal lines extending in the interlayer dielectric layer in the first lateral direction and alternating with the first metal lines in a second lateral direction transverse to the first lateral direction. The first metal lines have a plurality of different end-to-end dimensions, wherein the second metal lines have a plurality of different end-to-end dimensions.

Implementation Method

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower," "above," "upper," and the like are used herein to describe the relationship between one component or feature and another component(s) shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0010] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of this disclosure. However, those skilled in the art will understand that this disclosure can be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of this disclosure.

[0011] Unless the context otherwise requires, throughout the specification and the subsequent claims, the phrase “comprises” and its variations, such as “comprises / comprising”, shall be interpreted as open and inclusive, that is, as “including but not limited to”.

[0012] Using ordinal numbers such as first, second, and third does not necessarily imply an order of sequence, but rather can distinguish multiple instances of a behavior or structure.

[0013] The phrases "some embodiments" or "an embodiment" used throughout this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments. Therefore, the phrases "some embodiments" or "an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0014] As used in this specification and the accompanying claims, unless otherwise expressly provided, the singular forms "a" and "the" also include the plural references. It should also be noted that unless otherwise expressly provided, the term "or" is generally used as it includes "and / or".

[0015] As used herein, "light" generally refers to electromagnetic radiation of any wavelength unless a specific band or wavelength is specified. Therefore, unless otherwise specified, "light" means X-ray radiation, EUV radiation, ultraviolet (UV) radiation, visible light radiation, infrared radiation, or other bands, wavelengths, or categories of electromagnetic radiation. Furthermore, as used herein, "optical system" may include any system that receives / generates and utilizes electromagnetic radiation.

[0016] The embodiments disclosed herein provide a method for forming metal lines in an interlayer dielectric layer of an integrated circuit. A process forms a set of metal lines as a first set of metal lines and a second set of metal lines laterally intersecting the first set of metal lines. A patterned layer is formed above the interlayer dielectric layer. A first lithography and etching process forms tracks in the patterned layer. A plurality of dielectric spacers are formed on the sidewalls of the tracks, wherein the bottom of the tracks is exposed. A second lithography and etching process forms the pattern of the first set of metal lines in the patterned layer based on the dielectric spacers. A third lithography and etching process forms the pattern of the second set of metal lines in the patterned layer based on the dielectric spacers. Then, the patterns of the first and second sets of metal lines are transferred to the interlayer dielectric layer as trenches in the interlayer dielectric layer by an etching process. The first and second sets of metal lines are then simultaneously formed by depositing metal material in the trenches.

[0017] The embodiments disclosed herein offer several benefits. First, no separate lithography and etching processes are required to create breaks in the metal lines. Second, in the patterned layer, the trenches or windows of both the first and second sets of metal lines are confined by dielectric spacers. This allows both sets of metal lines to have multiple end-to-end dimensions or small dimensions (e.g., very small end-to-end distances). Excess line length and redundant metal are also significantly reduced. In unconstrained locations, the lines do not exhibit lateral scaling characteristics. This further leads to better integrated circuit functionality and fewer scrapped wafers.

[0018] Figures 1 to 13C are cross-sectional and top views of the integrated circuit 100 at various stages of processing according to some embodiments. Figures 1 to 13C illustrate the formation of metal lines in the interlayer dielectric layer. The process illustrated in Figures 1 to 13C efficiently and effectively forms metal lines with improved characteristics compared to other possible solutions. The process corresponds to the back end of line (BEOL) process.

[0019] Figure 1 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 1 illustrates an interlayer dielectric layer 102. In some embodiments, the interlayer dielectric layer includes a low-k dielectric material. In some embodiments, the interlayer dielectric layer 102 includes silicon oxide (e.g., SiO2). The interlayer dielectric layer 102 may include SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The interlayer dielectric layer 102 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) or other suitable deposition processes. The interlayer dielectric layer 102 has a thickness between 50 nm and 500 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0020] Although the interlayer dielectric layer 102 is shown as a single dielectric layer, in some embodiments, the interlayer dielectric layer 102 includes multiple dielectric layers stacked on top of each other.

[0021] In some embodiments, an interlayer dielectric layer 102 is formed over an active circuit region (not shown). The active circuit region includes a plurality of transistors. The transistors include PMOS transistors and NMOS transistors. In some embodiments, the transistors are core logic circuits. In some embodiments, the transistors form part of an SRAM array of integrated circuit 100.

[0022] In some embodiments, the active circuit region includes a semiconductor substrate. The channel region and source / drain region of the transistor are formed in conjunction with the semiconductor substrate. The gate dielectric layer and gate metal of the transistor are formed adjacent to the channel region. Gate contacts corresponding to conductive vias with conductive plugs extend downward to contact the gate region. Source / drain contacts corresponding to conductive vias or conductive plugs extend downward to contact the source / drain regions. Various dielectric layers including gate spacers are formed above the transistor structure.

[0023] An interlayer dielectric layer 102 is formed above various structures in the active circuit region. Although not shown in Figure 1, conductive vias may be formed in the lower part of the interlayer dielectric layer 102. Metal wires subsequently formed in the interlayer dielectric layer 102 may contact the conductive vias at selected locations.

[0024] In some embodiments, the integrated circuit 100 includes a hard mask layer 104 located above the interlayer dielectric layer 102. As will be described in more detail below, the hard mask layer 104 corresponds to a layer that will ultimately be patterned with a pattern corresponding to the layout of metal lines formed in the interlayer dielectric layer 102. After patterning the hard mask layer 104, trenches may be formed in the interlayer dielectric layer 102 according to the patterning of the hard mask layer 104. Conductive material may then be deposited in the trenches in the interlayer dielectric layer 102 to form metal lines in the trenches.

[0025] In some embodiments, the hard mask layer 104 includes a plurality of hard mask sublayers. In Figure 1, the hard mask layer 104 includes a first hard mask sublayer 106 located above the interlayer dielectric layer 102. The hard mask layer 104 includes a second hard mask sublayer 108 located above the first hard mask sublayer 106. The hard mask layer 104 includes a third hard mask sublayer 110 located above the second hard mask sublayer 108.

[0026] In some embodiments, the first hard mask sublayer 106 comprises tetraethoxysilane (TEOS). The first hard mask sublayer 106 may be deposited by CVD, ALD, or PVD. Other deposition processes and materials may be used for the first hard mask sublayer 106 without departing from the scope of this disclosure. The first hard mask sublayer 106 has a thickness between 20 nm and 28 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0027] In some embodiments, the second hard mask sublayer 108 comprises tungsten-doped carbon (tungsten-doped carbon). The second hard mask sublayer 108 may be deposited by CVD, ALD, or PVD. Other deposition processes and materials may be used for the second hard mask sublayer 108 without departing from the scope of this disclosure. The second hard mask sublayer 108 has a thickness between 10 nm and 15 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0028] In some embodiments, the third hard mask sublayer 110 comprises tetraethoxysilane (TEOS). The third hard mask sublayer 110 may be deposited by CVD, ALD, or PVD. Other deposition processes and materials may be used for the third hard mask sublayer 110 without departing from the scope of this disclosure. The third hard mask sublayer 110 has a thickness between 7 nm and 12 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0029] In some embodiments, the integrated circuit 100 includes a patterned layer 112 located on a hard mask layer 104. In an exemplary first figure, the patterned layer 112 is located on a third hard mask sublayer 110. As will be described in more detail below, the patterned layer 112 acts as a layer that assists in patterning the first set of metal lines and the second set of metal lines onto the hard mask layer 104. As will be described in more detail below, tracks or trenches are formed in the patterned layer 112. Spacers are then formed on the sidewalls of the tracks. The combination of the spacers and the patterned layer 112 facilitates patterning the first set of metal lines and the second set of metal lines onto the hard mask layer 104.

[0030] In some embodiments, the patterned layer 112 comprises amorphous silicon, which has good etch selectivity relative to the dielectric layer 106 spacers, thereby achieving strong self-alignment. In some embodiments, the patterned layer 112 is deposited by CVD, ALD, or PVD. In some embodiments, the patterned layer 112 has a thickness between 35 nm and 50 nm. Other materials, thicknesses, and deposition processes may be used for the patterned layer 112 without departing from the scope of this disclosure.

[0031] According to some embodiments, the integrated circuit 100 includes a dielectric layer 114 located on a patterned layer 112. In some embodiments, the dielectric layer 114 comprises amorphous carbon. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 114 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 114 without departing from the scope of this disclosure.

[0032] According to some embodiments, the integrated circuit 100 includes a dielectric layer 116 located on a dielectric layer 114. In some embodiments, the dielectric layer 116 includes SiOC. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 116 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 116 without departing from the scope of this disclosure.

[0033] In Figure 1, according to some embodiments, a photoresist layer 118 has been formed on the dielectric layer 116. The photoresist layer 118 comprises a material having a composition that changes upon exposure to lithography light. In some embodiments, the photoresist layer 118 comprises a material sensitive to extreme ultraviolet (EUV) radiation from about 13.5 nm. In some embodiments, the photoresist layer 118 comprises a positive photoresist. In some embodiments, the photoresist layer 118 comprises an organic photoresist.

[0034] In Figure 2A, a lithography process is performed. The lithography process includes exposing a photoresist layer 118 to lithography light that includes a pattern of a magnifying mask. After exposure, the exposed portion of the photoresist layer 118 is removed, thereby creating a pattern of trenches 120 in the photoresist layer 118. The pattern of the trenches 120 corresponds to the pattern of the magnifying mask. As will be explained in more detail below, this pattern of the trenches 120 will be used to form a set of initial tracks in the patterning layer 112.

[0035] Figure 2B is a top view of the processing stage of the integrated circuit 100 shown in Figure 2A according to some embodiments. The cross-sectional view of Figure 2A is taken along the cutting line 2A of Figure 2B. The top view of Figure 2B illustrates a rectangular trench 120 formed in the photoresist layer 118. The top surface of the dielectric layer 116 is exposed in the trench 120. Although Figure 2B illustrates a trench 120 with rectangular ends, in some embodiments, the trench 120 has rounded ends.

[0036] Figure 3A is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 3A, an etching process has been performed while the photoresist layer 118 is patterned. Specifically, a track 122 has been formed in the patterned layer 112. The track 122 has a pattern of track 122 of the photoresist layer 118. An etching process has been performed to etch dielectric layers 114 and 116 in a downward direction at locations exposed by the track 122. The etching process continues, and the patterned layer 112 is also etched in a downward direction at locations exposed by the track 122. As a result, the track 122 is formed in the patterned layer 112. The top surface of the hard mask sublayer 110 is exposed at the bottom of the track 122. The track 122 may also be referred to as a trench in the patterned layer 112.

[0037] In some embodiments, a single etching process is performed to etch through dielectric layers 116 and 114 and patterned layer 112. In some embodiments, multiple separate etching steps are performed to etch through dielectric layers 116 and 114 and patterned layer 112. The final etching step selectively etches the patterned layer 112 relative to the hard mask sublayer 110. As a result, the etching process terminates at the top surface of the hard mask sublayer 110 without substantially etching the hard mask layer 110. The etching process may include one or more dry etching steps with anisotropic etching in the down direction.

[0038] Figure 3B is a top view of the processing stage of the integrated circuit 100 shown in Figure 3A according to some embodiments. The cross-sectional view of Figure 3A is taken along the cutting line 3A of Figure 3B. The top view of Figure 3B illustrates a track 122 formed in a layer of patterned layer 112. The top surface of the hard mask sublayer 110 is exposed in the track 122. Although Figure 3B shows the track 122 as having rectangular ends, in some embodiments, the track 122 has rounded ends.

[0039] In Figure 4, according to some embodiments, a dielectric layer 124 has been deposited on the integrated circuit 100. The dielectric layer 124 is conformally deposited on the top surface of the patterned layer 112, the sidewalls of the patterned layer 112, and the top surface of the hard mask sublayer 110. In some embodiments, the dielectric layer 124 includes a material that can be selectively etched relative to the materials of the patterned layer 112 and the hard mask sublayer 110. In some embodiments, the dielectric layer 124 includes SiON, SiN, SiC, SiOC, SiOCN, SiO, or other suitable materials. The dielectric layer 124 has a thickness between 8 nm and 15 nm, corresponding to the vertical thickness of the dielectric layer 124 on the top surface of the patterned layer 112 and the lateral thickness on the sidewalls of the patterned layer 112. The dielectric layer 124 may be deposited by CVD, ALD, or PVD. Other materials, thicknesses, and deposition processes may be used for the dielectric layer 124 without departing from the scope of this disclosure.

[0040] Dielectric layer 124 is a spacer layer. As will be described in more detail below, dielectric layer 124 will be patterned to form spacers on the sidewalls of track 122. The spacers will be used to form a pattern of a first set of metal lines and a second set of metal lines intersecting the cross lines of the first set of metal lines.

[0041] Figure 5A is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 5A, an etching process has been performed with the dielectric layer 124 patterned. Specifically, spacers 125 have been formed from the dielectric layer 124 on the sidewalls of the patterned layer 112, corresponding to the sidewalls of the track 122. The etching process is an anisotropic etching process performed in the downward direction. The etching process is a timed etching process with a timing selected to remove a certain amount of material. The vertical thickness corresponds to the dielectric layer 124 at the top surface of the patterned layer 112 and the hard mask sublayer 110. Because the vertical thickness of dielectric layer 124 on the top surface of patterned layer 112 and hard mask sublayer 110 is less than its thickness on the sidewalls of patterned layer 112, dielectric layer 124 is completely removed from the top surface of patterned layer 112 and from the central portion of the exposed top surface of hard mask sublayer 110, without being removed from the sidewalls of patterned layer 112. As a result, spacer 125 is formed by dielectric layer 124 on the sidewalls of patterned layer 112. A portion of the top surface of hard mask sublayer 110 is exposed in track 122.

[0042] The formation of spacer 125 defines the general pattern of the first set of metal lines and the second set of metal lines in the interlayer dielectric layer 102. Specifically, the first set of metal lines will be formed below the position of track 122. The second set of metal lines will be formed below the position of the remaining portion of patterned layer 112. This is entirely defined by the position of spacer 125.

[0043] Figure 5B is a top view of the processing stage of the integrated circuit 100 shown in Figure 5A according to some embodiments. The cross-sectional view of Figure 5A is taken along the cutting line 5A of Figure 5B. The top view of Figure 5B illustrates spacers 125 that line and laterally enclose the track 122. The top surface of the hard mask sublayer 110 is exposed in the track 122.

[0044] As can be seen in the top view of Figure 5A, according to some embodiments, each spacer 125 encloses a region corresponding to the track 122. In some embodiments, the enclosed region is rectangular. In some embodiments, the enclosed region is elliptical. The enclosed region corresponds to the location where a first metal line will be formed in the interlayer dielectric layer 102 below it. The region 123 located between the enclosed regions corresponds to the location where a second set of metal lines will be formed in the interlayer dielectric layer 102 below it.

[0045] As described above, the area beneath each zone enclosed by the spacer 125 will be used to form one of the first metal lines. However, in practice, multiple first metal lines separated from each other in the Y direction may be formed beneath each enclosed area, as will be described in more detail below. Similarly, multiple second metal lines separated from each other in the Y direction may be formed beneath each zone 123 between adjacent spacers 125.

[0046] Figure 6 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 6, dielectric layer 128, dielectric layer 130, and photoresist layer 132 have been formed in preparation for a second lithography process. The second lithography process will be used to define the length (in the Y direction) and position of the first metal line.

[0047] A dielectric layer 128 is formed on the patterned layer 112, the spacer 125, and the exposed portion of the top surface of the hard mask sublayer 110. In some embodiments, the dielectric layer 128 comprises amorphous carbon. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 128 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 128 without departing from the scope of this disclosure.

[0048] According to some embodiments, dielectric layer 130 is formed on dielectric layer 128. In some embodiments, dielectric layer 130 comprises SiOC. In some embodiments, dielectric layer 130 is deposited by CVD, ALD, or PVD. In some embodiments, dielectric layer 130 has a thickness similar to that of dielectric layer 116. Other materials, deposition processes, and thicknesses may be used for dielectric layer 130 without departing from the scope of this disclosure.

[0049] According to some embodiments, a photoresist layer 132 has been formed on the dielectric layer 130. The photoresist layer 132 is made of the same material as the photoresist layer 118 in Figure 1.

[0050] Figure 7A is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 7A, a photolithography process has been performed. The photolithography process includes exposing a photoresist layer 132 to photolithography light including a pattern of a photomask. After exposure, the exposed portion of the photoresist layer 132 is removed, thereby creating a pattern of trenches 134 in the photoresist layer 132. The pattern of the trenches 134 corresponds to the pattern of the photomask.

[0051] Figure 7A illustrates trench 134 as having the same width in the X direction as trench 122. However, in some embodiments, trench 134 is wider than trench 122. Trench 134 overlaps with spacer 125. Because subsequent etching processes will not etch spacer 125, there is some leeway in the layout of trench 134. This helps to relax the alignment specifications of the trench 134 layout, as subsequent trenches will self-align with spacer 125 or trench 122.

[0052] Figure 7B is a cross-sectional view of the integrated circuit 100 according to some embodiments, showing the same processing stage as illustrated in Figure 7A. The cross-sectional view of Figure 7A is taken along cut line 7A, as shown in the top view of Figure 7C. The cross-sectional view of Figure 7B is taken along cut line 7B, as shown in the top view of Figure 7C. Figure 7C includes dashed lines indicating the position of the track 122 below the photoresist layer 132.

[0053] Figures 7B and 7C show that the groove 134 does not extend through the entire length of each track 122 in the Y direction. Instead, each groove 134 corresponds to a pattern of a single first metal wire. For the leftmost track 122, the single groove 134 is formed to correspond to a pattern of a single first metal wire. For the second track 122 from the left, two grooves 134 are formed and separated from each other in the Y direction, corresponding to patterns of two first metal wires. For the second track 122 from the right, the single groove 134 is formed to correspond to a pattern of a single first metal wire. For the rightmost track 122, the single groove 134 is formed to correspond to a pattern of a single first metal wire.

[0054] As will be explained in more detail below, the ends (in the Y direction) of each groove 134 are patterned without the need for separate masks to form cuts or breaks to separate adjacent metal lines. As a result, the ends of adjacent first metal lines can be extremely close. Furthermore, the ends of the first metal lines can be moved away from the ends of the track 122 as needed. This leads to a reduction in irrelevant or redundant metal. The first metal lines can be substantially exactly the same length (or short) as needed.

[0055] Figures 8A and 8B are cross-sectional views of an integrated circuit 100 according to some embodiments. Figure 8C is a top view of an integrated circuit 100 according to some embodiments. The cross-sectional views of Figures 8A and 8B are taken along cutting lines 8A and 8B in Figure 8C, respectively.

[0056] With the patterned layer of photoresist layer 132 present, an etching process has been performed. The etching process etches dielectric layers 130 and 128 at locations exposed by trench 134. The etching process also etches hard mask sublayer 110 at locations exposed by trench 134. The etching process is an anisotropic etching process that selectively etches in the down direction. In some embodiments, the etching process includes a single etching step that etches through dielectric layers 128 and 130 and hard mask sublayer 110. In some embodiments, the etching process includes multiple etching steps to etch through each layer separately. The etching process selectively etches exposed portions of the layers while substantially not etching spacer 125.

[0057] The final result of the etching process is the formation of trenches 136 in the hard mask sublayer 110 in the pattern of trenches 134 of the photoresist layer 132. Each trench 136 exposes the top surface of the hard mask sublayer 108. Each trench 136 corresponds to the pattern and location of an individual first metal line to be formed in the interlayer dielectric layer 102. As previously described with respect to Figures 7A to 7C, some tracks 122 correspond to the locations of a plurality of first metal lines separated from each other in the Y direction. Figure 8C illustrates this situation as trenches 136 being separated by portions of the hard mask sublayer 110 not etched based on the pattern of the photoresist layer 132. Figure 8C also illustrates how the location of the end trenches 136 can be selected without using individual masks for cutting or breaking.

[0058] Figure 9 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 9, dielectric layer 140, dielectric layer 142, and photoresist layer 144 have been formed in preparation for a third lithography process. The third lithography process will be used to define the length (in the Y direction) and position of the second metal line.

[0059] A dielectric layer 140 is formed on the patterned layer 112, on the spacers 125, on the exposed sidewalls of the hard mask sublayer 110, and on the exposed portion of the top surface of the hard mask sublayer 108. In some embodiments, the dielectric layer 140 comprises amorphous carbon. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 140 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 140 without departing from the scope of this disclosure.

[0060] According to some embodiments, dielectric layer 142 is formed on dielectric layer 140. In some embodiments, dielectric layer 142 comprises SiOC. In some embodiments, dielectric layer 142 is deposited by CVD, ALD, or PVD. In some embodiments, dielectric layer 142 has a thickness similar to that of dielectric layer 116. Other materials, deposition processes, and thicknesses may be used for dielectric layer 142 without departing from the scope of this disclosure.

[0061] According to some embodiments, a photoresist layer 144 has been formed on the dielectric layer 142. The photoresist layer 144 has a material similar to that of the photoresist layer 118 in Figure 1.

[0062] Figure 10A is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 10A, a photolithography process has been performed. The photolithography process includes exposing a photoresist layer 144 to photolithography light including a pattern of a photomask. After exposure, the exposed portion of the photoresist layer 144 is removed, thereby creating a pattern of trenches 146 in the photoresist layer 144. The pattern of the trenches 146 corresponds to the pattern of the photomask.

[0063] Figure 10A illustrates trench 146 as having the same width in the X direction as the portion 112 of patterned layer 112 below trench 146. However, in some embodiments, trench 146 is wider than a portion of patterned layer 112. Trench 146 overlaps with spacer 125. Because subsequent etching processes will not etch spacer 125, there is some leeway in the layout of trench 146. This helps to relax the alignment specifications of the trench 146 layout, as subsequent trenches will self-align with spacer 125 or the area 123 between spacer 125.

[0064] Figure 10B is a cross-sectional view of the integrated circuit 100 according to some embodiments, showing the same processing stage as illustrated in Figure 10A. The cross-sectional view of Figure 10A is taken along cut line 10A, as shown in the top view of Figure 10C. The cross-sectional view of Figure 10B is taken along cut line 10B, as shown in the top view of Figure 10C. Figure 10C includes dashed lines indicating the location of region 123 corresponding to the region between spacers 125 below the photoresist layer 144.

[0065] Figures 10B and 10C show that the trench 146 does not extend through the entire length of each region 123 in the Y direction. Instead, each trench 146 corresponds to a pattern of a single second metal wire. For the leftmost region 123, the single trench 146 is formed to correspond to a pattern of a single second metal wire. For the middle region 123, a single trench 146 is formed to correspond to the position of a single second metal wire. For the rightmost region 123, two trenches 146 are formed to be separated from each other in the Y direction and to correspond to patterns of two second metal wires.

[0066] As will be explained in more detail below, the ends (in the Y direction) of each groove 146 are patterned without the need for separate masking to form cuts or breaks to separate adjacent metal lines. As a result, the ends of adjacent second metal lines can be extremely close. Furthermore, the ends of the second metal lines can be moved away from the ends of region 123 as needed. This leads to a reduction in irrelevant or redundant metal. The second metal lines can be substantially exactly the same length (or short) as needed.

[0067] Figures 11A and 11B are cross-sectional views of an integrated circuit 100 according to some embodiments. Figure 11C is a top view of an integrated circuit 100 according to some embodiments. The cross-sectional views of Figures 11A and 11B are taken along cutting lines 11A and 11B in Figure 11C, respectively.

[0068] With the patterned layer of photoresist layer 144 present, an etching process has been performed. The etching process etches dielectric layers 142 and 140 at locations exposed by trench 146. The etching process also etches patterned layer 112 and hard mask sublayer 110 at locations exposed by trench 146. The etching process is an anisotropic etching process that selectively etches in the down direction. In some embodiments, the etching process includes a single etching step that etches through dielectric layers 140 and 142, patterned layer 112, and hard mask sublayer 110. In some embodiments, the etching process includes multiple etching steps to etch through each layer separately. The etching process selectively etches exposed portions of the layers while substantially not etching spacer 125.

[0069] The final result of the etching process is the formation of trenches 137 in the hard mask sublayer 110 in the pattern of trenches 146 of the photoresist layer 144. Each trench 137 exposes the top surface of the hard mask sublayer 108. Each trench 137 corresponds to the pattern and location of an individual second metal line to be formed in the interlayer dielectric layer 102. As previously described with respect to Figures 10A to 10C, some regions 123 correspond to the locations of a plurality of second metal lines separated from each other in the Y direction. Figure 11C illustrates this situation as trenches 137 being separated by the patterned layer 112 and portions of the hard mask sublayer 110 not etched based on the pattern of the photoresist layer 144. Figure 11C also illustrates how the location of the end trenches 137 can be selected without using individual masks for cutting or breaking.

[0070] Figures 12A and 12B are cross-sectional views of an integrated circuit 100 according to some embodiments. Figure 12C is a top view of the integrated circuit 100. The cross-sectional views of Figures 12A and 12B are taken along cutting lines 12A and 12B of Figure 12C, respectively.

[0071] In Figures 12A to 12C, according to some embodiments, an etching process has been performed. The hard mask layer 104 has been fully patterned according to the trenches 136 and 137 described with respect to Figures 11A to 11C. In other words, trenches 136 and 137 have been fully extended through the hard mask sublayers 108 and 106. The etching process further forms trenches 148 in the interlayer dielectric layer 102 in the pattern of trenches 136 by extending trenches 136 into the interlayer dielectric layer 102. The etching process further forms trenches 149 in the interlayer dielectric layer 102 in the pattern of trenches 137 by extending trenches 137 into the interlayer dielectric layer 102. The same etching process forms trenches 148 and 149. In some embodiments, the etching process includes multiple etching steps to etch through the hard mask sublayers 108 and 106 and the interlayer dielectric layer 102. In some embodiments, a single etching process is used to etch through the hard mask sublayers 108 and 106 and the interlayer dielectric layer 102.

[0072] Trench 148 corresponds to the pattern of trench 134 extending into the interlayer dielectric layer 102. Trench 148 corresponds to the location of the first metal line. Trench 149 corresponds to the pattern of trench 146 extending into the interlayer dielectric layer 102. Trench 149 corresponds to the location of the second metal line.

[0073] In Figures 12A to 12C, spacer 125 has been removed. Any remaining portion of patterned layer 112 has been removed. This is achieved through one or more etching steps. As a result, in Figures 12A to 12C, only the fully patterned hard mask layer 104 remains above the interlayer dielectric layer 102.

[0074] Figures 13A and 13B are cross-sectional views of an integrated circuit 100 according to some embodiments. Figure 13C is a top view of the integrated circuit 100. The cross-sectional views of Figures 13A and 13B are taken along cutting lines 13A and 13B of Figure 13C, respectively.

[0075] In Figures 13A to 13C, the hard mask layer 104 has been completely removed. In some embodiments, the hard mask layer 104 is removed by performing one or more etching steps that selectively etch the material of the hard mask sublayer relative to the material of the interlayer dielectric layer 102. In some embodiments, the hard mask layer 104 is removed by a CMP process.

[0076] In Figures 13A to 13C, a first metal line 150 and a second metal line 151 have been formed in the interlayer dielectric layer 102. The first metal line 150 and the second metal line 151 are formed by depositing one or more metals in trenches 148 and 149. The one or more metals may include one or more liner layers lining the sidewalls and bottom of trenches 148 and 149. The one or more liner layers may include TiN, TaN, or other suitable materials. In some embodiments, the one or more metals include metals deposited on the liner layers and filling trenches 148 and 149. The metals may include W, Ti, Ta, Al, Cu, Au, or other suitable conductive materials. The metal layers may be deposited by PVD, ALD, or CVD. After depositing one or more metals, a CMP process is performed to remove excess metal material from the top surface of the interlayer dielectric layer 102. The result is the formation of the first metal line 150 and the second metal line 151.

[0077] The first metal wire 150 corresponds to a group of first metal wires or a group of first metal wires. The second metal wire 151 corresponds to a group of second metal wires or a group of second metal wires. The metal wires 151 and 150 are intersected laterally.

[0078] Figures 13A to 13C illustrate metal line 150 being wider than metal line 151 in the X direction. However, in some embodiments, metal lines 150 and 151 have the same width in the X direction. In some embodiments, metal lines 150 and 151 each have a width between 10 nm and 50 nm, but other dimensions may be used without departing from the scope of this disclosure. In some embodiments, metal lines 150 and 151 are spaced apart from each other at a uniform distance in the X direction. In some embodiments, the spacing between adjacent metal lines 150 and 151 in the X direction is between 5 nm and 50 nm, but other dimensions may be used without departing from the scope of this disclosure.

[0079] According to some embodiments, the top view of Figure 13C helps to illustrate some benefits of the process used to form the integrated circuit 100. As can be seen in Figure 13C, the metal lines have different lengths in the Y direction. The portion of the interlayer dielectric layer 102 below each track 122 or region 123 is not occupied by unrelated metal material because the lengths of the metal lines 150 / 151 in the Y direction are chosen to be any length. This is partly because the use of spacers 125 avoids lithography processes specifically designed to create breaks or cuts in the metal lines. Furthermore, due to the process described above, the metal lines 151 do not unduly widen in the X direction where there are no adjacent metal lines 150. This helps to reduce parasitic capacitance and avoid short circuits.

[0080] Figure 14 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 of Figure 14 includes an active circuit region 101, a first interlayer dielectric layer 102a located above the active circuit region 101, and a second interlayer dielectric layer 102b located above the first interlayer dielectric layer 102a.

[0081] According to some embodiments, a complex number of transistors 103 are formed in the active circuit region 101. The transistors 103 include PMOS transistors and NMOS transistors. In some embodiments, the transistors 103 are core logic circuits. In some embodiments, the transistors 103 constitute part of the SRAM array of the integrated circuit 100.

[0082] In some embodiments, the active circuit region 101 includes a semiconductor substrate. The channel region and source / drain region of the transistor 103 are bonded to the semiconductor substrate. The gate dielectric layer and gate metal of the transistor are formed adjacent to the channel region. Gate contacts corresponding to conductive vias or conductive plugs extend downward to contact the gate region. Source / drain contacts corresponding to conductive vias or conductive plugs extend downward to contact the source / drain regions. Various dielectric layers including gate spacers are formed above the transistor structure.

[0083] The interlayer dielectric layer 102a includes a first metal line 150a and a second metal line 151a formed according to the process described with respect to Figures 1 to 13C. Before forming the metal lines 150a and 151a, a conductive via 154a is formed in the interlayer dielectric layer 102a. According to the circuit layout, the metal lines 150a / 151a contact the conductive via 154a at selected contact areas. The conductive via 154a provides an electrical connection between the transistor 103 and the metal lines 150a / 151a.

[0084] The interlayer dielectric layer 102b includes a first metal line 150b and a second metal line 151b formed according to the process described with respect to Figures 1 to 13C. Before forming the metal lines 150b and 151b, a conductive via 154b is formed in the interlayer dielectric layer 102b. According to the circuit layout, the conductive via 154b contacts the metal lines 150a / 151a at selected contact locations. According to the circuit layout, the metal lines 150b / 151b contact the conductive via 154b at selected contact areas. The conductive via 154b provides an electrical connection between the metal lines 150b / 151b and the metal lines 150a / 151a. An additional interlayer dielectric layer and corresponding metal lines may be formed above the interlayer dielectric layer 102b.

[0085] Figure 15A is a top view of a layout 160 of metal lines in an integrated circuit according to some embodiments. Layout 160 corresponds to a stored metal line design. Layout 160 illustrates the planned positions of metal lines 150 and 151 and contact 162, corresponding to the positions where the metal lines will contact conductive vias.

[0086] Figure 15B is a top view of the integrated circuit 100, wherein the layout 160 is implemented by solidly forming metal lines 150 and 151 and contacts 162. The metal lines 150 and 151 are formed using the processes described with respect to Figures 1 through 13C. Figure 15B also shows the location of spacer 125, but in practice, spacer 125 no longer exists after the metal lines 150 and 151 are formed. The use of spacer 125 allows for the use of a larger contact window.

[0087] As can be seen in Figure 15B, layout 160 is accurately implemented in integrated circuit 100. Multiple end-to-end spacings exist. The metal lines have a uniform width and do not increase in the Y direction.

[0088] Figure 16 is a top view of an integrated circuit 100 according to some embodiments. Figure 16 illustrates two first metal lines 150 and two second metal lines 151. Figure 16 illustrates that both the first metal lines 150 and the second metal lines 151 have variable end-to-end distances, as indicated by arrows. The end-to-end distance may correspond to the distance between adjacent metal lines 150 / 151 in the Y direction, or the distance between the end of a metal line 150 / 151 and the edge of a cell or track. Without using the limiting spacer 125, the metal lines 150 may have finite end-to-end dimensions.

[0089] Figure 17 is a top view of an integrated circuit 100 according to some embodiments. Figure 17 illustrates two sets of three first metal lines 150 and one set of three second metal lines 151. Figure 17 illustrates that, using the process described above, both the first metal lines 150 and the second metal lines 151 have very small end-to-end spacing.

[0090] Figure 18 is a top view of an integrated circuit 100 according to some embodiments. Figure 18 illustrates three first metal lines 150 and three second metal lines 151. As can be seen in Figure 18, there is no widening of the metal lines 151 in the X direction when there are no adjacent metal lines 150. This is because the use of limiting spacers 125 effectively prevents this widening. In some embodiments, the metal lines shown in Figure 18 correspond to a portion of an SRAM cell, wherein one of the metal lines 150 is a high power supply voltage line supplying VDD, and one of the metal lines 151 is a low power supply voltage line supplying GND.

[0091] Figure 19 is a flowchart of a method 1900 for forming an integrated circuit according to some embodiments. Method 1900 may utilize the processes, components, and structures described with respect to Figures 1 through 18. At 1902, method 1900 includes forming a patterned layer over an interlayer dielectric layer of the integrated circuit. An example of an interlayer dielectric layer is interlayer dielectric layer 102 of Figure 1. An example of a patterned layer is patterned layer 112 of Figure 1. At 1904, method 1900 includes forming a plurality of first trenches in the patterned layer using a first lithography process. An example of a first trench is first trench 122 of Figure 3A. At 1906, method 1900 includes conformally depositing a dielectric layer on the patterned layer and in the trenches. An example of a dielectric layer is dielectric layer 124 of Figure 4. In method 1900, method 1900 includes forming a plurality of spacers from the dielectric layer by removing the dielectric layer from the top surface of the patterned layer, each spacer being lined with the sidewalls of a respective first trench. An example of a spacer is spacer 125 in Figure 5A. In method 1910, method 1900 includes forming a plurality of first metal lines in the interlayer dielectric, each first metal line being laterally self-aligned with one of the spacers. An example of a first metal line is metal line 150 in Figure 13A. In method 1912, method 1900 includes forming a plurality of second metal lines in the interlayer dielectric layer, the second metal lines being laterally staggered with the first metal lines and laterally self-aligned with the gaps between each of the second and adjacent spacers. An example of a second metal line is metal line 151 in Figure 13A.

[0092] Figure 20 is a flowchart of a method 2000 for forming an integrated circuit according to some embodiments. Method 2000 may utilize the processes, components, and structures described with respect to Figures 1 through 18. At 2002, method 2000 includes forming a plurality of first trenches in a patterned layer above an interlayer dielectric layer using a first lithography process. The interlayer dielectric layer is interlayer dielectric layer 102 of Figure 1. An example of a patterned layer is patterned layer 112 of Figure 1. An example of a first trench is first trench 122 of Figure 3A. At 2004, method 2000 includes forming a plurality of spacers, each spacer being lined with the sidewalls of a respective first trench and isolated from each other. An example of a spacer is spacer 125 of Figure 5A. At 2006, method 2000 includes forming a plurality of second trenches in a hard mask layer below the patterned layer using a second lithography process. An example of a hard masking layer is hard masking layer 110 in Figure 1. An example of a second trench is trench 136 in Figure 8A. At 2008, method 2000 includes forming a plurality of third trenches laterally alternating with the second trenches in the hard masking layer, the second and third trenches being laterally self-aligned with the spacers. An example of a third trench is trench 137 in Figure 11A.

[0093] The embodiments disclosed herein provide a method for forming metal lines in an interlayer dielectric layer of an integrated circuit. A process forms a set of metal lines as a first set of metal lines and a second set of metal lines laterally intersecting the first set of metal lines. A patterned layer is formed above the interlayer dielectric layer. A first lithography and etching process forms tracks in the patterned layer. A plurality of dielectric spacers are formed on the sidewalls of the tracks, exposing the bottom of the tracks. A second lithography and etching process forms the pattern of the first set of metal lines in the patterned layer based on the dielectric spacers. A third lithography and etching process forms the pattern of the second set of metal lines in the patterned layer based on the dielectric spacers. The patterns of the first and second sets of metal lines are then transferred to the interlayer dielectric layer as trenches in the interlayer dielectric layer by an etching process. The first and second sets of metal lines are then simultaneously formed by depositing metal material in the trenches.

[0094] The embodiments disclosed herein offer several benefits. First, no separate lithography and etching processes are required to create breaks in the metal lines. Second, in the patterned layer, the trenches or windows of both the first and second sets of metal lines are limited by dielectric spacers. This allows both sets of metal lines to have multiple end-to-end dimensions or small dimensions (e.g., very small end-to-end distances). Excess line length and redundant metal are also significantly reduced. In unrestricted locations, the lines do not exhibit lateral scaling characteristics. This further leads to better integrated circuit functionality and fewer scrapped wafers.

[0095] In some embodiments, a method includes forming a patterned layer over an interlayer dielectric layer of an integrated circuit and forming a plurality of first trenches in the patterned layer using a first photolithography process. The method includes conformally depositing a dielectric layer on the patterned layer and in the trenches, and forming a plurality of spacers from the dielectric layer by removing the dielectric layer from the top surface of the patterned layer, each spacer being lined with the sidewalls of a respective first trench. The method includes forming a plurality of first metal lines in the interlayer dielectric, each first metal line being laterally self-aligned with one of the spacers, and forming a plurality of second metal lines in the interlayer dielectric layer, the second metal lines being laterally interleaved with the first metal lines and laterally self-aligned with the gaps between each of the second and adjacent spacers. In some embodiments, the method includes forming a plurality of second trenches in a hard mask layer beneath the first trenches, using a second lithography process; and forming a plurality of third trenches laterally intersecting the first trenches in the hard mask layer based on the spacers, using a third lithography process. In some embodiments, each of the second trenches is located below a respective first region enclosed by one of the spacers. In some embodiments, each of the third trenches is located below a respective second region between adjacent spacers. In some embodiments, the second and third trenches partially extend into the hard mask layer. In some embodiments, the method includes removing the spacers; forming a plurality of fourth trenches in a pattern of the second trenches in the interlayer dielectric layer using an etching process; and forming a plurality of fifth trenches in a pattern of the third trenches in the interlayer dielectric layer using the etching process. In some embodiments, the method includes the steps of forming the first metal lines in the fourth trenches and the second metal lines in the fifth trenches by depositing a metal using a deposition process. In some embodiments, the method includes the step of performing a chemical mechanical planarization process after the deposition process. In some embodiments, the patterned layer is amorphous silicon. In some embodiments, the hard mask layer includes a first hard mask sublayer on the interlayer dielectric layer, a second hard mask sublayer on the first hard mask sublayer, and a third hard mask sublayer on the second hard mask sublayer. In some embodiments, the first hard mask sublayer and the third hard mask sublayer are tetraethoxysilane.

[0096] In some embodiments, a method includes forming a plurality of first trenches and a plurality of spacers in a patterned layer above an interlayer dielectric layer using a first lithography process, each spacer being lined with the sidewalls of a respective first trench and isolated from each other. The method includes forming a plurality of second trenches in a hard mask layer below the patterned layer using a second lithography process and forming a plurality of third trenches in the hard mask layer that alternate laterally with the second trenches, the second and third trenches being laterally self-aligned with the spacers. In some embodiments, the method includes forming a plurality of fourth trenches in the interlayer dielectric layer using a first etching process in a pattern of the second trenches; forming a plurality of fifth trenches in the interlayer dielectric layer using the first etching process in a pattern of the third trenches; forming a plurality of first metal lines in the fourth trenches; and forming a plurality of second metal lines in the fifth trenches by depositing metal using a deposition process. In some embodiments, the hard mask layer includes a first hard mask sublayer and a second hard mask sublayer located on the first hard mask sublayer. In some embodiments, forming the second trenches includes etching the second hard mask sublayer using a second etching process prior to the first etching process, without etching the first hard mask sublayer; and forming the third trenches includes etching the second hard mask sublayer using a third etching process between the second etching process and the first etching process, without etching the first hard mask sublayer. In some embodiments, forming the fourth and fifth trenches includes extending the second and third trenches through the first hard mask sublayer using a fourth etching process. In some embodiments, the first hard mask layer comprises tungsten-doped carbon, wherein the second hard mask layer comprises tetraethoxysilane.

[0097] In some embodiments, an integrated circuit includes a plurality of transistors, an interlayer dielectric layer above the transistors, and a plurality of first metal lines extending in a first lateral direction in the interlayer dielectric layer. The integrated circuit includes a plurality of second metal lines extending in the interlayer dielectric layer in the first lateral direction and alternating with the first metal lines in a second lateral direction transverse to the first lateral direction. The first metal lines have a plurality of different end-to-end dimensions. The second metal lines have a plurality of different end-to-end dimensions. In some embodiments, the first metal lines and the second metal lines are part of an SRAM cell. In some embodiments, the first metal lines and the second metal lines are separated by a uniformly spaced distance in the second lateral direction.

[0098] The foregoing summary of features of several embodiments enables those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. 102a: First interlayer dielectric layer / interlayer dielectric layer [Simplified Explanation of the Diagram]

[0099] Figures 1 to 13C are cross-sectional and top views of an integrated circuit according to some embodiments at various stages of processing. Figure 14 is a cross-sectional view of an integrated circuit according to some embodiments. Figure 15A is a layout of an integrated circuit according to some embodiments. Figure 15B is a top view of an integrated circuit according to some embodiments, wherein the layout of Figure 15A has been implemented. Figure 16 is a cross-sectional view of an integrated circuit according to some embodiments. Figure 17 is a cross-sectional view of an integrated circuit according to some embodiments. Figure 18 is a cross-sectional view of an integrated circuit according to some embodiments. Figure 19 is a flowchart of a method for forming an integrated circuit according to some embodiments. Figure 20 is a flowchart of a method for forming an integrated circuit according to some embodiments. The features disclosed herein are best understood when read in conjunction with the accompanying drawings, based on the following detailed description. It should be noted that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. [Biomaterial Storage]

[0101] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of forming an integrated circuit, comprising: forming a patterned layer over an interlayer dielectric layer of the integrated circuit; forming a plurality of first trenches in the patterned layer using a first photolithography process; conformally depositing a dielectric layer on the patterned layer and in the first trenches; forming a plurality of spacers from the dielectric layer by removing the dielectric layer from a top surface of the patterned layer, each of the spacers being lined with a plurality of sidewalls of each of the first trenches; forming a plurality of first metal lines in the interlayer dielectric layer, each of the first metal lines being laterally self-aligned with one of the spacers; and forming a plurality of second metal lines in the interlayer dielectric layer, the second metal lines being laterally intersecting the first metal lines and each being laterally self-aligned with a gap between adjacent spacers.

2. The method as claimed in claim 1, comprising: forming a plurality of second trenches in a hard mask layer below the first trenches in a hard mask layer between the patterned layer and the interlayer dielectric layer using a second lithography process; and forming a plurality of third trenches laterally intersecting the first trenches in the hard mask layer based on the spacers using a third lithography process.

3. The method as described in claim 1, wherein the patterned layer is amorphous silicon.

4. The method as described in claim 2, wherein the hard mask layer includes a first hard mask sublayer located on the interlayer dielectric layer, a second hard mask sublayer located on the first hard mask sublayer, and a third hard mask sublayer located on the second hard mask sublayer.

5. The method as described in claim 4, wherein the first hard mask sublayer and the third hard mask sublayer are tetraethoxysilane.

6. A method of forming an integrated circuit, comprising: forming a plurality of first trenches in a patterned layer above an interlayer dielectric layer using a first photolithography and etching process; forming a plurality of spacers, each of the spacers being lined with a plurality of sidewalls of each of the first trenches and isolated from each other; forming a plurality of second trenches in a hard mask layer below the patterned layer using a second photolithography process; and forming a plurality of third trenches in the hard mask layer that are laterally alternating with the second trenches, the second trenches and the third trenches being laterally self-aligned with the spacers.

7. The method as claimed in claim 6, comprising: forming a plurality of fourth trenches in an interlayer dielectric layer in a pattern of the second trenches using a first etching process; forming a plurality of fifth trenches in an interlayer dielectric layer in a pattern of the third trenches using the first etching process; forming a plurality of first metal lines in the fourth trenches; and forming a plurality of second metal lines in the fifth trenches by depositing metal using a deposition process.

8. The method as described in claim 7, wherein the hard mask layer includes a first hard mask sublayer and a second hard mask sublayer located on the first hard mask sublayer.

9. An integrated circuit comprising: a plurality of transistors; an interlayer dielectric layer above the transistors; a plurality of first metal lines extending in the interlayer dielectric layer in a first lateral direction; and a plurality of second metal lines extending in the interlayer dielectric layer in the first lateral direction and alternating with the first metal lines in a second lateral direction transverse to the first lateral direction, wherein the first metal lines have a plurality of different end-to-end dimensions, and wherein the second metal lines have a plurality of different end-to-end dimensions.

10. The integrated circuit as claimed in claim 9, wherein the first metal lines and the second metal lines are part of an SRAM cell.

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