Method for plasma etching vertical features in a silicon-based semiconductor layer of a substrate

TW202633290APending Publication Date: 2026-08-01TOKYO ELECTRON LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
TOKYO ELECTRON LTD
Filing Date
2025-10-02
Publication Date
2026-08-01

Smart Images

  • Figure TWG2TA001070679_002
    Figure TWG2TA001070679_002
Patent Text Reader

Abstract

A method for plasma etching in a plasma processing chamber, where the method includes providing a substrate having a silicon-based semiconductor layer disposed over an etch stop layer and a patterned masking layer disposed over the silicon-based semiconductor layer, the patterned masking layer exposing a surface of the silicon-based semiconductor layer; using the patterned masking layer as an etch mask, vertically etching the silicon-based semiconductor layer using a first plasma etch process to form a pattern of lines and expose portIONs of the underlying etch stop layer, one or more lines of the pattern of lines having a foot along its base, the first plasma etch process including generating a first plasma; and vertically etching in situ the pattern of lines using a second plasma etch process, the second plasma etch process including generating a second plasma from a first gas including chlorine and a second gas including a compound of hydrogen with Si, Br, I, P, or S, the second plasma being different from the first plasma, and exposing the pattern of lines to the second plasma to remove the foot from the pattern of lines.
Need to check novelty before this filing date? Find Prior Art