Manufacturing method of semiconductor structure

Abstract

A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. Stack structures are formed on the substrate. The stacked structures are separated from each other. First spacers are formed on sidewalls of the stack structures. Second spacers are formed on the first spacers. Spacer layers are formed on the second spacers. First dielectric layers are formed on the spacer layers. A portion of the second spacers and a portion of the first dielectric layers are removed to form first openings above the second spacers and to form second openings above the first dielectric layers. Cap layers are formed. The cap layers fill the first openings.

Description

Method for manufacturing semiconductor structure The present invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure capable of preventing short circuits. In semiconductor devices, landing pads are used as electrical connection components. However, the process of forming the landing pads often results in short circuits between conductive components. For example, the process of forming the landing pads often results in short circuits between two adjacent landing pads. The present invention provides a method for manufacturing a semiconductor structure, which can prevent short circuits from being formed between conductive components. The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate; forming a plurality of stacked structures on the substrate; separating the plurality of stacked structures from each other; forming a plurality of first spacers on the sidewalls of the plurality of stacked structures; forming a plurality of second spacers on the plurality of first spacers; forming a plurality of spacer layers on the plurality of second spacers; forming a plurality of first dielectric layers on the plurality of spacer layers; removing a portion of the plurality of second spacers and a portion of the plurality of first dielectric layers to form a plurality of first openings above the plurality of second spacers and a plurality of second openings above the plurality of first dielectric layers; forming a plurality of top cap layers; and filling the plurality of first openings with the plurality of top cap layers. Based on the above, in the semiconductor structure fabrication method of the present invention, multiple capping layers are filled into the multiple first openings, so that the multiple capping layers can at least protect the multiple second spacers. Consequently, during the subsequent landing pad formation process, the spacer structures on the sidewalls of the stacked structure can have a flatter surface profile and a more complete structure. Therefore, during the subsequent landing pad formation process, the spacer structures, due to their relatively flat surface profile, can effectively pattern the material layer used to form the landing pads, thereby forming separate landing pads and effectively preventing short circuits between adjacent landing pads. Furthermore, during the subsequent landing pad formation process, the spacer structures, due to their relatively complete structure, can effectively isolate other conductive components (e.g., between contacts and bit lines), thereby preventing short circuits between other conductive components (e.g., between contacts and bit lines). In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. 1A to 1I are cross-sectional views of the manufacturing process of a semiconductor structure according to some embodiments of the present invention. Referring to FIG. 1A , a substrate 100 is provided. Substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, an isolation structure 102 may be formed in substrate 100 . Isolation structure 102 may be a shallow trench isolation structure. The material of isolation structure 102 may be, for example, silicon oxide. Furthermore, although not shown in the figure, other desired components (e.g., doped regions and / or buried wordline structures) may be formed in substrate 100 . Next, a plurality of stacked structures 104 are formed on the substrate 100. The plurality of stacked structures 104 are separated from each other. The plurality of stacked structures 104 may include a plurality of bit line stacked structures. The stacked structures 104 (e.g., bit line stacked structures) may include a conductive layer 106, bit lines 108, and a hard mask layer 110. The conductive layer 106 is located on the substrate 100 and has a portion in contact with the substrate 100. The portion of the conductive layer 106 in contact with the substrate 100 may serve as a bit line contact window. The conductive layer 106 may be made of a conductive material such as doped polysilicon. The bit lines 108 are located on the conductive layer 106. The bit lines 108 may be made of a conductive material such as tungsten. The hard mask layer 110 is located on the bit lines 108. The hard mask layer 110 may be a single-layer structure or a multi-layer structure. The hard mask layer 110 may be made of silicon nitride, for example. The stack structure 104 (eg, a bit line stack structure) may further include a barrier layer 112. The barrier layer 112 is located between the conductive layer 106 and the bit line 108. The barrier layer 112 may be made of, for example, titanium, titanium nitride, or a combination thereof. The stacked structure 104 (e.g., a bit line stack structure) may further include a dielectric layer 114. The dielectric layer 114 is located on the substrate 100. The dielectric layer 114 may be located on the isolation structure 102. The dielectric layer 114 is located between the conductive layer 106 and the substrate 100. The dielectric layer 114 may be located between the conductive layer 106 and the isolation structure 102. The dielectric layer 114 may be a single-layer structure or a multi-layer structure. In this embodiment, the dielectric layer 114 may include a dielectric layer 122 and a dielectric layer 124. The dielectric layer 122 is located on the substrate 100. The material of the dielectric layer 122 is, for example, silicon oxide. The dielectric layer 124 is located on the dielectric layer 122. The material of the dielectric layer 124 is, for example, silicon nitride. Next, a plurality of spacers 128 are formed on the sidewalls of the plurality of stacked structures 104. The spacers 128 may be a single-layer structure or a multi-layer structure. In some embodiments, a slit SL may be formed in the spacers 128. The material of the spacers 128 is, for example, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. Then, a plurality of spacers 130 are formed on the plurality of spacers 128. The material of the spacers 128 is, for example, silicon oxide. Next, a spacer material layer 132 may be formed on the plurality of spacers 128, the plurality of spacers 130, the plurality of stacked structures 104, and the substrate 100. The material of the spacer material layer 132 is, for example, silicon nitride. Subsequently, a plurality of dielectric layers 134 may be formed on the spacer material layer 132. The dielectric layer 134 may be located between two adjacent stacked structures 104. The material of the dielectric layer 134 is, for example, silicon oxide. In some embodiments, a dielectric layer 136 may be formed on the spacer material layer 132 and the dielectric layer 134. The material of the dielectric layer 136 is, for example, silicon oxide. In some embodiments, a dielectric layer 138 may be formed on the dielectric layer 136. The material of the dielectric layer 138 is, for example, silicon nitride. Referring to FIG. 1B , an etch-back process is performed to remove a portion of the spacer material layer 132 to form a plurality of spacer layers 132 a and expose the plurality of spacers 130. Thus, a plurality of spacer layers 132 a can be formed on the plurality of spacers 130, and a plurality of dielectric layers 134 can be formed on the plurality of spacer layers 132 a. The cross-sectional shape of the spacer layer 132 a can be U-shaped. In the etch-back process, the dielectric layer 138, the dielectric layer 136, a portion of the plurality of spacers 128, a portion of the plurality of spacers 130, a portion of the plurality of stacked structures 104 (e.g., a portion of the hard mask layer 110), and a portion of the plurality of dielectric layers 134 can be removed simultaneously. The etch-back process is, for example, a dry etching process. 1C , portions of the plurality of spacers 130 and portions of the plurality of dielectric layers 134 are removed, thereby forming a plurality of openings OP1 above the plurality of spacers 130 and a plurality of openings OP2 above the plurality of dielectric layers 134. A depth D1 of the plurality of openings OP1 may be smaller than a depth D2 of the plurality of openings OP2. The removal of portions of the plurality of spacers 130 and portions of the plurality of dielectric layers 134 may be performed by, for example, wet etching. Referring to FIG. 1D , a cap material layer 140 is formed on the plurality of spacers 128, the plurality of spacers 130, the plurality of spacer layers 132a, the plurality of stacked structures 104, and the plurality of dielectric layers 134. The cap material layer 140 may be filled into the plurality of openings OP1. The cap material layer 140 may be conformally formed in the plurality of openings OP2. The material of the cap material layer 140 is, for example, silicon nitride. The cap material layer 140 may be formed by, for example, atomic layer deposition (ALD). Referring to FIG. 1E , the cap material layer 140 is etched back to form a plurality of cap layers 140 a. The plurality of cap layers 140 a fill the plurality of openings OP1. In this embodiment, the plurality of cap layers 140 a may cover the top surfaces S1 of the plurality of stacked structures 104. The etch-back process may be, for example, a dry etching process. 1F , the plurality of dielectric layers 134 may be removed by, for example, wet etching. Referring to FIG. 1G , a portion of the plurality of spacer layers 132 a may be removed to form a plurality of spacers 132 b, thereby exposing the plurality of openings OP2 to the substrate 100. In some embodiments, during the process of removing a portion of the plurality of spacer layers 132 a, a portion of the cap layer 140 a may be removed. The method for removing a portion of the plurality of spacer layers 132 a may be, for example, dry etching. Subsequently, a portion of the substrate 100 may be removed, thereby extending the plurality of openings OP2 into the substrate 100. The method for removing a portion of the substrate 100 may be, for example, dry etching. Referring to FIG. 1H , a plurality of contact windows 142 may be formed in the plurality of openings OP2. The material of the contact windows 142 may be, for example, a conductive material such as doped polysilicon. In some embodiments, a method for forming the contact windows 142 may include the following steps. First, a contact window material layer (not shown) is formed to fill the openings OP2. Next, a portion of the contact window material layer is removed to form the plurality of contact windows 142. The method for removing the portion of the contact window material layer may be, for example, an etch-back method (e.g., a dry etching method). Referring to FIG. 1I , a plurality of landing pads 144 may be formed on a plurality of contact windows 142. An opening OP3 may be defined on one side of the landing pad 144. The landing pad 144 may have a single-layer structure or a multi-layer structure. In this embodiment, the landing pad 144 may include a conductive layer 146 and a barrier layer 148. The conductive layer 146 is located on the contact windows 142. The barrier layer 148 is located between the conductive layer 146 and the contact windows 142. The conductive layer 146 may be made of a conductive material such as tungsten. The barrier layer 148 may be made of titanium, titanium nitride, or a combination thereof. In some embodiments, the method for forming the conductive layer 146, the barrier layer 148, and the opening OP3 may include the following steps. First, a material layer (not shown) for forming the barrier layer 148 and a material layer (not shown) for forming the conductive layer 146 may be sequentially formed. Next, the material layer for forming the conductive layer 146 and the material layer for forming the barrier layer 148 are patterned to form the conductive layer 146, the barrier layer 148, and the opening OP3. In the patterning process, the material layer for forming the conductive layer 146 and the material layer for forming the barrier layer 148 may be patterned by a photolithography process and an etching process (e.g., a dry etching process). In subsequent manufacturing processes, other required components (eg, capacitors, etc.) may be formed to complete the fabrication of semiconductor devices (eg, memory devices), and description thereof is omitted herein. Based on the above embodiment, it can be seen that in the method for manufacturing the semiconductor structure 10, the plurality of cap layers 140a fill the plurality of openings OP1. Therefore, the plurality of cap layers 140a can at least protect the plurality of spacers 130. As a result, in the subsequent process of forming the landing pads 144, the spacer structures (e.g., spacers 128, 130, and 132b) located on the sidewalls of the stacked structure 104 can have a relatively flat surface profile and a relatively complete structure. Therefore, in the subsequent process of forming the landing pads 144, since the spacer structures (e.g., spacers 128, 130, and 132b) have a relatively flat surface profile, the material layer used to form the landing pads 144 can be effectively patterned to form separate landing pads 144, thereby effectively preventing short circuits between adjacent landing pads 144. Furthermore, in the subsequent process of forming the landing pad 144, since the spacer structure (e.g., spacers 128, 130, and 132b) can have a relatively complete structure, it can effectively isolate other conductive components (e.g., between the contact window 142 and the bit line 108), thereby preventing the formation of a short circuit between other conductive components (e.g., between the contact window 142 and the bit line 108). 2A to 2D are cross-sectional views of the manufacturing process of a semiconductor structure according to some embodiments of the present invention. 2A , which provides a structure similar to that shown in FIG1D . Furthermore, the structure of FIG1D and its manufacturing method have been described in detail in the above embodiment and will not be further described here. Referring to FIG. 2B , an oxidation process is performed on the cap material layer 140 to form an oxide layer 140 b and a plurality of cap layers 140 c. In some embodiments, a portion of the spacer layer 132 a is oxidized to form a portion of the oxide layer 140 b. The plurality of cap layers 140 c fill the plurality of openings OP1. In this embodiment, the plurality of cap layers 140 c may not cover the top surfaces S1 of the plurality of stacked structures 104. 2C , the oxide layer 140 b may be removed. During the process of removing the oxide layer 140 b , the plurality of dielectric layers 134 may be removed simultaneously. The oxide layer 140 b and the plurality of dielectric layers 134 may be removed by, for example, wet etching. 2D , the same steps as those in FIG 1G to FIG 1I may be performed to form the semiconductor structure 20 of FIG 2D . In addition, in the semiconductor structure 20 of FIG 2D and the semiconductor structure 10 of FIG 1I , the same or similar components are denoted by the same reference numerals and their descriptions are omitted. In subsequent manufacturing processes, other required components (eg, capacitors, etc.) may be formed to complete the fabrication of semiconductor devices (eg, memory devices), and description thereof is omitted herein. In summary, in the semiconductor structure fabrication method of the above-described embodiment, the cap layer can be used to protect the spacer. Thus, in the subsequent landing pad formation process, the spacer structure located on the sidewall of the stacked structure can have a flatter surface profile and a more complete structure. Therefore, in the subsequent landing pad formation process, short circuits between adjacent landing pads and short circuits between other conductive components (e.g., between contact windows and bit lines) can be effectively prevented. Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications. 10, 20: Semiconductor structure 100: Substrate 102: Isolation structure 104: Stacked structure 106, 146: Conductive layer 108: Bit line 110: Hard mask layer 112, 148: Barrier layer 114, 122, 124, 134, 136, 138: Dielectric layer 128, 130, 132b: Spacer 132: Spacer material layer 132a: Spacer layer 140: Cap material layer 140a, 140c: Cap layer 140b: Oxide layer 142: Contact window 144: Landing pad D1, D2: Depth OP1, OP2, OP3: Opening S1: Top surface SL: Slit 1A to 1I are cross-sectional views of a semiconductor structure fabrication process according to some embodiments of the present invention. FIG2A to 2D are cross-sectional views of a semiconductor structure fabrication process according to some embodiments of the present invention. 10: Semiconductor structure 100: Base 102: Isolation Structure 104: Stacked structure 106,146: Conductive layer 108: Bit line 110: Hard mask layer 112,148: Barrier layer 114,122,124: Dielectric layer 128,130,132b: interstitial wall 140a: Top cover layer 142: Contact window 144: Landing Pad OP1, OP2, OP3: Opening S1: Top surface SL: Slit

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked structures on the substrate, wherein the plurality of stacked structures are separated from each other; forming a plurality of first spacers on the sidewalls of the plurality of stacked structures; forming a plurality of second spacers on the plurality of first spacers; forming a plurality of spacer layers on the plurality of second spacers; and forming a plurality of first dielectric layers on the plurality of spacer layers; removing a portion of the second spacers and a portion of the first dielectric layers to form a plurality of first openings above the second spacers and a plurality of second openings above the first dielectric layers; and forming a plurality of top cover layers, wherein the plurality of the top cover layers fill the plurality of the first openings.

2. The method for manufacturing a semiconductor structure as described in claim 1, wherein a depth of the plurality of first openings is smaller than a depth of the plurality of second openings.

3. In the method for manufacturing a semiconductor structure according to claim 1 , a method for removing a portion of the plurality of second spacers and a portion of the plurality of first dielectric layers comprises a wet etching method.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein a method for forming the plurality of spacer layers comprises: forming a spacer material layer on the plurality of first spacers, the plurality of second spacers, the plurality of stacked structures and the substrate; forming a plurality of first dielectric layers on the spacer material layer; and performing an etch-back process to remove a portion of the spacer material layer to form a plurality of the spacer layers and expose a plurality of the second spacers.

5. A method for manufacturing a semiconductor structure as described in claim 4, wherein in the back etching process, a portion of multiple first spacers, a portion of multiple second spacers, a portion of multiple stacked structures and a portion of multiple first dielectric layers are removed simultaneously.

6. The method for manufacturing a semiconductor structure as described in claim 4, wherein the etch-back process includes a dry etching process.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for forming the plurality of cap layers comprises: A top cover material layer is formed on the plurality of first spacers, the plurality of second spacers, the plurality of spacer layers, the plurality of stacked structures and the plurality of first dielectric layers, wherein the top cover material layer is filled into the plurality of first openings; and a back etching process is performed on the top cover material layer to form the plurality of top cover layers.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein the plurality of cap layers cover top surfaces of the plurality of stacked structures.

9. The method for manufacturing a semiconductor structure as described in claim 7, wherein the etch-back process includes a dry etching process.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for forming the plurality of cap layers comprises: A top cover material layer is formed on the plurality of first spacers, the plurality of second spacers, the plurality of spacer layers, the plurality of stacked structures and the plurality of first dielectric layers, wherein the top cover material layer is filled into the plurality of first openings; and an oxidation process is performed on the top cover material layer to form an oxide layer and the plurality of top cover layers.

11. The method for manufacturing a semiconductor structure according to claim 10 further comprises: The oxide layer is removed.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein in the process of removing the oxide layer, a plurality of the first dielectric layers are removed simultaneously.

13. The method for manufacturing a semiconductor structure as described in claim 12, wherein a method for removing the oxide layer and the plurality of first dielectric layers comprises a wet etching method.

14. The method for manufacturing a semiconductor structure according to claim 10, wherein the plurality of cap layers do not cover top surfaces of the plurality of stacked structures.

15. The method for manufacturing a semiconductor structure according to claim 1 further comprises: removing a plurality of the first dielectric layers; removing a portion of the plurality of spacer layers to form a plurality of third spacers, and making the plurality of second openings expose the substrate; and forming a plurality of contact windows in the plurality of second openings.

16. The method for manufacturing a semiconductor structure according to claim 15 further comprises: Before forming the plurality of contact windows, a portion of the substrate is removed so that the plurality of second openings extend into the substrate.

17. The method for manufacturing a semiconductor structure according to claim 15, wherein a method of removing a portion of the plurality of spacer layers comprises a dry etching method.

18. The method for manufacturing a semiconductor structure according to claim 1, wherein the plurality of stack structures comprises a plurality of bit line stack structures.

19. The method for manufacturing a semiconductor structure according to claim 18, wherein the bit line stack structure comprises: a conductive layer, located on the substrate and having a portion in contact with the substrate; A bit line located on the conductive layer; and a hard mask layer located on the bit line.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein the bit line stack structure further comprises: The second dielectric layer is located between the conductive layer and the substrate.

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