Semiconductor device and method for forming the same

Abstract

The present disclosure provides a semiconductor device and a method for forming the same. A first die including a first interconnection structure formed on a first region of a substrate is provided. A second die including a second interconnection structure formed on a second region, different from the first region, of the substrate is provided, wherein the first interconnection structure and the second interconnection structure are covered by a first dielectric layer formed on the substrate. A first test structure electrically connecting to the first interconnection structure and a second test structure electrically connecting to the second interconnection structure are formed on the first interconnection structure and the second interconnection structure, respectively. The first test structure includes a first test pad and a first connection pad electrically connected to the first test pad. The second test structure includes a second test pad and a second connection pad electrically connected to the second test pad.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same. Prior Technology

[0002] System-on-a-chip (SoC) applications require high-speed and low-power operation. To meet these requirements, on-chip transistors are miniaturized and operate at lower supply voltages. This results in increased current density. The rapid switching of transistors and the high current density generate large voltage drops. These voltage drops act as power supply noise, affecting circuit operation. Furthermore, lower supply voltages relatively reduce the design margin for voltage fluctuations. Therefore, power supply noise is one of the problems currently faced in low-voltage integrated circuits.

[0003] In traditional flip-chip packaging, multilayer ceramic capacitors (MLCCs) are placed near conductive components to act as temporary charging and discharging "dams," regulating current in the circuit and preventing electromagnetic interference between components. Since the thickness of a single dielectric layer and the number of stacked layers are related to the capacitance value, techniques for thinning single layers and stacking more layers are important.

[0004] However, the performance of MLCCs is limited by parasitic elements, such as equivalent series inductance (ESL) and equivalent series resistance (ESR), and is also affected by factors such as high temperature, frequency, or DC bias.

[0005] As electronic devices continue to shrink in size and users demand higher performance from them, those skilled in the art expect to place small capacitors between conductive components, such as silicon capacitors (Si-Cap) made with silicon as the insulator and manufactured using semiconductor technology. This would not only reduce the impact of reduced power / ground balls, but also provide current to high-speed application processors quickly and stably. Summary of the Invention

[0006] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a first die, wherein the first die includes a first interconnect structure formed on a first region of a substrate; providing a second die, wherein the second die includes a second interconnect structure formed on a second region of the substrate, the second region being different from the first region, and the second interconnect structure and the first interconnect structure being covered by a first dielectric layer formed on the substrate; and forming a first test structure electrically connected to the first interconnect structure and a second test structure electrically connected to the second interconnect structure on the first interconnect structure and the second interconnect structure, respectively, wherein the first test structure includes a first test pad and a first connection pad electrically connected to the first test pad, and the second test structure includes a second test pad and a second connection pad electrically connected to the second test pad.

[0007] An embodiment of the present invention provides a semiconductor device including a first die, a second die, a first dielectric layer, and a first connection pad. The first die includes a first interconnect structure disposed on a first region of a substrate. The second die includes a second interconnect structure disposed on a second region of the substrate, wherein the second region is different from the first region. The first dielectric layer is on the substrate and covers the first interconnect structure and the second interconnect structure. The first connection pad is on the first interconnect structure and electrically connected to the first interconnect structure, wherein the first dielectric layer includes a first opening with its bottom surface defined by the first connection pad and a second opening with its bottom surface defined by the first dielectric layer and adjacent to the first opening above the first interconnect structure, wherein the depth of the first opening is less than the depth of the second opening. Simple Explanation of the Diagram

[0008] Figure 1A and Figures 2 to 5 are schematic cross-sectional views of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 1B is a top view of one embodiment of the first test structure of Figure 1A. Figure 6A is a top view schematic diagram of the first conductive via in Figure 5 according to an embodiment. Figure 6B is a top view schematic diagram of the second conductive via in Figure 5 according to one embodiment. Implementation

[0009] First, referring to FIG1A, dies D1, D2, and D3 are provided. Dies D1, D2, and D3 respectively include interconnect structures ICS1, ICS2, and ICS3 formed on regions R1, R2, and R3 of substrate 100. Regions R1, R2, and R3 are different from each other. In some embodiments, dies D1, D2, and D3 may be formed in regions R1, R2, and R3 of a wafer, respectively. That is, substrate 100 may be the substrate of a whole wafer. In some embodiments, dies D1, D2, and D3 may be formed in regions R1, R2, and R3 of substrate 100 through front-end-of-line (FEOL) and / or back-end-of-line (BEOL) processes, respectively.

[0010] The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate and a component layer formed on the semiconductor substrate or SOI substrate.

[0011] The element layer may be a film layer in which active elements are formed. In some embodiments, the element layer may include active elements such as N-type metal-oxide semiconductor (NMOS), P-type metal-oxide semiconductor (PMOS), or complementary metal-oxide semiconductor (CMOS).

[0012] The interconnect structures ICS1, ICS2, and ICS3 may include multiple conductive layers and at least one conductive via connecting these conductive layers. The conductive layers and / or conductive vias may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0013] The interconnect structures ICS1, ICS2, and ICS3 are covered by a first dielectric layer 110 formed on the substrate 100. The first dielectric layer 110 may include any suitable dielectric material. For example, the first dielectric layer 110 may include oxides such as tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), oxides formed by high-density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), oxides formed by spin coating such as spin-on glass (SOG) and spin-on dielectric (SOD), or oxides formed by a high aspect ratio process (HARP).

[0014] In some embodiments, the grains D1, D2, and D3 may include passive elements SC1, SC2, and SC3 formed in the first dielectric layer 110 and respectively located on regions R1, R2, and R3. In some embodiments, the passive elements SC1, SC2, and SC3 may include resistive elements. For example, the resistive element may be a silicon capacitor (Si-Cap). The passive elements SC1, SC2, and SC3 may be electrically connected to the interconnect structures ICS1, ICS2, and ICS3, respectively.

[0015] Then, test structures TS1, TS2, and TS3, electrically connected to interconnect structure ICS1, ICS2, and ICS3 respectively, are formed on interconnect structures ICS1, ICS2, and ICS3. Test structure TS1 includes a test pad TP1 and a connecting pad SP1 electrically connected to the test pad TP1. Test structure TS2 includes a test pad TP2 and a connecting pad SP2 electrically connected to the test pad TP2. Test structure TS3 includes a test pad TP3 and a connecting pad SP3 electrically connected to the test pad TP3. Test pads TP1, TP2, and TP3 may include any suitable conductive material. For example, test pads TP1, TP2, and TP3 may include a metallic material such as aluminum (Al). Connecting pads SP1, SP2, and SP3 may include any suitable conductive material such as a metallic material such as aluminum (Al). In some embodiments, test pads TP1, TP2, and TP3 and connecting pads SP1, SP2, and SP3 may be formed simultaneously in the same process.

[0016] As shown in Figures 1A and 1B, the test structures TS1, TS2, and TS3 may include wires CL1, CL2, and CL3 that electrically connect the test pads TP1, TP2, and TP3 and the connecting pads SP1, SP2, and SP3. Wires CL1, CL2, and CL3 may include one end connected to the test pads TP1, TP2, and TP3 and the other end connected to the connecting pads SP1, SP2, and SP3. Wires CL1, CL2, and CL3 may include any suitable conductive material, such as aluminum (Al) or other metallic materials. In some embodiments, the test pads TP1, TP2, and TP3, the wires CL1, CL2, and CL3, and the connecting pads SP1, SP2, and SP3 may be formed simultaneously in the same process.

[0017] The grains D1, D2, and D3 may each include conductive vias via1, via2, and via3 formed in the first dielectric layer 110 and electrically connecting the connecting pads SP1, SP2, and SP3 to the interconnect structures ICS1, ICS2, and ICS3. In some embodiments, the conductive vias via1, via2, and via3 may be disposed below the connecting pads SP1, SP2, and SP3. The conductive vias via1, via2, and via3 may include conductive materials such as metals or metal alloys, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0018] The first dielectric layer 110 covers the test structures TS1, TS2, and TS3 and includes multiple openings that expose test pads TP1, TP2, and TP3 and connection pads SP1, SP2, and SP3, respectively. The wires CL1, CL2, and CL3 are covered by the first dielectric layer 110 and are not exposed. Subsequent test probes TPB will probe the test pads TP1, TP2, and TP3 through these openings to test the dies D1, D2, and D3.

[0019] Next, referring to Figure 2, the test probe TPB probes the test pads TP1, TP2, and TP3 to test the dies D1, D2, and D3. When a die is determined to be non-compliant with a predetermined standard (also known as a bad die), the test probe TPB probes the corresponding connection pad through the corresponding opening. For example, when die D3 is determined to be a bad die, the test probe TPB probes the corresponding connection pad SP3. In this way, since the test pads TP1', TP2', and TP3' probed by the test probe TPB and the connection pad SP3' have etch selectivity relative to the connection pads SP1 and SP2 that have not been probed, the connection pads (e.g., connection pad SP3') of the bad die (e.g., die D3) can be removed by methods such as wet etching, thereby preventing the signal from connecting to the bad die and causing the semiconductor device containing the bad die to fail. In this embodiment, a die not conforming to a predetermined standard means that its component performance (e.g., electrical performance) does not meet the preset specifications, but this is not a limitation.

[0020] Then, referring to Figures 2 and 3, the test pads TP1', TP2', TP3' and the connecting pad SP3' that were probed by the test probe TPB are removed. In some embodiments, the test pads TP1', TP2', TP3' and the connecting pad SP3' that were probed by the test probe TPB are removed by a wet etching process. In some embodiments, hydrofluoric acid (DHF) can be used as an etchant for example to perform the wet etching process to remove the test pads TP1', TP2', TP3' and the connecting pad SP3' that were probed by the test probe TPB. In this embodiment, even though the test pads TP1', TP2', TP3' and the connecting pads SP1, SP2, SP3' are made of the same material, the structure of the test pads TP1', TP2', TP3' and the connecting pads SP3' that have been probed by the test probe TPB is damaged. Therefore, the connecting pads SP1 and SP2 that have not been probed by the test probe TPB have good selectivity in this wet etching process. For example, under the same conditions, the removal rate of the test pads TP1', TP2', TP3' and the connecting pads SP3' will be significantly greater than the removal rate of the connecting pads SP1 and SP2.

[0021] As shown in Figures 2 and 3, after removing the test pads TP1', TP2', TP3' and the connecting pad SP3' that were probed by the test probe TPB, the multiple openings of the first dielectric layer 110 that previously exposed the test pads TP1, TP2, TP3 and the connecting pads SP1, SP2, SP3 are formed into a first opening exposing the connecting pads SP1 and SP2, and a second opening defined by the first dielectric layer 110 on the bottom surface (corresponding to the openings where the test pads TP1', TP2', TP3' and the connecting pad SP3' were removed), wherein the depth of the first opening is less than the depth of each of the second openings. In some embodiments, after removing the test pads TP1', TP2', TP3' and the connecting pad SP3' that were probed by the test probe TPB, the conductive via 1 and the conductive via 2 are covered by the connecting pads SP1 and SP2, respectively, while the conductive via 3 is exposed by one of the second openings (corresponding to the opening where the connecting pad SP3' was removed).

[0022] Next, referring to FIG4, a second dielectric layer 120 is formed on the first dielectric layer 110, wherein the second dielectric layer 120 fills the aforementioned first and second openings and covers the connection pads SP1 and SP2. The second dielectric layer 120 may include any suitable dielectric material, such as polyimide (PI). Then, through a photolithography and etching process, openings exposing the connection pads SP1 and SP2 and openings corresponding to the previously removed connection pad SP3' and exposing the first dielectric layer 110 are formed in the second dielectric layer 120.

[0023] Then, referring to FIG5, a redistribution layer 130 is formed on the second dielectric layer 120, wherein the redistribution layer 130 may include vias 132, 134, and 136 formed in the second dielectric layer 120 and a conductive layer 138 on and connecting the vias 132, 134, and 136. The vias 132 and 134 are formed in openings exposing the connecting pads SP1 and SP2, respectively, and are in contact with the connecting pads SP1 and SP2. The via 136 is formed in an opening corresponding to the previously removed connecting pad SP3' and exposing the first dielectric layer 110, and is in contact with the first dielectric layer 110. The vias 132, 134, and 136 and the conductive layer 138 may include any suitable conductive material, such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0024] In this embodiment, vias 132 and 134 are formed above interconnect structures ICS1 and ICS2, respectively, and can be electrically connected to interconnect structures ICS1 and ICS2 through first connecting pads SP1 and SP2. Via 136 is formed above interconnect structure ICS3 and is electrically isolated from interconnect structure ICS3. In this way, the passive components SC1 and SC2 of dies D1 and D2 can be connected to each other through vias 132 and 134, and the capacitance of the semiconductor device can be adjusted by means of series and / or parallel connections. Since via 136 is electrically isolated from interconnect structure ICS3, signal connection to die D3 (determined to be a bad die in the above tests) can be avoided, preventing the semiconductor device containing the bad die from malfunctioning. When die D3 is determined to be a bad die, the connection pad SP3 electrically connected to the interconnect structure ICS3 can be probed by the aforementioned test probe TPB and removed by a wet etching process. Therefore, it is not necessary to adjust the photomask and / or mask (e.g., different combinations of photomasks and / or masks) to prevent via 136 from being formed in the second dielectric layer 120 (e.g., no via hole formed in the second dielectric layer 120), thereby preventing signal connection to die D3. In this way, this disclosure can form vias 132, 134, and 136 by using the same photomask and / or mask process without adjusting the positions of good dies (e.g., dies D1, D2) and bad dies (e.g., die D3), thereby helping to improve the stability of the semiconductor device and saving the cost of photomasks and / or masks.

[0025] In some embodiments, as shown in Figures 5 and 6A, one end of the wires CL1 and CL2 contacts the second dielectric layer 120 after the test pads TP1 and TP2 are removed, while the other end of the wires CL1 and CL2 remains in contact with the connection pads SP1 and SP2. In some embodiments, as shown in Figures 5 and 6B, one end of the wire CL3 contacts the second dielectric layer 120 after the test pads TP1 and TP2 are removed, while the other end of the wire CL3 also contacts the second dielectric layer 120 after the test pads TP3 and SP3' are removed.

[0026] In some embodiments, as shown in FIG5, FIG6A, and FIG6B, vias 132 and 134 of the redistribution layer 130 penetrate the second dielectric layer 120 to contact the corresponding connection pads SP1 and SP2, while via 136 of the redistribution layer 130 penetrates the second dielectric layer 120 to contact the first dielectric layer 110 but does not contact the underlying conductive via 3. In some embodiments, the positions of via 136 and conductive via 3 are offset from each other in the top view and do not overlap.

[0027] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described by way of example with reference to FIG5, FIG6A and FIG6B. The semiconductor device of this embodiment can be formed by the method described above, but is not limited thereto.

[0028] Referring to Figures 5, 6A, and 6B, a semiconductor device may include a first die (e.g., die D1 or D2), a second die (e.g., die D3), a first dielectric layer 110, and a first interconnect pad (e.g., interconnect pad SP1 or SP2). The first die includes a first interconnect structure (e.g., interconnect structure ICS1 or ICS2) disposed on a first region (e.g., region R1 or R2) of the substrate 100. The second die includes a second interconnect structure (e.g., interconnect structure ICS3) disposed on a second region (e.g., region R3) of the substrate 100, wherein the second region is different from the first region. The first dielectric layer 110 is on the substrate 100 and covers the first interconnect structure (e.g., interconnect structure ICS1 or ICS2) and the second interconnect structure (e.g., interconnect structure ICS3). The first interconnect pad (e.g., interconnect pad SP1 or SP2) is on the first interconnect structure (e.g., interconnect structure ICS1 or ICS2) and electrically connected to the first interconnect structure. The first dielectric layer 110 includes a first opening on the bottom surface of the first interconnect structure (e.g., interconnect structure ICS1 or ICS2) and a second opening on the bottom surface of the first dielectric layer 110 and adjacent to the first opening, wherein the depth of the first opening is less than the depth of the second opening.

[0029] In some embodiments, the semiconductor device may further include a first conductor (e.g., conductor CL1 or CL2) disposed in the first dielectric layer 110 and connected to a first connection pad (e.g., connection pad SP1 or SP2), wherein the first conductor may be configured between the first opening and the second opening.

[0030] In some embodiments, the semiconductor device may further include a second dielectric layer 120 disposed on the first dielectric layer 110 and filling the first opening and the second opening, wherein the first conductor (e.g. conductor CL1 or CL2) may include one end in contact with the second dielectric layer 120 and the other end in contact with the first connection pad (e.g. connection pad SP1 or SP2).

[0031] In some embodiments, the semiconductor device may further include a redistribution layer 130 disposed on the second dielectric layer 120. The redistribution layer 130 may include a first via (e.g., via 132 or 134) penetrating the second dielectric layer 120 through the first opening and contacting a first connection pad (e.g., connection pad SP1 or SP2).

[0032] In some embodiments, the first dielectric layer 110 includes a third opening and a fourth opening, the bottom surfaces of which are defined by the first dielectric layer 110 and are adjacent to each other, above the second interconnect structure (e.g., interconnect structure ICS3). The depth of the third opening is approximately equal to the depth of the fourth opening, and the second dielectric layer 120 fills the third and fourth openings. The semiconductor device may further include a second conductor (e.g., conductor CL3) disposed in the first dielectric layer 110 and positioned between the third and fourth openings, and the second conductor includes one end and the other end respectively contacting the second dielectric layer 120.

[0033] In some embodiments, the semiconductor device may further include a first conductive via and a second conductive via. The first conductive via (e.g., via1 or via2) may be disposed in a first dielectric layer 110 below a first connecting pad (e.g., connecting pad SP1 or SP2) and electrically connected to a first interconnect structure (e.g., interconnect structure ICS1 or ICS2) and the first connecting pad. The second conductive via (e.g., via3) may be disposed in the first dielectric layer 110 below a fourth opening and electrically connected to a second interconnect structure (e.g., interconnect structure ICS3). As shown in FIG6B, the second conductive via (e.g., via3) may be covered by a second dielectric layer 120 filling the fourth opening.

[0034] In some embodiments, the redistribution layer 130 may include a second via (e.g., via 136) that penetrates the second dielectric layer 120 through the fourth opening and contacts the first dielectric layer 110, wherein the second via does not contact the second conductive via (e.g., via 3).

[0035] In summary, in the semiconductor device and its formation method described in the above embodiments, the test structure is designed to include test pads and connection pads. In the step of testing the die by probing the test pads with a test probe, the die that is determined to be non-compliant with the predetermined standard (hereinafter referred to as a bad die) will have its connection pads probed again with a test probe. Since the test pads and connection pads probed by the test probe have etching selectivity relative to the connection pads that have not been probed in, for example, a wet etching process, the connection pads of the bad die can be removed by means such as wet etching, thereby preventing the signal from being connected to the bad die and causing the semiconductor device containing the bad die to fail.

[0036] 100: Base 110: First dielectric layer 120: Second dielectric layer 130: Rewire Layer 132, 134, 136: Through holes 138: Conductive layer CL1, CL2, CL3: Wires D1, D2, D3: Grains ICS1, ICS2, ICS3: Internal Wiring Structure R1, R2, R3: Areas SC1, SC2, SC3: Passive components SP1, SP2, SP3, SP3': Connecting pads TP1, TP2, TP3, TP1', TP2', TP3': Test pads TPB: Test Probe TS1, TS2, TS3: Test Structure via1, via2, via3: conductive vias

Claims

1. A method of forming a semiconductor device, comprising: A first grain is provided, wherein the first grain includes a first interconnect structure formed on a first region of a substrate; A second die is provided, wherein the second die includes a second interconnect structure formed on a second region of the substrate, the second region being different from the first region, and the second interconnect structure and the first interconnect structure are covered by a first dielectric layer formed on the substrate; a first test structure electrically connected to the first interconnect structure and a second test structure electrically connected to the second interconnect structure are formed on the first interconnect structure and the second interconnect structure, respectively, wherein the first test structure includes a first test pad and a first connection pad electrically connected to the first test pad, and the second test structure includes a second test pad and a second connection pad electrically connected to the second test pad; a test probe is used to probe the first test pad and the second test pad to test the first die and the second die; and when the second die is determined to be non-compliant with a predetermined standard after testing, the test probe is used to probe the second connection pad.

2. The method as described in claim 1, further comprising: Remove the first test pad, the second test pad, and the second connecting pad that have been probed by the test probe.

3. The method as described in claim 2, wherein the first test pad, the second test pad, and the second connection pad that were probed by the test probe are removed by a wet etching process.

4. The method of claim 3, wherein the first test pad, the second test pad, and the second connection pad that have been probed by the test probe have etch selectivity in the wet etching process relative to the first connection pad that has not been probed by the test probe.

5. The method as described in claim 2, further comprising: A second dielectric layer covering the first connection pad is formed on the first dielectric layer; A redistribution layer is formed on the second dielectric layer, wherein the redistribution layer includes a first via and a second via formed in the second dielectric layer, the first via contacting the first connection pad and the second via contacting the first dielectric layer.

6. The method of claim 5, wherein the first through-hole is formed above the first interconnect structure and electrically connected to the first interconnect structure via the first connecting pad, and the second through-hole is formed above the second interconnect structure and electrically isolated from the second interconnect structure.

7. The method of claim 5, wherein the first test structure includes a first wire connected at one end to the first test pad and at the other end to the first connection pad, wherein the first end of the first wire contacts the second dielectric layer after the first test pad is removed.

8. The method of claim 5, wherein the second test structure includes a second conductor with one end connected to the second test pad and the other end connected to the second connection pad, wherein the one end and the other end of the second conductor are in contact with the second dielectric layer after the second test pad and the second connection pad are removed.

9. The method of claim 2, wherein the first dielectric layer covers the first test structure and the second test structure and includes a plurality of openings exposing the first test pad, the first connection pad, the second test pad, and the second connection pad, respectively, and the test probe contacts the first test pad, the second test pad, and the second connection pad through the plurality of openings.

10. The method as described in claim 9, further comprising: After removing the first test pad, the second test pad, and the second connection pad that have been probed by the test probe, the plurality of openings include a first opening exposing the first connection pad and a plurality of second openings on the bottom surface defined by the first dielectric layer, wherein the depth of the first opening is less than the depth of each of the second openings.

11. The method as described in claim 10, further comprising: A first conductive via electrically connecting the first interconnect structure and the first connecting pad, and a second conductive via electrically connecting the second interconnect structure and the second connecting pad are formed in the first dielectric layer, wherein after the first test pad, the second test pad, and the second connecting pad that have been probed by the test probe are removed, the second conductive via is exposed by one of the plurality of second openings.

12. The method as described in claim 11, further comprising: After removing the first test pad, the second test pad, and the second connection pad that have been probed by the test probe, a second dielectric layer is formed on the first dielectric layer, wherein the second dielectric layer fills the first opening and the plurality of second openings, and the second dielectric layer covers the exposed second conductive via; and a redistribution layer is formed on the second dielectric layer, wherein the redistribution layer includes a first via and a second via formed in the second dielectric layer, the first via contacting the first connection pad, and the second via not contacting the second conductive via.

13. A semiconductor device, comprising: The first grain includes a first interconnect structure disposed on a first region of the substrate; The second die includes a second interconnect structure disposed on a second region of the substrate, wherein the second region is different from the first region; a first dielectric layer disposed on the substrate and covering the first interconnect structure and the second interconnect structure; a first connector pad disposed on the first interconnect structure and electrically connected to the first interconnect structure, wherein the first dielectric layer includes a first opening defined by the first connector pad on the top surface of the first interconnect structure and a second opening defined by the first dielectric layer on the bottom surface and adjacent to the first opening, wherein the depth of the first opening is less than the depth of the second opening; a first conductor disposed in the first dielectric layer and connected to the first connector pad, wherein the first conductor is disposed between the first opening and the second opening; and a second dielectric layer disposed on the first dielectric layer and filling the first opening and the second opening, wherein the first conductor includes one end in contact with the second dielectric layer and the other end in contact with the first connector pad.

14. The semiconductor device as claimed in claim 13, further comprising: A redistribution layer is disposed on the second dielectric layer and includes a first through-hole that penetrates the second dielectric layer through the first opening and contacts the first connection pad.

15. The semiconductor device of claim 14, wherein the first dielectric layer includes a third opening and a fourth opening, the bottom surfaces of which are defined by the first dielectric layer and are adjacent to each other, over the second interconnect structure, the depth of the third opening being approximately equal to the depth of the fourth opening, and the second dielectric layer filling the third opening and the fourth opening, the semiconductor device further comprising: A second conductor is disposed in the first dielectric layer and between the third opening and the fourth opening, and the second conductor includes one end that is in contact with the second dielectric layer and the other end that is in contact with the second dielectric layer.

16. The semiconductor device as claimed in claim 15, further comprising: The first conductive via is disposed in the first dielectric layer below the first connecting pad and electrically connects the first interconnect structure to the first connecting pad. And a second conductive via, disposed in the first dielectric layer below the fourth opening and electrically connected to the second interconnect structure, wherein the second conductive via is covered by the second dielectric layer filling the fourth opening.

17. The semiconductor device of claim 16, wherein the redistribution layer includes a second via penetrating the second dielectric layer in the fourth opening and contacting the first dielectric layer, wherein the second via does not contact the second conductive via.

Images