Semiconductor structure and method for forming the same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a conductive structure penetrating an interconnection structure and a substrate where the interconnection structure is disposed thereon. The conductive structure includes a through-conductive via penetrating the interconnection structure and the substrate in a vertical direction and a ring-type conductive via disposed in the interconnection structure and surrounding the through-conductive via. The interconnection structure includes a conductive layer configured on the ring-type conductive via and being directly in contact with a top surface of the ring-type conductive via.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the same. Prior Technology

[0002] Three-dimensional (3D) wafer vertical stacking technology enables the vertical stacking of multiple active components (such as processors, programmable devices, memory devices, etc.) within a single wafer, thereby shortening the average line length and reducing interconnect resistance-capacitance delay (RC delay) and increasing system performance. In some embodiments, active components formed in vertically stacked wafers can be connected via through-substrate vias (TSVs). For example, TSVs through these wafers can provide electrical connection paths between different wafers, but this requires multiple TSV layers, each containing a TSV, to connect different wiring layers to provide the aforementioned electrical connection paths. However, with the continuous miniaturization of electronic devices, the fabrication of the TSV layers connecting these wafers faces various challenges (e.g., the stability of the electrical connections between the various TSV layers and the various wiring layers may not meet current or future requirements).

[0003] To address the challenges mentioned above, a technique using a single TSV to connect multiple wiring layers (also known as one-step TSV) has been proposed. However, one-step TSVs form the desired electrical connection path by penetrating through the wiring layers, which reduces the contact area between the one-step TSV and the wiring layers. Furthermore, the diameter of the one-step TSV gradually decreases with the number of wiring layers it passes through, and the contact area also gradually decreases with the number of wiring layers it passes through. As a result, to ensure the stability of the electrical connection path, it is difficult to reduce the diameter and spacing of one-step TSVs. Summary of the Invention

[0004] This invention provides a semiconductor structure and a method for forming the same. The conductive structure is designed to include a through-hole penetrating the substrate and an interconnect structure in the vertical direction, and an annular conductive via disposed in the interconnect structure and surrounding the through-hole. This annular conductive via increases the contact area between the through-hole and the conductive layer in the interconnect structure, thereby reducing contact resistance and providing good stability. Furthermore, when this semiconductor structure is applied to a one-step TSV, it not only maintains the stability of the desired electrical connection path but also further reduces the diameter and spacing of the one-step TSV.

[0005] An embodiment of the present invention provides a semiconductor structure including a conductive structure passing through an interconnect structure and a substrate on which the interconnect structure is disposed. The conductive structure includes a through-hole conductive via penetrating the interconnect structure and the substrate in a vertical direction, and an annular conductive via disposed in the interconnect structure and surrounding the through-hole conductive via. The interconnect structure includes a conductive layer disposed on the annular conductive via and in direct contact with the top surface of the annular conductive via.

[0006] In some embodiments, the bottom surface of the annular conductive via is in direct contact with the dielectric layer in the interconnect structure.

[0007] In some embodiments, the annular conductive via is in direct contact with the through conductive via.

[0008] In some embodiments, the annular conductive via and the conductive layer are respectively the via portion and wiring portion of the entire conductor layer.

[0009] In some embodiments, the through-hole includes a lower portion surrounded by an annular conductive via and a conductive layer, and an upper portion on the conductive layer, wherein the width of the upper portion in the horizontal direction is greater than the width of the lower portion in the horizontal direction.

[0010] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising forming a conductive structure. The conductive structure penetrates an interconnect structure and a substrate on which the interconnect structure is formed. The conductive structure includes a through-hole penetrating the substrate and the interconnect structure in a vertical direction, and an annular conductive via formed in the interconnect structure and surrounding the through-hole. The interconnect structure includes a conductive layer formed on the annular conductive via and in direct contact with the top surface of the annular conductive via.

[0011] In some embodiments, the step of forming an annular conductive via includes the following steps: forming a stack on a substrate, wherein the stack includes a plurality of alternately stacked first dielectric material layers and a plurality of second dielectric material layers, and the second dielectric material layers are between the first dielectric material layers; forming an annular via hole in the stack, wherein the annular via hole penetrates a first layer among the plurality of first dielectric material layers and a second layer above the first layer; forming a trench in the second layer communicating with the annular via hole; and filling the annular via hole and the trench with conductive material to form an annular conductive via and a conductive layer.

[0012] In some embodiments, the step of forming a through-hole includes: after forming an annular conductive via, forming an insulating layer on a stack; forming a through-hole in the insulating layer, a portion of the stack surrounded by the annular conductive via, and a substrate, wherein the through-hole exposes the sidewalls of the annular conductive via; and forming a through-hole in the through-hole.

[0013] In some embodiments, the step of forming an annular conductive via includes: forming a dielectric material layer on a substrate; forming an annular via hole in the dielectric material layer; and forming an annular conductive via in the annular via hole.

[0014] In some embodiments, the step of forming a through-hole includes: forming a conductive material layer on a dielectric material layer that covers the annular conductive via; patterning the conductive material layer to form a conductive layer, wherein the conductive layer includes an opening exposing a portion of the dielectric material layer surrounded by the annular conductive via; forming an insulating layer on the dielectric material layer that covers the conductive layer and fills the opening; forming a through-hole through the insulating layer, the portion of the dielectric material layer surrounded by the annular conductive via, and the substrate, wherein the through-hole exposes the sidewalls of the annular conductive via; and forming a through-hole in the through-hole.

[0015] Based on the above, in the above semiconductor structure and its formation method, the conductive structure is formed as a through conductive via penetrating the substrate and the interconnect structure in the vertical direction, and an annular conductive via formed in the interconnect structure and surrounding the through conductive via. In this way, the contact area between the through conductive via and the conductive layer in the interconnect structure can be increased by the annular conductive via, thereby reducing the contact resistance and having good stability. Simple Explanation of the Diagram

[0016] Figures 1A to 9B are schematic diagrams of a method for forming a semiconductor structure according to an embodiment of the present invention. Figures 10A to 18B are schematic diagrams of a method for forming a semiconductor structure according to another embodiment of the present invention. Implementation

[0017] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0018] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may mean that there are other elements between two elements. "Electrical connection" as used herein may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0019] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0020] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0021] Figures 1A to 9B are schematic diagrams of a method for forming a semiconductor structure according to an embodiment of the present invention. Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 9A are top views of a method for forming a semiconductor structure according to an embodiment of the present invention, while Figures 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, and 9B are cross-sectional views taken along line A-A' in Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 9A, respectively.

[0022] Methods for forming a semiconductor structure may include forming a conductive structure through an interconnect structure and a substrate on which the interconnect structure is formed. In some embodiments, the conductive structure may be formed by the following steps.

[0023] First, referring to Figures 1A and 1B, a substrate 100 is provided. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate, and a device layer formed on the semiconductor substrate or SOI substrate.

[0024] The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be P-type, while the second conductivity type can be N-type.

[0025] The component layer may include active components such as N-type metal-oxide semiconductor (NMOS), P-type metal-oxide semiconductor (PMOS), or complementary metal-oxide semiconductor (CMOS).

[0026] Next, a stacked STL is formed on the substrate 100. The stacked STL may include a plurality of alternating first dielectric material layers 102a, 102b, 102c and a plurality of second dielectric material layers 104a, 104b, wherein the second dielectric material layers 104a, 104b are spaced between the first dielectric material layers 102a, 102b, 102c. In some embodiments, the materials of the first dielectric material layers 102a, 102b, 102c may be different from the materials of the second dielectric material layers 104a, 104b. For example, the first dielectric material layers 102a, 102b, 102c may include oxides such as silicon oxide. The second dielectric material layers 104a, 104b may include nitrides such as silicon nitride.

[0027] Then, an annular via (as shown in Figures 3A and 3B) is formed in the stacked STL, wherein the annular via penetrates the first layer (e.g., the first dielectric layer 102b) and the second layer (e.g., the first dielectric layer 102c) above the first dielectric layers 102a, 102b, and 102c. In some embodiments, the annular via can be formed by the following steps. First, referring to Figures 2A and 2B, a mask pattern PR1 with an annular opening OP1 is formed on the stacked STL. In some embodiments, the mask pattern PR1 may include a photoresist pattern. Next, referring to Figures 2A and 2B, and Figures 3A and 3B, the first dielectric material layer 102c exposed by the annular opening OP1, and the second dielectric material layer 104b and the first dielectric material layer 102b below it, are removed to form the first dielectric material layer 112c, the second dielectric material layer 114b, and the first dielectric layer 112b, as well as the annular via hole VH1 exposing the second dielectric material layer 104a. In this embodiment, the second dielectric material layer 104a can serve as an etch stop layer for forming the annular via hole VH1. After forming the annular via hole VH1, the mask pattern PR1 is removed.

[0028] Then, a trench communicating with the annular via hole VH1 (e.g., trench T1 shown in Figures 5A and 5B) is formed in the second layer (e.g., the first dielectric material layer 102c or the first dielectric material layer 112c). In some embodiments, the trench can be formed by the following steps. First, referring to Figures 4A and 4B, a mask pattern PR2 is formed on the first dielectric material layer 112c. The mask pattern PR2 may include a first portion PR2a and a second portion PR2b. The first portion PR2a covers the portion of the first dielectric material layer 112c surrounded by the annular via hole VH1. The second portion PR2b defines the pattern of the trench to be formed subsequently (the pattern of trench T1 shown in Figure 5A). In some embodiments, the mask pattern PR2 may include a photoresist pattern. Next, referring to Figures 4A and 4B, and Figures 5A and 5B, the portion of the first dielectric material layer 112c exposed by the masking pattern PR2 and the second dielectric material layer 114b below that portion are removed to form the first dielectric material layer 122c, the second dielectric material layer 124b, and the trench T1. In some embodiments, during the step of removing the second dielectric material layer 114b, the portion of the second dielectric material layer 104a exposed by the annular via hole VH1 is also removed to form the second dielectric material layer 114a. After forming the trench T1, the masking pattern PR2 is removed.

[0029] In some embodiments, as shown in Figures 5A and 5B, a first portion 122c1 of the first dielectric layer 122c and a first portion 124b1 of the second dielectric layer 124b cover the portions of the first dielectric layer 112b and the second dielectric layer 114a surrounded by the annular via VH2. The sidewalls of the second portion 122c2 of the first dielectric layer 122c and the second portion 124b2 of the second dielectric layer 124b define the outline of the trench T1.

[0030] Next, referring to Figures 5A and 5B, and Figures 6A and 6B, conductive material CML1 is filled into the annular via VH2 and the trench T1. In some embodiments, conductive material CML1 may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. Then, referring to Figures 6A and 6B, and Figures 7A and 7B, a planarization process such as chemical mechanical polishing (CMP) is performed on conductive material CML1 to form conductive layer CL1 and annular conductive via RV1.

[0031] Then, referring to Figures 7A and 7B, and Figures 8A and 8B, after forming the conductive layer CL1 and the annular conductive via RV1, an insulating layer 150 is formed on the first dielectric material layer 122c. In some embodiments, the insulating layer 150 may include oxides, such as tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), oxides formed by high-density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), oxides formed by spin coating such as spin-on glass (SOG) and spin-on dielectric (SOD), or oxides formed by a high aspect ratio process (HARP).

[0032] Next, a through-hole TSV1h is formed, penetrating the insulating layer 150, a first portion 122c1 of the first dielectric material layer 122c, a first portion 124b1 of the second dielectric material layer 124b, a portion of the first dielectric material layer 112b and the second dielectric material layer 114a surrounded by the annular conductive via RV1, and the first dielectric material layer 102a and the substrate 100 below this portion. The through-hole TSV1h may include a first portion P1 formed in the insulating layer 150 and a second portion P2 exposing the sidewalls of the annular conductive via RV1. The second portion P2 of the through-hole TSV1h is formed by removing the first portion 122c1 of the first dielectric material layer 122c and the first portion 124b1 of the second dielectric material layer 124b, as well as the first dielectric material layer 112b, the second dielectric layer 114a, the first dielectric layer 102a, and the substrate 100 below them.

[0033] Subsequently, a through-hole TSV1 is formed in the through-hole TSV1h. In this way, the through-hole TSV1 penetrates the substrate 100 and the interconnect structure ICS1 in the vertical direction, and an annular conductive via RV1 is formed in the interconnect structure ICS1 and surrounds the through-hole TSV1. This annular conductive via RV1 increases the contact area between the through-hole TSV1 and the conductive layer CL1 in the interconnect structure ICS1, thereby reducing contact resistance and providing good stability. On the other hand, when this semiconductor structure is applied to a one-step TSV (e.g., when both ends of the through-hole TSV1 are electrically connected to other wafers), not only can the stability of the desired electrical connection path be maintained, but the diameter and spacing of the one-step TSV can also be further reduced. In some embodiments, the through-hole TSV1 may include a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0034] In some embodiments, as shown in FIG9B, the interconnect structure ICS1 may include first dielectric material layers 112a, 122b, 132 and second dielectric material layers 124a, 134 alternately disposed on the substrate 100, wherein the second dielectric material layers 124a, 134 are disposed between the first dielectric material layers 112a, 122b, 132. In some embodiments, a conductive layer CL1 may be formed in the first dielectric material layer 132 and the second dielectric material layer 134 in the interconnect structure ICS1, and an annular conductive via RV1 may be formed in the first dielectric material layer 122b and the second dielectric layer 124a in the interconnect structure ICS1.

[0035] Hereinafter, a semiconductor structure according to an embodiment of the present invention will be illustrated by way of FIG. 9A and FIG. 9B. The semiconductor structure of this embodiment can be formed by the method described above, but is not limited thereto.

[0036] Referring to Figures 9A and 9B, the semiconductor structure may include a conductive structure passing through an interconnect structure ICS1 and a substrate 100 on which the interconnect structure ICS1 is disposed. The conductive structure may include a through-hole conductive via TSV1 penetrating the interconnect structure ICS1 and the substrate 100 in a vertical direction, and an annular conductive via RV1 disposed in the interconnect structure ICS1 and surrounding the through-hole conductive via TSV1. The interconnect structure ICS1 may include a conductive layer CL1 disposed on the annular conductive via RV1 and in direct contact with the top surface of the annular conductive via RV1.

[0037] In some embodiments, the bottom surface of the annular conductive via RV1 may be in direct contact with the dielectric layer (e.g., the first dielectric material layer 112a) in the interconnect structure ICS1. In some embodiments, the annular conductive via RV1 is in direct contact with the through conductive via TSV1. In some embodiments, the annular conductive via RV1 and the conductive layer CL1 are respectively the via portion and the wiring portion of the entire conductor layer. In other words, the annular conductive via RV1 and the conductive layer CL1 are formed simultaneously in the same process, that is, the interface between the annular conductive via RV1 and the conductive layer CL1 does not include the interface between different materials. In some embodiments, the through conductive via TSV1 includes a lower portion TSV1b surrounded by the annular conductive via RV1 and the conductive layer CL1 and an upper portion TSV1a on the conductive layer CL1, wherein the width Wa of the upper portion TSV1a in the horizontal direction is greater than the width Wb of the lower portion TSV1b in the horizontal direction.

[0038] Figures 10A to 18B are schematic diagrams of a method for forming a semiconductor structure according to another embodiment of the present invention. Figures 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A are top views of a method for forming a semiconductor structure according to another embodiment of the present invention, while Figures 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, and 18B are cross-sectional views taken along line A-A' in Figures 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A, respectively.

[0039] In other embodiments, the conductive structure can be formed by the following steps, wherein the same or similar elements as those described in the above embodiments are represented by the same or similar element symbols, which will not be repeated here.

[0040] First, referring to Figures 10A and 10B, a dielectric material layer 202 is formed on a substrate 200. The substrate 200 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate, or a component layer formed on the semiconductor substrate or SOI substrate. The dielectric material layer 202 may include any suitable dielectric material.

[0041] Next, an annular via (as shown in Figures 11A and 11B) is formed in the dielectric material layer 202. In some embodiments, the annular via can be formed by the following steps: First, referring to Figures 10A and 10B, a mask pattern PR11 with an annular opening OP11 is formed on the dielectric material layer 202. Next, referring to Figures 10A and 10B and Figures 11A and 11B, a portion of the dielectric material layer 202 exposed by the annular opening OP11 is removed to form the dielectric material layer 212 and the annular via VH11. After forming the annular via VH11, the mask pattern PR11 is removed.

[0042] Next, referring to Figures 11A and 11B, and Figures 12A and 12B, an annular conductive via RV2 is formed in the annular via hole VH11. In some embodiments, the dielectric material layer 212 includes a portion 212a surrounded by the annular conductive via RV2.

[0043] Next, referring to Figures 12A and 12B, and Figures 13A and 13B, a conductive material layer CML2 covering the annular conductive via RV2 is formed on the dielectric material layer 212. In some embodiments, the conductive material layer CML2 may include a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0044] Then, the conductive material layer CML2 is patterned to form a conductive layer (as shown in Figures 15A and 15B). In some embodiments, the conductive layer can be formed by the following steps. First, referring to Figures 14A and 14B, a mask pattern PR22 is formed on the conductive material layer CML2. The mask pattern PR22 may include an opening OP22 that exposes a portion of the conductive material layer CML2. This portion of the conductive material layer CML2 may be located on a portion 212a of the dielectric material layer 212. That is, the shape and position of the opening OP22 of the mask pattern PR22 may correspond to the shape and position of the portion 212a of the dielectric material layer 212 surrounded by the annular conductive via RV2. Next, referring to Figures 14A and 14B and Figures 15A and 15B, the portion of the conductive material layer CML2 exposed by the mask pattern PR22 is removed to form the conductive layer CL2. In this embodiment, the conductive layer CL2 may include an opening CL2o that exposes a portion 212a of the dielectric material layer 212 surrounded by an annular conductive via RV2.

[0045] Next, referring to Figures 15A and 15B, and Figures 16A and 16B, an insulating layer 250 is formed on the dielectric material layer 212, covering the conductive layer CL2 and filling the opening CL2o. In some embodiments, the insulating layer 250 may include oxides, such as tetraethyl orthosilicate (TEOS), borosilicate glass (BPSG), oxides formed by high-density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), oxides formed by spin coating such as spin-coated glass (SOG) and spin-coated dielectric (SOD), or oxides formed by high aspect ratio process (HARP).

[0046] Next, referring to Figures 16A and 16B, and Figures 17A and 17B, a through-hole TSV2h is formed, penetrating the insulating layer 250, the dielectric material layer 212 surrounded by the annular conductive via RV2, and the substrate 200. The through-hole TSV2h exposes the sidewalls of the annular conductive via RV2. The through-hole TSV2h may include a first portion P11 formed in the insulating layer 250 and a second portion P22 exposing the sidewalls of the annular conductive via RV2. The second portion P22 of the through-hole TSV2h is formed by removing the portion of the insulating layer 250 in the opening CL2o of the conductive layer CL2, the portion 212a of the dielectric material layer 212 surrounded by the annular conductive via RV2, and the dielectric material layer 212 and the substrate 200 below it.

[0047] Next, referring to Figures 17A and 17B, and Figures 18A and 18B, a through-hole conductive via TSV2 is formed in the through-hole TSV2h. In this way, the through-hole conductive via TSV2 penetrates the substrate 200 and the interconnect structure ICS2 in the vertical direction, and an annular conductive via RV2 is formed in the interconnect structure ICS2 and surrounds the through-hole conductive via TSV2. This annular conductive via RV2 increases the contact area between the through-hole conductive via TSV2 and the conductive layer CL2 in the interconnect structure ICS2, thereby reducing contact resistance and providing good stability. On the other hand, when this semiconductor structure is applied to a one-step TSV, not only can the stability of the desired electrical connection path be maintained, but the diameter and spacing of the one-step TSV can also be further reduced. In some embodiments, the through-hole conductive via TSV2 may include a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In some embodiments, the through-hole TSV2 includes a lower portion TSV2b surrounded by an annular through-hole RV2 and a conductive layer CL2, and an upper portion TSV2a on the conductive layer CL2, wherein the width Wa of the upper portion TSV2a in the horizontal direction is greater than the width Wb of the lower portion TSV2b in the horizontal direction.

[0048] In summary, in the above-mentioned semiconductor structure and its formation method, the conductive structure is formed as a through conductive via penetrating the substrate and the interconnect structure in the vertical direction, and an annular conductive via formed in the interconnect structure and surrounding the through conductive via. In this way, the contact area between the through conductive via and the conductive layer in the interconnect structure can be increased by the annular conductive via, thereby reducing the contact resistance and having good stability.

[0049] 100, 200: Base 102a, 112a: First dielectric material layer 102b, 112b, 122b: First dielectric material layer 102c, 112c, 122c, 132: First dielectric material layer 122c1: Part 1 122c2: Part Two 104a, 114a, 124a: Second dielectric material layer 104b, 114b, 124b, 134: Second dielectric material layer 124b1: Part 1 124b2: Part Two 150, 250: Insulation layer 202, 212: Dielectric material layers 212a: Part CL1, CL2: Conductive layers CL2o: Opening CML1: Conductive material CML2: Conductive material layer ICS1, ICS2: Internal Wiring Structure OP1, OP11: Annular opening OP22: Opening P1, P11: Part 1 P2, P22: Part Two PR1, PR2, PR11, PR22: Curtain Pattern PR2a: Part 1 PR2b: Part Two RV1, RV2: Annular conductive vias STL: Stacked Layers T1: Ditch TSV1, TSV2: Through-hole conductive vias TSV1a, TSV2a: Upper part TSV1b, TSV2b: Lower Part TSV1h, TSV2h: Through-hole VH1, VH11, VH2: Annular through-holes Wa, Wb: Width

Claims

1. A semiconductor structure, comprising: A conductive structure, penetrating an interconnect structure and a substrate on which the interconnect structure is disposed, wherein the conductive structure includes: a through conductive via penetrating the interconnect structure and the substrate in a vertical direction; and an annular conductive via disposed in the interconnect structure and surrounding the through conductive via, wherein the interconnect structure includes a conductive layer disposed on the annular conductive via and in direct contact with the top surface of the annular conductive via, wherein the through conductive via includes a lower portion surrounded by the annular conductive via and the conductive layer and an upper portion on the conductive layer, wherein the width of the upper portion in the horizontal direction is greater than the width of the lower portion in the horizontal direction.

2. The semiconductor structure as claimed in claim 1, wherein the bottom surface of the annular conductive via is in direct contact with the dielectric layer in the interconnect structure.

3. The semiconductor structure as claimed in claim 1, wherein the annular conductive via is in direct contact with the through conductive via.

4. The semiconductor structure as claimed in claim 1, wherein the annular conductive via and the conductive layer are respectively the via portion and wiring portion of the entire conductor layer.

5. A method for forming a semiconductor structure, comprising: A conductive structure is formed, wherein the conductive structure penetrates an interconnect structure and a substrate on which the interconnect structure is formed, wherein the conductive structure includes: a through conductive via penetrating the substrate and the interconnect structure in a vertical direction; and an annular conductive via formed in the interconnect structure and surrounding the through conductive via, wherein the interconnect structure includes a conductive layer formed on the annular conductive via and in direct contact with the top surface of the annular conductive via, and the step of forming the annular conductive via includes: forming a stack on the substrate, wherein the stack includes a plurality of alternately stacked first dielectric material layers and a plurality of second dielectric material layers, wherein the second dielectric material layers are between the first dielectric material layers; and forming an annular via hole in the stack, wherein the annular via hole penetrates a first layer among the plurality of first dielectric material layers and a second layer above the first layer; A channel communicating with the annular through-hole is formed in the second layer; and conductive material is filled into the annular through-hole and the channel to form the annular conductive through-hole and the conductive layer.

6. The method of claim 5, wherein the step of forming the through conductive via comprises: After forming the annular conductive via, an insulating layer is formed on the stack; A through-hole is formed through the insulating layer, the portion of the stack surrounded by the annular conductive via, and the substrate, wherein the through-hole exposes the sidewall of the annular conductive via; and the through-hole is formed in the through-hole.

7. A method for forming a semiconductor structure, comprising: A conductive structure is formed, wherein the conductive structure penetrates an interconnect structure and a substrate on which the interconnect structure is formed, wherein the conductive structure includes: a through conductive via penetrating the substrate and the interconnect structure in a vertical direction; and an annular conductive via formed in the interconnect structure and surrounding the through conductive via, wherein the interconnect structure includes a conductive layer formed on the annular conductive via and in direct contact with the top surface of the annular conductive via, and the step of forming the annular conductive via includes: forming a dielectric material layer on the substrate; forming an annular via hole in the dielectric material layer; and forming the annular conductive via in the annular via hole.

8. The method of claim 7, wherein the step of forming the through conductive via comprises: A conductive material layer covering the annular conductive via is formed on the dielectric material layer; The conductive material layer is patterned to form the conductive layer, wherein the conductive layer includes an opening that exposes a portion of the dielectric material layer surrounded by the annular conductive via. An insulating layer is formed on the dielectric material layer, covering the conductive layer and filling the opening; A through-hole is formed through the portion of the insulating layer, the dielectric material layer, and the substrate surrounded by the annular conductive via, wherein the through-hole exposes the sidewalls of the annular conductive via; and the through-hole is formed in the through-hole.

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