Build up bonding layer process and structure for low temperature bonding
TW202633438APending Publication Date: 2026-08-01AMERICAN CO ADIA SEMICON BONDING TECH CO LTD
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Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- AMERICAN CO ADIA SEMICON BONDING TECH CO LTD
- Filing Date
- 2025-09-15
- Publication Date
- 2026-08-01
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Abstract
Disclosed herein are methods of forming a microelectronic component. In some embodiments, the method includes providing a substrate, forming a metal feature over the substrate, forming an organic dielectric layer over the element such that the organic dielectric layer covers sidewalls of the metal feature, forming an inorganic dielectric material over the organic dielectric layer, and planarizing the inorganic dielectric material, the organic dielectric layer, and the metal feature. The planarized surface can serve as a hybrid bonding surface. The metal feature is exposed at the hybrid bonding surface.
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