Manufacturing method of circuit components with solder bumps and circuit components with solder bumps
TW202633455APending Publication Date: 2026-08-01RESONAC CORP
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Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- RESONAC CORP
- Filing Date
- 2025-10-14
- Publication Date
- 2026-08-01
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Abstract
The method for manufacturing the circuit component with solder bumps includes: a deposition step (S02), in which a solder layer (11) is deposited on one side of a substrate (2) having conductive pillars (3) in a region containing the top surface (3a) of the pillars (3); a reduction step (S03), in which the solder layer (11) is reduced in a reducing gas environment to form solder bumps (4) on the top surface (3a) of the pillars (3); a removal step (S04), in which excess solder layer (12) remaining on one side of the substrate (2) after the reduction step is removed; and a re-reduction step (S05), in which the solder bumps (4) on the top surface (3a) of the pillars (3) are re-reduced in a reducing gas environment to form an alloy layer (6) based on the constituent materials of the pillars (3) and the constituent materials of the solder bumps (4) at the interface between the pillars (3) and the solder bumps (4).
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