Three-dimensional integrated circuit, mobile communication device and method of making three-dimensional integrated circuit

TW202633459APending Publication Date: 2026-08-01QORVO US INC
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Patent Information

Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-10-22
Publication Date
2026-08-01

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Abstract

Improved die-to-wafer stacking techniques are disclosed. In particular, during assembly of a three-dimensional integrated circuit (3DIC), a wafer may include insulation between multiple dice provided by a spun polymer. This spun polymer replaces a more traditional silicon oxide insulator created by deposition techniques. Replacement of the silicon oxide insulator makes mass production of the wafer economically feasible, which in turn allows creation of 3DIC at commercially practical volumes. The use of a 3DIC minimizes lateral surface area of a circuit package, allowing for more real estate to be used by a battery within a mobile computing device. Further, the use of a 3DIC may allow for shorter interconnects between circuit elements, which may, in turn, allow for faster communication between the circuit elements.
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