Semiconductor package suppressing electrical coupling
TW202633464APending Publication Date: 2026-08-01ALPHA & OMEGA SEMICON INT LP
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Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- ALPHA & OMEGA SEMICON INT LP
- Filing Date
- 2025-12-11
- Publication Date
- 2026-08-01
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Figure TWG2TA001071448_001 
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Abstract
A semiconductor package comprises a lead frame, a first high side field-effect transistor (FET), a second high side FET, a first metal clip, a second metal clip, a first low side FET, a second low side FET, a third metal clip, a metal slug, an integrated circuit (IC), a plurality of bond wires, and a molding encapsulation. A method comprises the steps of providing a lead frame; mounting a first high side FET and a second high side FET; attaching a first metal clip and a second metal clip; mounting a first low side FET and a second low side FET; attaching a third metal clip; attaching an IC; forming a molding encapsulation; and applying a singulation process.
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