Package substrate and manufacturing method thereof

Abstract

Disclosed is a package substrate, which includes a core board and dielectric layers formed on the opposite surfaces of the core board, wherein the dielectric layers serve as a cover layer to prevent the substrate from cracking. The package substrate further includes a plurality of through holes penetrating through the core board and the dielectric layers, a barrier layer formed on the inner walls of the through holes, and a seed layer formed on the barrier layer on the inner walls of the through holes to ensure the electrical connection of the circuit portions and circuit structures on the opposite surfaces of the core board.

Claims

1. A packaging substrate, comprising: The core plate has a first surface and a second surface that are opposite to each other; The first dielectric layer is formed only on the first and second surfaces of the core plate. A plurality of vias penetrate the core plate and the first dielectric layer and connect the first surface and the second surface of the core plate; a barrier layer is formed on the inner wall of the plurality of vias and partially contacts the core plate; a seed layer is formed on the barrier layer on the inner wall of the plurality of vias; a circuit portion is formed on the first dielectric layer on the first surface and the second surface of the core plate and electrically connected to the seed layer on the inner wall of the plurality of vias; and a circuit structure is formed on the first dielectric layer and the circuit portion on the first surface and the second surface of the core plate, the circuit structure comprising at least one second dielectric layer, at least one circuit layer disposed on the second dielectric layer and a plurality of conductive blind vias formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer fills the plurality of vias.

2. The packaging substrate as described in claim 1, wherein, The core plate is made of glass, ceramic, silicon carbide (SiC) or composite materials.

3. The packaging substrate as described in claim 1, wherein, The first dielectric layer is a glass fiber prepreg (PP).

4. The packaging substrate as described in claim 3, wherein, The glass fiber prepreg (PP) contains epoxy groups, has a thickness of 1 nm, and has a coefficient of thermal expansion (CTE) of 2 ppm / ℃.

5. The packaging substrate as described in claim 1, wherein, The barrier layer is formed of tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride, or diamond-like carbon (DLC), and the thickness of the barrier layer is 1 nm.

6. The packaging substrate as described in claim 1, wherein, The seed layer is made of copper or manganese-doped copper or ruthenium, and the thickness of the seed layer is 0.5 μm.

7. The packaging substrate as described in claim 1, wherein, The circuit section contains the same material as the seed layer.

8. The packaging substrate as described in claim 7, wherein, The circuit section contains the same material as the barrier layer and the seed layer, and the barrier layer is a conductive material.

9. The packaging substrate as described in claim 1, wherein, The circuit structure has a weld-resistant layer.

10. A method for manufacturing a packaging substrate, comprising: Provide a core plate having a first surface and a second surface that are opposite each other; Only the first dielectric layer is formed on the first and second surfaces of the core plate; A plurality of vias are formed penetrating the core plate and the first dielectric layer, such that the plurality of vias connect the first surface and the second surface of the core plate; a barrier layer is formed on the first dielectric layer and on the inner wall of the plurality of vias, and partially contacts the core plate; a seed layer is formed on the barrier layer, and the seed layer located on the first dielectric layer on the first surface and the second surface of the core plate is patterned to form a circuit portion, and the circuit portion is electrically connected to the seed layer on the inner wall of the plurality of vias; and a circuit structure is formed on the first dielectric layer and the circuit portion on the first surface and the second surface of the core plate, the circuit structure including at least one second dielectric layer, at least one circuit layer disposed on the second dielectric layer, and a plurality of conductive blind vias formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer fills the plurality of vias.

11. The method for manufacturing the packaging substrate as described in claim 10, wherein, The core plate is made of glass, ceramic, silicon carbide (SiC) or composite materials.

12. The method for manufacturing the packaging substrate as described in claim 10, wherein, The first dielectric layer is a glass fiber prepreg (PP).

13. The method for manufacturing the packaging substrate as described in claim 12, wherein, The glass fiber prepreg (PP) contains epoxy groups, has a thickness of 1 nm, and has a coefficient of thermal expansion (CTE) of 2 ppm / ℃.

14. The method for manufacturing the packaging substrate as described in claim 10, wherein, The barrier layer is formed of tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride, or diamond-like carbon (DLC), and the thickness of the barrier layer is 1 nm.

15. The method for manufacturing the packaging substrate as described in claim 10, wherein, The seed layer is made of copper or manganese-doped copper or ruthenium, and the thickness of the seed layer is 0.5 μm.

16. The method for manufacturing the packaging substrate as described in claim 10, wherein, The circuit section contains the same material as the seed layer.

17. The method for manufacturing the packaging substrate as described in claim 16, wherein, The barrier layer is a conductive material, and the step of patterning the seed layer further includes patterning the barrier layer on the first dielectric layer located on the first surface and the second surface of the core plate, so that the circuit portion contains the same material as the barrier layer and the seed layer.

18. The method for manufacturing the packaging substrate as described in claim 10, wherein, The circuit structure has a weld-resistant layer.

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