Electronic device

Abstract

An electronic device includes semiconductor dies, an interposer, and a passive component. The semiconductor dies are laterally spaced from each other by a die gap region. The semiconductor dies are bonded onto a first surface of the interposer, wherein the interposer provides a gap electric transmission pathway in the die gap region, the gap electric transmission pathway extends from the first surface of the interposer to a second surface of the interposer, and the second surface is opposite to the first surface. The passive component is bonded onto the second surface of the interposer, and located in the die gap region, wherein the passive component is electrically connected to the semiconductor dies through the gap electric transmission pathway.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Previous Technology]

[0002] Integrated circuit packaging is becoming increasingly complex, with more device chips packaged in the same package to form systems with more functions. Integrated Passive Devices (IPDs) are discrete components that are commonly used in packages. IPDs are electrically connected to the semiconductor chip in the package and help reduce transmission losses and power consumption in the package. [Summary of the Invention]

[0003] This disclosure relates to an electronic device that provides a short transmission path between a semiconductor die and a passive element bonded to the opposite side of an interposer.

[0004] According to an embodiment of the present disclosure, an electronic device includes a semiconductor die, an interposer, and a passive element. The semiconductor dies are laterally spaced apart by die gap regions. The semiconductor dies are bonded to a first surface of the interposer, wherein the interposer provides a gap electrical transport path in the die gap regions, the gap electrical transport path extending from the first surface of the interposer to a second surface of the interposer, and the second surface is opposite to the first surface. The passive element is bonded to the second surface of the interposer and located in the die gap regions, wherein the passive element is electrically connected to the semiconductor die through the gap electrical transport path.

[0005] According to an embodiment of the present disclosure, an electronic device includes a semiconductor die and an interposer. The semiconductor dies are laterally spaced through die gap regions. The semiconductor dies are bonded to the interposer, wherein the interposer includes a substrate, a redistribution circuit structure, and a plurality of embedded passive components. The redistribution circuit structure is disposed on the substrate and includes a dielectric structure and a metal layer embedded in the dielectric structure to provide a gap electrical transport path in the die gap regions. The embedded passive components are disposed between the substrate and the redistribution circuit structure. At least one embedded passive component is electrically connected to the semiconductor die through the gap electrical transport path.

[0006] Based on the above, an electronic device having semiconductor dies laterally spaced from each other provides an interposer layer having gap electrical transport paths in the die-gap regions between the semiconductor dies for electrical connection between the semiconductor dies and passive components bonded to different surfaces of the interposer layer. The gap electrical transport paths and the passive components are located in the die-gap regions to reduce the electrical transport path between the passive components and the semiconductor dies, which ensures the effectiveness of the passive components for better device performance.

Implementation Method

[0007] FIG1 schematically illustrates a side view of an electronic device according to some embodiments of the present disclosure. In FIG1, the electronic device 100 includes semiconductor dies 110A and 110B, an interposer 120, and a passive element 130. For descriptive purposes, FIG1 uses a simple pattern to show the elements, which is not intended to limit the actual structure of these elements. Semiconductor dies 110A and 110B are bonded to a first surface T120 of the interposer 120 and are laterally spaced apart in the X direction by a die gap region RG. Passive element 130 is bonded to a second surface B120 of the interposer 120 opposite to the first surface T120. In some embodiments, passive element 130 is located in the die gap region RG. The interposer 120 may provide a gap electrical transport path 122 in the die gap region RG through which passive element 130 is electrically connected to semiconductor dies 110A and 110B. In some embodiments, the gap electrical transmission path 122 may include a first gap electrical transmission path 122A and a second gap electrical transmission path 122B, wherein the second gap electrical transmission path 122B transmits a different supply voltage than the first gap electrical transmission path 122A.

[0008] Semiconductor dies 110A and 110B may contain transistors therein to implement the desired circuit functions. Each of semiconductor dies 110A and 110B may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a similar die, or a combination thereof. In some embodiments, semiconductor dies 110A and 110B communicate with each other via signals.

[0009] Interposer 120 is an element that includes at least a redistribution circuit structure that establishes electrical transport paths to enable the necessary electrical connections between semiconductor dies 110A and 110B. In some embodiments, a first gap electrical transport path 122A and a second gap electrical transport path 122B provided by interposer 120 pass through interposer 120 in the thickness direction (Z direction) and extend laterally from the die gap region RG toward semiconductor dies 110A and 110B in the X direction. For example, each of the first gap electrical transport path 122A and the second gap electrical transport path 122B may extend from a first surface T120 to a second surface B120. The first gap electrical transport path 122A and the second gap electrical transport path 122B wire between semiconductor dies 110A and 110B bonded to the first surface T120 and passive element 130 bonded to the second surface B120.

[0010] Passive element 130 may be a decoupling capacitor integrated into electronic device 100, such as a silicon capacitor (Si-Cap). Passive element 130 may be pre-fabricated as a package and bonded to the second surface B120 of interposer 120 as shown in FIG1. ​​In some applications, passive element 130 may be referred to as an integrated passive device (IPD). Passive element 130 may include a first bonding pad 132A and a second bonding pad 132B bonded to interposer 120. In some embodiments, the first bonding pad 132A is a power pad for transmitting power (such as VDD), and the second bonding pad 132B is a grounding pad electrically grounded. At least one first bonding pad 132A is electrically connected to semiconductor dies 110A and 110B through a first gap electrical transmission path 122A, and at least one second bonding pad 132B is electrically connected to semiconductor dies 110A and 110B through a second gap electrical transmission path 122B. In some embodiments, the first bonding pad 132A is configured to transmit power, and the second bonding pad 132B is electrically grounded. Therefore, the first gap electrical transmission path 122A transmits power, and the second gap electrical transmission path 122B is electrically grounded.

[0011] In some embodiments, the interposer 120 includes other electrical transport paths, such as a lower electrical transport path 124 disposed below semiconductor die 110A and a lower electrical transport path 126 disposed below semiconductor die 110B. The lower electrical transport path 124 includes a first lower electrical transport path 124A and a second lower electrical transport path 124B, the second lower electrical transport path 124B transmitting a different supply voltage than the first lower electrical transport path 124A. The first lower electrical transport path 124A and the second lower electrical transport path 124B are located below semiconductor die 110A and are electrically connected between semiconductor die 110A and passive element 130. For example, the first lower electrical transport path 124A is connected to one of the first bonding pads 132A of passive element 130 to deliver power, and the second lower electrical transport path 124B is connected to one of the second bonding pads 132B to be electrically grounded.

[0012] The lower electrical transmission path 126 includes a first lower electrical transmission path 126A and a second lower electrical transmission path 126B, the second lower electrical transmission path 126B transmitting a different supply voltage than the first lower electrical transmission path 126A. The first lower electrical transmission path 126A and the second lower electrical transmission path 126B are located below the semiconductor die 110B and are electrically connected between the semiconductor die 110B and the passive element 130. For example, the first lower electrical transmission path 126A is connected to one of the first bonding pads 132A of the passive element 130 to transmit power, and the second lower electrical transmission path 126B is connected to one of the second bonding pads 132B to be electrically grounded.

[0013] Therefore, the passive element 130 can be electrically connected to semiconductor dies 110A and 110B via the gap electrical transmission path 122 in the die gap region RG and the lower electrical transmission path 124 below semiconductor die 110A and the second lower electrical transmission path 126 below semiconductor die 110B. In some embodiments, the interposer layer 120 may further provide a lateral signal transmission path 128 to enable signal transmission between semiconductor dies 110A and 110B in the lateral direction (e.g., the X direction).

[0014] In this embodiment, the first gap electrical transmission path 122A, the second gap electrical transmission path 122B, and the passive element 130 are located in the inter-die region RG between semiconductor dies 110A and semiconductor dies 110B, such that the first gap electrical transmission path 122A and the second gap electrical transmission path 122B provide shorter transmission paths than the lower electrical transmission paths 124 and 126, which helps to reduce transmission resistance and inductance. The gap electrical transmission path 122 provides optimized electrical transmission performance, reducing transmission losses caused by inductor DC resistance (DCR) and reactance.

[0015] FIG2 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. The electronic device 200 shown in FIG2 includes semiconductor dies 210A and 210B, an interposer 220, a passive element 230, and a package substrate 240. In this embodiment, the electronic device 200 can be considered as an implementation of the electronic device 100, wherein semiconductor dies 210A and 210B can be equivalent to semiconductor dies 110A and 110B, interposer 220 can be equivalent to interposer 120, and passive element 230 can be equivalent to passive element 130. Semiconductor dies 110A and 110B are bonded to a first surface T220 of interposer 220, for example, through bonding structure 252. Interposer 220 is bonded to a first surface T240 of package substrate 240 through bonding structure 254. Furthermore, conductive connectors 256 are disposed on a second surface B240 of package substrate 240 for connecting the electronic device 200 to an external device. In some embodiments, the bonding structure 252 may be a microbump, the bonding structure 254 may be a C4 bump, and the conductive connector 256 may be a BGA ball, but this disclosure is not limited thereto.

[0016] Semiconductor dies 210A and 210B can be considered as implementations of semiconductor dies 110A and 110B depicted in FIG1. ​​In some embodiments, each of semiconductor dies 210A and 210B includes electronic components and interconnect structures fabricated in / on a semiconductor substrate to achieve a specific circuit function. The electronic components formed in semiconductor dies 210A and 210B may include active components (such as transistors), passive components (such as capacitors), and / or combinations thereof. Referring to the description in FIG1, each of the semiconductor dies 210A and 210B may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a similar die, or a combination thereof.

[0017] Intermediate layer 220 may include a redistribution circuit structure RDL, which includes a dielectric structure DLS and metal layers M1, M2...Mx-1, Mx embedded in the dielectric structure DLS, wherein x is 5 in this embodiment, but this disclosure is not limited thereto. The dielectric structure DLS is formed by multiple dielectric layers, separating each metal layer M1...Mx from the next. The dielectric structure DLS may be made of dielectric materials such as polyimide, and the metal layers may be made of conductive metal materials such as copper, but this disclosure is not limited thereto. The metal layers M1...Mx are arranged sequentially at different levels from the first surface T220 to the second surface B220 of the intermediate layer 220. The metal layers M1...Mx are patterned to form discrete conductive features to establish the required electrical transmission wiring. To connect the different conductive features in the different metal layers M1...Mx, the redistribution circuit structure RDL also includes vias TV, each via connecting the gap conductive features in two adjacent metal layers M1...Mx.

[0018] In this embodiment, the interposer 220 may further include a bonding pad PD disposed on its first surface T220. The bonding pad PD is connected to the metal layer M1 closest to the first surface T220, and semiconductor dies 210A and 210B are bonded to the bonding pad PD via bonding structure 252. In some embodiments, the bonding pad PD may be made of a different conductive metal material than the metal layers M1...Mx. For example, the bonding pad PD may be made of aluminum, but this disclosure is not limited thereto. A further bonding pad (not shown) may be disposed on the second surface B220 of the interposer 220 as a bottom bonding pad, and bonding structure 254 is disposed on the bottom bonding pad, but this disclosure is not limited thereto. In some embodiments, the dielectric structure DLS may expose a portion of the metal layer Mx closest to the second surface B220 of the interposer 220, and bonding structure 254 is disposed on the exposed portion of the metal layer Mx to form the desired electrical connection.

[0019] The passive element 230 is bonded to the second surface B220 of the interposer layer 220 via a bonding structure 232 and electrically connected to semiconductor dies 210A and 210B via corresponding metal features formed by the metal layers M1...Mx of the redistribution circuit structure RDL. In some embodiments, the bonding structure 232 may be a conductive bump connected to a bonding pad (not shown) of the passive element 230. For example, a portion of the bonding structure 232 may conduct power and be connected to the first bonding pad 132A depicted in FIG. 1, and another portion of the bonding structure 232 may be connected to ground and be connected to the second bonding pad 132B depicted in FIG. 1.

[0020] In this embodiment, semiconductor die 210A and semiconductor die 210B are laterally separated in the X direction by a die gap region RG, and the region where semiconductor dies 210A and 210B are located is considered as die region RD. Passive element 230 is located in die gap region RG. The metal layers M1...Mx of the redistribution circuit structure RDL construct a gap conductive feature 222, a lower conductive feature 224 below semiconductor die 210A, and a lower conductive feature 226 below semiconductor die 210B located in die gap region RG. For illustrative purposes, FIG2 shows only one gap conductive feature 222, one lower conductive feature 224, and one lower conductive feature 226. Gap conductive feature 222 is located in die gap region RG and is directly above passive element 230, while lower conductive features 224 and lower conductive features 226 are located in die region RD and are below semiconductor dies 210A and 210B. In some embodiments, the gap conductive feature 222 can be regarded as an example of implementing the first gap electrical transmission path 122A and the second gap electrical transmission path 122B respectively, the lower conductive feature 224 can be regarded as an example of implementing the first lower electrical transmission path 124A and the second lower electrical transmission path 124B respectively, and the lower conductive feature 226 can be regarded as an example of implementing the first lower electrical transmission path 126A and the second lower electrical transmission path 126B respectively.

[0021] The gap conductive feature 222 includes a top pattern 222A in metal layer M1 (the top metal layer in metal layers M1...Mx), a bottom pattern 222B in metal layer Mx (the bottom metal layer in metal layers M1...Mx), and an intermediate pattern 222C in the intermediate metal layers M2...Mx-1 between metal layers M1 and Mx. The intermediate pattern 222C establishes a continuous electrical transport path between the top pattern 222A and the bottom pattern 222B in the Z direction. In some embodiments, the top pattern 222A, the bottom pattern 222B, and the intermediate pattern 222C are mainly located in the grain gap region RG. The bottom pattern 222B may be correspondingly located in and electrically connected to one of the bonding structures 232. The top pattern 222A extends laterally from the grain gap region RG toward the semiconductor grains 210A and 210B and partially overlaps the semiconductor grains 210A and 210B. Specifically, corresponding portions of the bonding pads PD for bonding semiconductor dies 210A and 210B are configured on and connected to the top layer pattern 222A. Thus, the top layer pattern 222A is electrically connected to the semiconductor dies 210A and 210B via corresponding portions of the bonding pads PD. In some embodiments, an intermediate pattern 222C may be stacked between the top layer pattern 222A and the bottom layer pattern 222B along the thickness direction (Z direction), such that the gap conductive feature 222 provides a substantially perpendicular electrical transport path between the semiconductor dies 210A and 210B and the passive element 230.

[0022] The lower conductive feature 224 in the grain region RD can electrically connect the passive element 230 and one of the semiconductor dies (i.e., semiconductor die 210A). The lower conductive feature 224 includes a top pattern 224A in metal layer M1, a bottom pattern 224B in metal layer Mx, and an intermediate pattern 224C in intermediate metal layers M2...Mx-1 between metal layers M1 and Mx. The intermediate pattern 224C is arranged along the thickness direction (Z direction) and located below the semiconductor die 210A to connect the top pattern 224A and the bottom pattern 224B. A corresponding bonding pad PD is disposed on the top pattern 224A and electrically connected to the semiconductor die 210A through bonding structure 252. The bottom pattern 224B extends laterally from the grain region RD toward the grain gap region RG and partially overlaps the passive element 230. In some embodiments, the extension length of the bottom pattern 224B of the lower conductive feature 224 is greater than the extension length of the top pattern 222A of the gap conductive feature 222, such that the gap conductive feature 222 provides a relatively short electrical transport path between the semiconductor die 210A and the passive element 230, which is shorter than that of the lower conductive feature 224.

[0023] The lower conductive feature 226 has a structure similar to that of the lower conductive feature 224 and is located below the semiconductor die 210B to provide electrical transmission between the semiconductor die 210B and the passive element 230. Specifically, the lower conductive feature 226 includes a top pattern 226A in metal layer M1, a bottom pattern 226B in metal layer Mx, and an intermediate pattern 226C arranged between the top pattern 226A and the bottom pattern 226B in intermediate metal layers M2...Mx-1 between metal layers M1 and Mx. The redistribution circuit structure RDL may further include other conductive features, such as a lateral conductive feature 228 in metal layers M2...Mx-1 between metal layers M1 and Mx, a portion of which may extend partially through the die gap region RG to provide a lateral electrical transmission path between the semiconductor die 210A and the semiconductor die 210B, as an example of implementing the lateral signal transmission path 128 depicted in FIG. 1.

[0024] FIG3 schematically illustrates a top view of a portion of the metal layer Mx of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. In some embodiments, the metal layer Mx is configured to form a power delivery network (PDN) to deliver power to an electronic device. For descriptive purposes, FIG3 shows a portion of the die gap region RG and the die region RD where the semiconductor dies 210A and 210B depicted in FIG2 are located. FIG3 shows the metal layer Mx in the die gap region RG and also shows the arrangement of the bonding structures 232 of the passive element 230 depicted in FIG2. The bonding structures 232 include a first bonding structure 232A for delivering power and a second bonding structure 232B electrically connected to ground. The first bonding structures 232A are grouped together along the Y direction. The second bonding structures 232B are inserted between different groups of the first bonding structures 232A, but the present disclosure is not limited thereto. As shown in FIG3, as an example, each group of the first bonding structures 232A includes ten first bonding structures 232A arranged in a 5×2 array, but the present disclosure is not limited thereto. The metal layer Mx includes a first bottom layer pattern 262a connected to the first bonding structure 232A and a second bottom layer pattern 262b connected to the second bonding structure 232B. The first bottom layer pattern 262a and the second bottom layer pattern 262b are arranged alternately along the Y direction. Each of the first bottom layer pattern 262a and the second bottom layer pattern 262b is an elongated pattern extending across the grain gap region RG along the X direction, partially overlapping the grain regions RD on both sides of the grain gap region RG.

[0025] Each of the first bottom layer pattern 262a and the second bottom layer pattern 262b may serve as an example of the bottom layer pattern 222B for implementing the gap conductive feature 222. When the gap conductive feature 222 of FIG. 2 is configured to transmit power to form the first gap electrical transmission path 122A in FIG. 1, the bottom layer pattern 222B of the gap conductive feature 222 may be implemented by the first bottom layer pattern 262a. When the gap conductive feature 222 of FIG. 2 is configured to be connected to ground to form the second gap electrical transmission path 122B in FIG. 1, the bottom layer pattern 222B of the gap conductive feature 222 may be implemented by the second bottom layer pattern 262b. In some embodiments, each of the first bottom layer pattern 262a and the second bottom layer pattern 262b may extend to the grain region RD and serve as an example of the bottom layer pattern 224B for implementing the lower conductive feature 224 or the bottom layer pattern 226B for the lower conductive feature 226 depicted in FIG. 2. For example, the bottom pattern 222B of the gap conductive feature 222, the bottom pattern 224B of the bottom conductive feature 224, and the bottom pattern 226B of the bottom conductive feature 226 can be realized by a common pattern in the grain gap region RG, such as a first bottom pattern 262a and a second bottom pattern 262b.

[0026] FIG4 schematically illustrates a top view of a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. For descriptive purposes, FIG4 shows a portion of the die gap region RG and the die region RD where the semiconductor dies 210A and 210B depicted in FIG2 are located. FIG4 shows the pattern design of the metal layer M1 in the X and Y direction planes. In addition, FIG4 also shows a bonding structure 252 for connecting the semiconductor dies 210A and 210B to the interposer layer 220 depicted in FIG2. The bonding structure 252 includes a first bonding structure 252A for transmitting power and a second bonding structure 252B for connecting to ground, while other bonding structures 252 are configured to transmit electrical signals of the semiconductor dies 210A and 210B. The first bonding structure 252A and the second bonding structure 252B are arranged along the periphery of the semiconductor die 210A or 210B and are configured to be electrically connected to the passive element 230 depicted in FIG2, wherein the first bonding structure 252A is arranged near the die gap region RG. The metal layer M1 of the redistribution circuit structure RDL may include a first top layer pattern 264a and a second top layer pattern 264b. The first top layer pattern 264a is configured to conduct power and extends from the inter-die region RG to the die region RD to connect a first bonding structure 252A arranged at the boundary between the inter-die region RG and the die region RD. The second top layer pattern 264b is a linear pattern extending in the X direction, located on opposite sides of the first top layer pattern 264a in the Y direction. The second top layer pattern 264b extends from the inter-die region RG to the die region RD to connect a second bonding structure 252B located around the die region RD. The first top layer pattern 264a occupies a large portion of the area of ​​the inter-die region RG as a block pattern, but this disclosure is not limited thereto.

[0027] FIG5 schematically illustrates a top view of a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. For descriptive purposes, FIG5 also shows a bonding structure 252 for connecting semiconductor dies 210A and 210B to the interposer layer 220 depicted in FIG2. The arrangement of the bonding structures 252 shown in FIG5 is the same as that depicted in FIG4. Specifically, the bonding structure 252 includes a first bonding pattern 252A and a second bonding structure 252B arranged along the periphery of each die region RD, wherein the first bonding structure 252A is located between the die gap region RG and the die region RD. The metal layer M1 in the die gap region RG includes a first top layer pattern 266a and a second top layer pattern 266b arranged in the die gap region RG and extending in the X direction toward the die regions RD on opposite sides of the die gap region RG.

[0028] A first top layer pattern 266a is located on opposite sides of a second top layer pattern 266b in the X direction. Each first top layer pattern 266a extends and overlaps a grain region RD. Each first top layer pattern 266a includes an elongated portion P1 extending in the Y direction along the boundary between a grain gap region RG and a grain region RD, and a finger-like portion P2 connected to the elongated portion P1. The elongated portion P1 of each first top layer pattern 266a partially overlaps a grain region RD and is connected / overlapped with a first bonding structure 252A. The finger-like portion P2 of each first top layer pattern 266a extends from the elongated portion P1 toward another first top layer pattern 266a in the X direction. The finger-like portions P2 of the two first top layer patterns 266a may point to each other, but this disclosure is not limited thereto. The second top layer pattern 266b includes a widened portion P3 extending between the elongated portions P1 of the two first top layer patterns 266a, and a neck region P4 located between the finger-like portions P2 of the two first top layer patterns 266a. Each widened portion P3 is wider in the Y direction than the neck region P4 is in the Y direction. Furthermore, the second top layer pattern 266b may also include a peripheral portion P5 extending along the X-direction grain region RD to connect to the peripheral portion of the second bonding structure 252B.

[0029] FIG6 schematically illustrates a top view of a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. Furthermore, for descriptive purposes, FIG6 also shows a bonding structure 252 depicted in FIG2 for connecting semiconductor dies 210A and 210B to the interposer layer 220. The arrangement of the bonding structures 252 shown in FIG6 is the same as depicted in FIG4. Specifically, the bonding structure 252 includes a first bonding structure 252A and a second bonding structure 252B arranged along the periphery of each die region RD, wherein the first bonding structure 252A is located between the die gap region RG and the die region RD. In FIG6, the metal layer M1 in the die gap region RG includes a first top layer pattern 268a and a second top layer pattern 268b. The first top layer pattern 268a includes an elongated portion P6 and a connecting portion P7 extending continuously in the X direction between the elongated portions P6. Each elongated portion P6 extends along the boundary between the intergranular region RG and the corresponding grain region RD, and partially overlaps the corresponding grain region RD to connect the first bonding structure 252A. A second top layer pattern 268b is located on opposite sides of the connecting portion P7 of the first top layer pattern 268a in the Y direction. Each second top layer pattern 268b includes a blocky portion P8 located in the intergranular region RG, and a peripheral portion P9 extending in the X direction along the periphery of the grain region RD to connect the second bonding structure 252B.

[0030] FIG3 schematically illustrates a top view design embodiment of the bottom pattern 222B for implementing the gap conductive feature 222 in the metal layer Mx of the interposer 220 depicted in FIG2, and FIGS. 4 to 6 schematically illustrate various top view design embodiments of the top pattern 222A for implementing the gap conductive feature 222 in the metal layer M1 of the interposer 220 depicted in FIG2. In some embodiments, the intermediate pattern 222C arranged in the other metal layers M2...Mx-1 may be designed according to the pattern design of the top pattern 222A and the bottom pattern 222B to form a continuous electrical transport path, providing the first gap electrical transport path 122A and the second gap electrical transport path 122B depicted in FIG1. ​​In some embodiments, each gap electrical transport path 122 depicted in FIG1 may be implemented by the cross-sectional structure of the gap conductive feature 222 shown in FIG2. In some embodiments, the top layer pattern 222A of the first gap electrical transmission path 122A can be implemented by any of the first top layer patterns 264a, 266a, and 268a in Figures 4 to 6, and the top layer pattern 222A of the second gap electrical transmission path 122B can be implemented by any of the second top layer patterns 264b, 266b, and 268b in Figures 4 to 6. In some embodiments, the bottom layer pattern 222B of the first gap electrical transmission path 122A can be implemented by the first bottom layer pattern 262a in Figure 3, and the bottom layer pattern 222B of the second gap electrical transmission path 122B can be implemented by the second bottom layer pattern 262b in Figure 3.

[0031] FIG7 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. Electronic device 300 is similar to electronic device 200, but differs from electronic device 200 in the design of the interposer 320. Therefore, some elements indicated by the same reference numerals in FIG2 and FIG7 may be the same or equivalent elements, and the descriptions of these elements in different embodiments may be referred to mutually. Specifically, electronic device 300 includes semiconductor dies 210A and 210B, interposer 320, passive element 230, and package substrate 240, wherein interposer 320 includes a redistribution circuit structure RDL, substrate 302, substrate via 304, and embedded passive element 306. Embedded passive element 306 may be a decoupling capacitor, such as embedded deep trench capacitors (eDTCs). Here, the configuration, structure, material, function, or similar characteristics of semiconductor dies 210A and 210B, redistribution circuit structure RDL, passive element 230, and packaging substrate 240 can be referred to the description of the elements in Figure 2, and will not be repeated here.

[0032] In this embodiment, the redistribution circuit structure RDL is disposed on the side of the substrate 302 adjacent to the semiconductor dies 210A and 210B. In other words, the redistribution circuit structure RDL is located between the substrate 302 and the semiconductor dies 210A and 210B. The substrate via 304 passes through the substrate 302 in the thickness direction (Z direction) and is electrically connected to the redistribution circuit structure RDL. An embedded passive element 306 is disposed between the substrate 302 and the redistribution circuit structure RDL. The embedded passive element 306 may be partially embedded in the substrate 302 and / or partially embedded in an interconnect structure (not shown) disposed between the substrate 302 and the redistribution circuit structure RDL. The interposer 320 is bonded to the package substrate 240 through a bonding structure 254 located between the substrate 302 and the package substrate 240, and the substrate via 304 is electrically connected to the bonding structure 254. Passive component 230 is bonded to substrate 302 of interposer 320 via bonding structure 232 and is located between substrate 302 and package substrate 240. Semiconductor dies 210A and 210B are bonded to redistribution circuit structure RDL of interposer 320 via bonding structure 252. Through-hole 304 electrically connects redistribution circuit structure RDL to passive component 230 and package substrate 240.

[0033] In this embodiment, at least one substrate via 304 is located in the grain gap region RG, such as substrate via 304A. The substrate via 304A located in the grain gap region RG can form an electrical connection between the gap conductive feature 222 formed in the redistribution circuit structure RDL and the passive element 230. Furthermore, the substrate via 304A and the gap conductive feature 222 can form the gap electrical transmission path 122 depicted in FIG. 1. The substrate via 304A and the gap conductive feature 222 located in the grain gap region RG can form a short electrical transmission path between the passive element 230 and the semiconductor dies 210A and 210B, which helps to reduce transmission resistance and inductance, thereby ensuring the decoupling effect provided by the passive element 230. FIG. 7 shows one gap conductive feature 222 for illustrative purposes only, but the interposer layer 320 may include multiple gap conductive features 222 to transmit various signals. For example, at least one gap conductive feature 222 is configured to transmit power, and at least another gap conductive feature 222 is configured to be electrically grounded.

[0034] In this embodiment, the embedded passive element 306 is formed in a trench 302T of the substrate 302 and includes a first electrode layer MA, a second electrode layer MB, and a dielectric layer DL that isolates the first electrode layer MA from the second electrode layer MB. The first electrode layer MA, the dielectric layer DL, and the second electrode layer MB are sequentially disposed on the substrate 302 and extend conformally along the shape of the trench 302T. The embedded passive element 306 and the passive element 230 can provide similar functions, such as decoupling functions. The interposer layer 320 may include a plurality of embedded passive elements 306 and a plurality of conductive features 222, wherein one of the embedded passive elements 306 may be located in the inter-die region RG and electrically connected to the semiconductor dies 210A and 210B through an inter-die conductive feature 222, thereby shortening the electrical transport path between the embedded passive element 306 and the semiconductor dies 210A and 210B.

[0035] FIG8 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. The electronic device 400 shown in FIG8 is similar to the electronic device 300 shown in FIG7. Some elements indicated by the same reference numerals in FIG7 and FIG8 may be the same or equivalent elements, and the descriptions of these elements in different embodiments may be referred to each other. Electronic device 400 includes semiconductor dies 210A and 210B, an interposer 320, and a package substrate 240. In FIG8, the passive element 230 in FIG7 may be omitted. Similar to the embodiments described above, semiconductor dies 210A and 210B are laterally spaced from each other through die gap regions RG and are bonded to the interposer 320. The interposer 320 is bonded to the package substrate 240.

[0036] In this embodiment, the interposer 320 includes a redistribution circuit structure RDL, a substrate 302, a substrate via 304, and a plurality of embedded passive components 306. The redistribution circuit structure RDL disposed on the substrate 302 includes a dielectric structure DLS and metal layers M1...Mx embedded in the dielectric structure DLS to provide a gap electrical transport path in the die gap region RG. For example, the gap electrical transport path in the die gap region RG may perform a function similar to the gap electrical transport path 122 depicted in FIG1. ​​In some embodiments, the metal layers M1...Mx construct gap conductive features 222 in the die gap region RG to form a gap electrical transport path. Embedded passive components 306 are disposed between the substrate 302 and the redistribution circuit structure RDL. At least one embedded passive component, such as embedded passive component 306A, is electrically connected to semiconductor dies 210A and 210B via the gap electrical transport path formed by the gap conductive features 222.

[0037] In this embodiment, the gap conductive feature 222 includes a top pattern 222A in one of the metal layers, namely the metal layer M1 closest to the semiconductor grains 210A and 210B. The top pattern 222A extends laterally from the grain gap region RG toward the semiconductor grains 210A and 210B and partially overlaps the semiconductor grains 210A and 210B. The gap conductive feature 222 also includes a bottom pattern 222B in another metal layer, namely the metal layer Mx closest to the substrate 302, and an intermediate pattern 222C in an intermediate metal layer, namely the metal layers M2...Mx-1 between the metal layers M1 and Mx. The intermediate pattern 222C is arranged along the thickness direction Z between the top pattern 222A and the bottom pattern 222B. In this embodiment, the bottom pattern 222B can be connected to the embedded passive element 306A through a corresponding via.

[0038] Furthermore, the metal layers M1...Mx may further construct a lower conductive feature 224 in the grain region RD where one of the semiconductor dies 210A and 210B is located. The lower conductive feature 224 electrically connects at least one other embedded passive element (such as embedded passive element 306B) and one of the semiconductor dies (such as semiconductor die 210A). The lower conductive feature 224 in the grain region RD includes a top pattern 224A, a bottom pattern 224B, and an intermediate pattern 224C, which are similar to those depicted in FIG2. In this embodiment, the bottom pattern 224B is connected to the embedded passive element 306B through a corresponding via, and the bottom pattern 224B may extend laterally from the grain region RD to the inter-diet region RG to partially overlap the embedded passive element 306A.

[0039] In summary, the electronic device includes semiconductor dies bonded side-by-side on a first surface of an interposer, and passive elements bonded on a second surface of the interposer in inter-die-gap regions between the semiconductor dies. In this embodiment, the interposer provides an electrical transmission path between the passive elements and the semiconductor dies in the inter-die-gap regions. Therefore, the electrical transmission path between the passive elements and the semiconductor dies is shorter, which helps reduce transmission resistance and inductance, and ensures decoupling of the passive elements.

[0040] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of the disclosure. Based on the foregoing, this disclosure is intended to cover such modifications and variations, provided they fall within the scope of the following claims and their equivalents. [Simplified Explanation of the Diagram]

[0041] The accompanying drawings are included to provide a further understanding of the present disclosure and form part of this specification. These drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. FIG1 schematically illustrates a side view of an electronic device according to some embodiments of the present disclosure. FIG2 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG3 schematically illustrates a top view of a portion of the metal layer Mx of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. FIG4 schematically illustrates a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. FIG5 schematically illustrates a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. FIG6 schematically illustrates a portion of the metal layer M1 of the redistribution circuit structure in FIG2 according to some embodiments of the present disclosure. FIG7 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG8 schematically illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.

Claims

1. An electronic device comprising: Semiconductor grains are laterally spaced from each other by intergranular regions. An interposer layer, wherein the semiconductor die is bonded to a first surface of the interposer layer, wherein the interposer layer provides a gap electrical transport path in the die gap region, the gap electrical transport path extending from the first surface of the interposer layer to a second surface of the interposer layer, and the second surface is opposite to the first surface; And a passive element, bonded to the second surface of the interposer and located in the inter-die region, wherein the passive element is electrically connected to the semiconductor die via the inter-die electrical transport path.

2. The electronic device of claim 1, wherein the intermediate layer includes a redistribution circuit structure, and the redistribution circuit structure includes a dielectric structure and a metal layer, the metal layer being embedded in the dielectric structure.

3. The electronic device of claim 2, wherein the metal layer constructs gap conductive features in the grain gap region to form the gap electrical transport path.

4. The electronic device of claim 3, wherein the gap conductive feature includes a top layer pattern in one of the metal layers closest to the first surface, and the top layer pattern extends laterally from the grain gap region toward the semiconductor grain and partially overlaps the semiconductor grain.

5. The electronic device of claim 4, wherein the top layer pattern of the gap conductive feature is a block pattern in the grain gap region.

6. The electronic device of claim 4, wherein the gap conductive feature includes a bottom pattern in another metal layer closest to the second surface and an intermediate pattern in an intermediate metal layer between the one metal layer and the other metal layer, and the intermediate pattern is arranged in the thickness direction between the top pattern and the bottom pattern.

7. The electronic device as claimed in claim 6, wherein the underlying pattern and the intermediate pattern are located in the intergranular region.

8. The electronic device of claim 2, wherein the metal layer forms an underlying conductive feature in a grain region where one of the semiconductor grains is located, and the underlying conductive feature is electrically connected between the passive element and one of the semiconductor grains.

9. The electronic device of claim 8, wherein the underlying conductive feature in the grain region includes a bottom layer pattern in one of the metal layers closest to the second surface, and the bottom layer pattern extends laterally from the grain region toward the grain gap region and partially overlaps the passive element.

10. The electronic device of claim 2, wherein the interposer further comprises a substrate and a substrate via, the redistribution circuit structure being disposed on the substrate, the substrate via passing through the substrate in the thickness direction and being electrically connected to the redistribution circuit structure.

11. The electronic device of claim 10, wherein a via in the substrate located in the inter-diode region forms the inter-diode electrical transport path.

12. The electronic device of claim 10, wherein the interposer further comprises an embedded passive element disposed between the substrate and the redistribution circuit structure.

13. The electronic device of claim 12, wherein the interposer also provides an additional gap electrical transport path in the die gap region, and the embedded passive element is electrically connected to the semiconductor die through the additional gap electrical transport path.

14. The electronic device of claim 1, further comprising a packaging substrate, wherein the interposer is bonded to the packaging substrate, and the passive element is located between the interposer and the packaging substrate.

15. The electronic device of claim 1, wherein the interposer also provides a lateral signal transmission path electrically connected between the semiconductor dies.

16. The electronic device of claim 1, wherein the gap electrical transmission path is used to transmit power.

17. The electronic device as claimed in claim 1, wherein the gap electrical transmission path is configured to be electrically grounded.

18. The electronic device of claim 1 further includes a bonding structure for connecting each of the semiconductor die to the interposer layer.

19. The electronic device of claim 18, wherein the bonding structure comprises a first bonding structure and a second bonding structure arranged along the periphery of each of the semiconductor grains and electrically connected to the passive element.

20. The electronic device of claim 19, wherein the first bonding structure transmits power and the second bonding structure is electrically grounded.

21. An electronic device comprising: Semiconductor grains are laterally spaced from each other through grain gap regions; and an interposer layer to which the semiconductor die is bonded, wherein the interposer layer comprises: a substrate; a redistribution circuit structure disposed on the substrate and including a dielectric structure and a metal layer embedded in the dielectric structure to provide a gap electrical transport path in the die gap region; and a plurality of embedded passive elements disposed between the substrate and the redistribution circuit structure, wherein at least one of the embedded passive elements is electrically connected to the semiconductor die through the gap electrical transport path.

22. The electronic device of claim 21, wherein the metal layer constructs gap conductive features in the grain gap region to form the gap electrical transport path.

23. The electronic device of claim 22, wherein the gap conductive feature includes a top layer pattern in one of the metal layers closest to the semiconductor die, and the top layer pattern extends laterally from the die gap region toward the semiconductor die and partially overlaps the semiconductor die.

24. The electronic device of claim 23, wherein the gap conductive feature includes a bottom pattern in another metal layer closest to the substrate, and an intermediate pattern in an intermediate metal layer between the one metal layer and the other metal layer, wherein the intermediate pattern is arranged along the thickness direction between the top pattern and the bottom pattern.

25. The electronic device of claim 21, wherein the metal layer forms an underlying conductive feature in a grain region where one of the semiconductor grains is located, and the underlying conductive feature is electrically connected between at least one other embedded passive element and one of the semiconductor grains.

26. The electronic device of claim 25, wherein the underlying conductive feature in the grain region includes a bottom layer pattern in one of the metal layers closest to the substrate, and the bottom layer pattern extends laterally from the grain region to the grain gap region and partially overlaps the at least one embedded passive element.

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