Chip package and manufacturing method thereof

Abstract

A chip package includes a semiconductor substrate, a bonding adhesive, a support element, a first protection layer, and a second protection layer. The top surface of the semiconductor substrate has a conductive pad and a sensing area, and the corner of the top surface of the semiconductor substrate has a groove. The bonding adhesive is located in the groove. The support element covers the bonding adhesive and the conductive pad, and surrounds the sensing area. The first protection layer is located on the bottom surface of the semiconductor substrate. The second protection layer covers the first protection layer, the sidewall of the semiconductor substrate, and the lateral surface of the bonding adhesive.

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