Humidity sensing device

Abstract

A humidity sensing device is provided. The humidity sensing device includes a substrate, a humidity sensing element, a logic element, and an isolation element. The substrate includes a sensing area and a logic area adjacent to the sensing area. The humidity sensing element is disposed in the sensing area. The logic element is disposed in the logic area. The isolation element is disposed in the sensing area and located between the humidity sensing element and the logic element. Wherein, in a top view, the isolation element surrounds the humidity sensing element.

Description

[Technical Field]

[0001] This disclosure relates to a humidity sensing device, and more particularly to a humidity sensing device including an isolation element. [Previous Technology]

[0002] Humidity sensing devices are widely used because humidity needs to be controlled frequently in home, medical, transportation, and agricultural and livestock applications.

[0003] However, in humidity sensing devices, insufficient isolation between different components may lead to unnecessary flow of moisture at different components. This may degrade the accuracy of humidity sensing and / or damage the humidity sensing device. In addition, moisture can easily seep in at the connections used to transmit signals from the humidity sensing element. Furthermore, the resonance of the sensing electrodes may generate discrete charges, further degrading the accuracy of humidity sensing.

[0004] Therefore, although existing humidity sensing devices have gradually met their intended uses, they are not yet completely satisfactory in all aspects. Thus, there are still some problems to be overcome regarding humidity sensing devices. [Summary of the Invention]

[0005] The humidity sensing device disclosed herein may include an isolation element disposed between a humidity sensing element and a logic element to improve isolation. For example, the isolation element can prevent unnecessary flow of moisture in the logic element and moisture in the humidity sensing element. Accordingly, the accuracy and / or reliability of humidity sensing can be improved. In some embodiments, the potential of the isolation element may be 0. Therefore, the isolation element can discharge discrete charges generated by the resonance of the sensing electrode from the humidity sensing device. Accordingly, the discrete charges can be prevented from interfering with the accuracy of humidity sensing. In some embodiments, the isolation element may include a plurality of isolation strips, and the isolation strips may be staggered to further improve isolation.

[0006] In some embodiments, this disclosure provides a humidity sensing device. The humidity sensing device includes a substrate, a humidity sensing element, a logic element, and an isolation element. The substrate includes a sensing area and a logic area adjacent to the sensing area. The humidity sensing element is disposed in the sensing area. The logic element is disposed in the logic area. The isolation element is disposed in the sensing area and located between the humidity sensing element and the logic element. In a top view, the isolation element surrounds the humidity sensing element.

[0007] The humidity sensing device disclosed herein can be applied to various types of sensing devices. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings.

Implementation Method

[0008] The humidity sensing device of various embodiments of this disclosure will be described in detail below. It should be understood that the following description provides many different embodiments for implementing some embodiments of this disclosure in different ways. The specific elements and arrangements described below are only for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not for limiting this disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements in order to clearly describe this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any relationship between the different embodiments and / or structures discussed.

[0009] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element of the diagram to another. It is understood that if the arrangement of the diagrams is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0010] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include a situation where the first material layer and the second material layer are in direct contact, or a situation where the first material layer and the second material layer are not in direct contact, that is, a situation where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0011] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that (or those) element, nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0012] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms may also include situations where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0013] In this text, the terms "approximately," "about," and "substantially" generally indicate a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The terms "range between the first value and the second value" or "first value ~ second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first value and the second value within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0014] Certain terms are used throughout this disclosure and in the claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Therefore, when the terms "comprise" and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, for example, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and shall not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0016] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness / height direction). In some embodiments, the cross-sectional view described herein is a schematic diagram for viewing the XY plane, and the top view described herein is a schematic diagram for viewing the XY plane. In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0017] Referring to Figure 1, which is a top view of a humidity sensing device 1 according to an embodiment of the present disclosure. As shown in Figure 1, in some embodiments, the humidity sensing device 1 may include a substrate 100, a humidity sensing element 10, a logic element 20, and an isolation element 30, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may include a sensing area SA and a logic area LA, and the sensing area SA may be adjacent to the logic area LA. In some embodiments, the logic area LA may be disposed on at least one side of the sensing area SA. In some embodiments, the humidity sensing element 10 may be used to sense humidity and may be disposed in the sensing area SA of the substrate 100. In some embodiments, the logic element 20 may be used to control the humidity sensing element 10 and may be disposed in the logic area LA of the substrate 100. In some embodiments, the isolation element 30 may be disposed in the sensing area SA of the substrate 100 and located between the humidity sensing element 10 and the logic element 20.

[0018] As shown in Figure 1, in some embodiments, in a top view, the isolation element 30 may surround the humidity sensing element 10 to provide a moisture isolation effect. Accordingly, the isolation element 30 can prevent moisture in the logic element 20 from flowing into the humidity sensing element 10. Therefore, the accuracy and / or reliability of humidity sensing of the humidity sensing device 1 can be improved. In some embodiments, in a top view, the isolation element 30 may be disposed on at least three sides of the humidity sensing element 10. In some embodiments, in a top view, the isolation element 30 may be disposed on all sides of the humidity sensing element 10. In some embodiments, in a top view, the isolation element 30 may expose at least a portion of one side of the humidity sensing element 10 to electrically connect the humidity sensing element 10 to the logic element 20 at the exposed portion. Accordingly, the isolation element 30 can improve the isolation for each side of the humidity sensing element 10.

[0019] As shown in Figure 1, in some embodiments, the isolation element 30 may be grounded. Therefore, the potential of the isolation element 30 may be 0, or the potential of the isolation element 30 may be the minimum potential in the humidity sensing device 1. The isolation element 30 can drain and remove stray charges generated by the resonance of the sensing electrode to avoid discrete charges interfering with the accuracy of humidity sensing, thereby reducing sensing error, improving the signal-to-noise ratio, and / or improving sensing sensitivity.

[0020] As shown in Figure 1, in some embodiments, the humidity sensing element 10 may include a sensing electrode 712, and the signal sensed by the sensing electrode 712 may be transmitted sequentially to the logic element 20 via a third signal portion 512, a second signal portion 312, and a first signal portion 152. Accordingly, the signal transmission path of the humidity sensing element 10 can be adjusted so that the signal connection is located in a dense dielectric layer, thereby reducing the risk of moisture infiltration due to insufficient density of the dielectric layer. For example, the first signal portion 152 may be disposed in a dense dielectric layer (e.g., the first dielectric layer 200) to prevent moisture from seeping in from the adjacent first signal portion 152. In other words, when the first signal portion 152 and the first isolation portion (e.g., the first isolation portion 156) in the isolation element 30 are disposed in the same layer, the first signal portion 152 may be located in the first dielectric layer 200 to adjust the signal transmission path.

[0021] Referring to Figure 2, which is a schematic cross-sectional view of a humidity sensing device 1 according to an embodiment of the present disclosure. As shown in Figure 2, in some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or an on-insulator semiconductor (SOI) substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate. In some embodiments, the substrate 100 may include elemental semiconductors, including silicon, germanium, the like or combinations thereof; the substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like or combinations thereof; the substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like or combinations thereof, but the present disclosure is not limited thereto. For example, the substrate 100 may be a silicon wafer.

[0022] In some embodiments, the conductivity type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, doping depth, and size of the doped region can also be adjusted according to electrical requirements. In some embodiments, the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For ease of explanation, in the following text, the first conductivity type can be P-type, and the second conductivity type can be N-type, but this disclosure is not limited thereto. In some embodiments, the substrate 100 may have a first conductivity type, i.e., P-type.

[0023] As shown in Figure 2, in some embodiments, a first well region 110 and a second well region 120 may be formed in the substrate 100 by performing an implantation process. In some embodiments, the first well region 110 and the second well region 120 are separated from each other, the first well region 110 may have a first conductivity type (P-type), and the second well region 120 may have a second conductivity type (N-type).

[0024] As shown in Figure 2, in some embodiments, insulating layers 130, 132 may be formed on substrate 100 by performing a heat treatment process. In some embodiments, insulating layers 130, 132 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, or combinations thereof, but this disclosure is not limited thereto. For example, insulating layer 130 may include field oxide.

[0025] As shown in Figure 2, in some embodiments, a gate dielectric layer 140 may be formed on the first well region 110 and the second well region 120. In some embodiments, the gate dielectric layer 140 may be formed by a deposition process such as chemical vapor deposition (CVD). In some embodiments, the gate dielectric layer 140 may include a dielectric material with a high dielectric constant.

[0026] As shown in Figure 2, in some embodiments, a conductive layer 150 may be compliantly formed on the gate dielectric layer 140 and the isolation layers 130, 132. In some embodiments, the conductive layer 150 may serve as a zero metal layer (MO). In some embodiments, the conductive layer 150 may be formed by a deposition process, a sputtering process, an electron beam evaporation process, a resistance heating evaporation process, similar processes, or combinations thereof. In some embodiments, the conductive layer 150 may include a conductive material. In some embodiments, the conductive material may include amorphous silicon, polysilicon, metals, alloys, conductive metal nitrides, conductive metal oxides, conductive polymers, the like, or combinations thereof, but this disclosure is not limited thereto. Metals may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), their analogues, or combinations thereof, but this disclosure is not limited thereto. Conductive metal nitrides may include TiN, TaN, MoN, WN, their analogues, or combinations thereof. Conductive metal oxides may include indium tin oxide (ITO), indium zinc oxide (IZO), their analogues, or combinations thereof. Conductive polymers may include polyaniline, polypyrrole, polythiophene, their analogues, or copolymers thereof, but this disclosure is not limited thereto. For example, the conductive material may be polycrystalline silicon.

[0027] As shown in Figure 2, in some embodiments, after compliantly forming the conductive layer 150, a patterning process may be performed to form a patterned conductive layer 150. In some embodiments, the patterned conductive layer 150 may include a first signal portion 152, a gate electrode 154, and a first isolation portion 156 that are physically separated from each other. In other words, the first signal portion 152, the gate electrode 154, and the first isolation portion 156 may be formed in the same process, may be disposed on the same layer, and may include the same conductive material, but this disclosure is not limited thereto. In other embodiments, the first signal portion 152, the gate electrode 154, and the first isolation portion 156 may be formed in different processes and may include different conductive materials. In some embodiments, the first signal portion 152 and the first isolation portion 156 may be disposed in a sensing region SA, and the gate electrode 154 may be disposed in a logic region LA. In some embodiments, the first signal portion 152 may be disposed on the isolation layer 132, the gate electrode 154 may be disposed on the gate dielectric layer 140, and the first isolation portion 156 may be disposed on the isolation layer 130. In some embodiments, the first isolation portion 156 may surround the first signal portion 152.

[0028] As shown in Figure 2, in some embodiments, gate spacer 160 may be formed on opposite sides of gate electrode 154 by a deposition process. In some embodiments, gate spacer 160 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, gate spacer 160 may include a single-layer or multi-layer structure.

[0029] As shown in Figure 2, in some embodiments, doped regions 170 and 180 can be formed by performing an implantation process. In some embodiments, doped region 170 may have a second conductivity type (N-type), and doped region 170 may be disposed in a first well region 110. In some embodiments, doped region 180 may have a first conductivity type (P-type), and doped region 180 may be disposed in a second well region 120. In some embodiments, the doping concentration of doped region 170 may be greater than the doping concentration of second well region 120, and the doping concentration of doped region 180 may be greater than the doping concentration of first well region 110.

[0030] As shown in Figure 2, in some embodiments, the first dielectric layer 200 may be formed on the conductive layer 150 in a blanket manner. In some embodiments, the first dielectric layer 200 may be disposed on the first signal portion 152, the gate electrode 154, and the first isolation portion 156, and may cover the top and side surfaces of the first signal portion 152, the gate electrode 154, and the first isolation portion 156. In some embodiments, the first dielectric layer 200 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the first dielectric layer 200 may be an oxide such as silicon oxide. In some embodiments, the first dielectric layer 200 may be silicon oxide formed using tetraethoxysilane (TEOS) as a precursor, or may be boro-phospho-silicate glass (BPSG). In some embodiments, the density of the first dielectric layer 200 is greater than the density of other dielectric layers subsequently formed on the first dielectric layer 200. For example, density may include density, structural strength, other suitable properties, or a combination thereof.

[0031] As shown in Figure 2, in some embodiments, first vias 212, 214, and 216 may be formed in the first dielectric layer 200, and the first vias 212, 214, and 216 may penetrate the first dielectric layer 200. In some embodiments, the first vias 212, 214, and 216 may include conductive material. In some embodiments, the first via 212 may be connected to the first signal portion 152, the first via 214 may be connected to the doped regions 170 and 180, and the first via 216 may be connected to the first isolation portion 156.

[0032] As shown in Figure 2, in some embodiments, a first metal layer 300 may be compliantly formed on the first dielectric layer 200. In some embodiments, the first metal layer 300 may serve as a first metal layer (M1). In some embodiments, the first metal layer 300 may be formed by a deposition process, a sputtering process, an electron beam evaporation process, a resistance heating evaporation process, a similar process, or a combination thereof. In some embodiments, the first metal layer 300 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof, but this disclosure is not limited thereto.

[0033] As shown in Figure 2, in some embodiments, the first metal layer 300 may include a second signal portion 312, an interconnect 314, a second isolation portion 316, and a blocking portion 318 that are physically separated from each other. In other words, the second signal portion 312, the interconnect 314, the second isolation portion 316, and the blocking portion 318 may be formed in the same process, may be disposed on the same layer, and may include the same material, but this disclosure is not limited thereto. In other embodiments, the second signal portion 312, the interconnect 314, the second isolation portion 316, and the blocking portion 318 may be formed in different processes and may include different materials. In some embodiments, the second signal portion 312, the second isolation portion 316, and the blocking portion 318 may be disposed in the sensing area SA, and the interconnect 314 may be disposed in the logic area LA. In some embodiments, the first signal portion 152 and the second signal portion 312 may be connected via a first via 212. In some embodiments, the doped regions 170 and 180 and the interconnect 314 can be connected via the first via 214. In some embodiments, the first isolation portion 156 and the second isolation portion 316 can be connected via the first via 216. In some embodiments, the second isolation portion 316 may surround the second signal portion 312 and the blocking portion 318. In some embodiments, the blocking portion 318 is electrically isolated from the second signal portion 312 and the second isolation portion 316.

[0034] As shown in Figure 2, in some embodiments, since the blocking portion 318 may be floating and may include conductive material, the blocking portion 318 may serve as a waterproof layer and / or etching stop layer in the vertical direction (i.e., the third direction D3) of the humidity sensing device 1 to improve the reliability of the humidity sensing device 1. Specifically, since the blocking portion 318 may be disposed below the subsequently formed sensing electrode, it can prevent moisture from below from interfering with the sensing electrode. Furthermore, the blocking portion 318 can also prevent over-etching of the dielectric layer subsequently formed on the blocking portion 318.

[0035] As shown in Figure 2, in some embodiments, the second dielectric layer 400 may be formed on the first metal layer 300 in a blanket manner. In some embodiments, the material of the second dielectric layer 400 may be the same as or different from the material of the first dielectric layer 200. In some embodiments, the second dielectric layer 400 may be an oxide such as silicon oxide. In some embodiments, the second dielectric layer 400 may be silicon oxide formed by a chemical vapor deposition (CVD) process. In some embodiments, both the first dielectric layer 200 and the second dielectric layer 400 may be silicon oxide, and the density of the first dielectric layer 200 may be greater than that of the second dielectric layer 400 depending on the formation method or dopants.

[0036] In some embodiments, second vias 412, 414, and 416 may be formed in the second dielectric layer 400, and the second vias 412, 414, and 416 may penetrate the second dielectric layer 400. In some embodiments, the second vias 412, 414, and 416 may include a conductive material. In some embodiments, the second via 412 may connect to the second signal portion 312, the second via 414 may connect to the interconnect 314, and the second via 416 may connect to the second isolation portion 316.

[0037] As shown in Figure 2, in some embodiments, a second metal layer 500 may be compliantly formed on the second dielectric layer 400. In some embodiments, the material and formation method of the second metal layer 500 may be the same as or different from the material and formation method of the first metal layer 300. In some embodiments, the second metal layer 500 may serve as a second metal layer (M2). In some embodiments, the second metal layer 500 and the blocking portion 318 of the first metal layer 300 do not overlap in the normal direction of the substrate 100. In some embodiments, the projection range of the second metal layer 500 onto the substrate 100 is separate from the projection range of the blocking portion 318 of the first metal layer 300 onto the substrate 100.

[0038] As shown in Figure 2, in some embodiments, the second metal layer 500 may include a third signal portion 512, an interconnect 514, and a third isolation portion 516 that are physically separated from each other. In other words, the third signal portion 512, the interconnect 514, and the third isolation portion 516 may be formed in the same process, may be disposed on the same layer, and may include the same material, but this disclosure is not limited thereto. In some embodiments, the third signal portion 512 and the third isolation portion 516 may be disposed in a sensing area SA, and the interconnect 514 may be disposed in a logic area LA. In some embodiments, the second signal portion 312 and the third signal portion 512 may be connected via a second via 412. In some embodiments, the interconnect 314 and the interconnect 514 may be connected via a second via 414. In some embodiments, the second isolation portion 316 and the third isolation portion 516 may be connected via a second via 416. In some embodiments, the third isolation portion 516 may surround the third signal portion 512.

[0039] As shown in Figure 2, in some embodiments, a third dielectric layer 600 may be formed on the second metal layer 500 in a blanket manner. In some embodiments, the material of the third dielectric layer 600 may be the same as or different from the material of the first dielectric layer 200. In some embodiments, the third dielectric layer 600 may be an oxide such as silicon oxide. In some embodiments, the third dielectric layer 600 may be silicon oxide formed by a chemical vapor deposition (CVD) process. In some embodiments, the density of the first dielectric layer 200 may be greater than the density of the second dielectric layer 400 and the third dielectric layer 600.

[0040] In some embodiments, third vias 612, 614, and 616 may be formed in the third dielectric layer 600, and the third vias 612, 614, and 616 may penetrate the third dielectric layer 600. In some embodiments, the third vias 612, 614, and 616 may include a conductive material. In some embodiments, the third via 612 may connect to the third signal portion 512, the third via 614 may connect to the interconnect 514, and the third via 616 may connect to the third isolation portion 516.

[0041] As shown in Figure 2, in some embodiments, a third metal layer 700 may be compliantly formed on the third dielectric layer 600. In some embodiments, the material and formation method of the third metal layer 700 may be the same as or different from the material and formation method of the first metal layer 300. In some embodiments, the third metal layer 700 may serve as a third metal layer (M3).

[0042] As shown in Figure 2, in some embodiments, the third metal layer 700 may include a sensing electrode 712, an interconnect 714, and a fourth isolation portion 716 that are separated from each other. In other words, the sensing electrode 712, the interconnect 714, and the fourth isolation portion 716 may be formed in the same process, may be disposed on the same layer, and may include the same material, but this disclosure is not limited thereto. In some embodiments, the sensing electrode 712 and the fourth isolation portion 716 may be disposed in the sensing region SA, and the interconnect 714 may be disposed in the logic region LA. In some embodiments, the sensing electrode 712 may be disposed on the second signal portion 312 and the blocking portion 318, so as to isolate the sensing electrode 712 from interference by moisture from below through the blocking portion 318.

[0043] As shown in Figure 2, in some embodiments, the third signal portion 512 and the sensing electrode 712 can be connected via the third via 612. In some embodiments, the interconnect 514 and the interconnect 714 can be connected via the third via 614. In some embodiments, the third isolation portion 516 and the fourth isolation portion 716 can be connected via the third via 616. In some embodiments, the fourth isolation portion 716 may surround the sensing electrode 712.

[0044] As shown in Figure 2, in some embodiments, a plurality of trenches 720 may be formed in the sensing area SA. In some embodiments, a portion of the third dielectric layer 600 and the second dielectric layer 400 may be removed to form the trenches 720. In some embodiments, a capping layer 800 may be compliantly formed on the third metal layer 700 and in the trenches 720. In some embodiments, the material of the capping layer 800 may be the same as or different from the material of the first dielectric layer 200. In some embodiments, the capping layer 800 may include a moisture barrier material to prevent unnecessary flow of moisture. For example, the capping layer 800 may include silicon nitride with a density greater than silicon oxide or other suitable moisture barrier materials. Accordingly, the capping layer 800 can prevent the moisture to be detected from penetrating into the logic element 20 during humidity sensing, causing oxidation or degradation of the logic element 20. Furthermore, the cover layer 800 prevents moisture from the components below it from diffusing onto the cover layer 800, thus avoiding interference with the sensing results of the sensing material layer subsequently formed on the cover layer 800. Therefore, the cover layer 800 can reduce sensing errors, improve the signal-to-noise ratio, and / or increase sensing sensitivity. Moreover, the cover layer 800 can be combined with a blocking portion 318 disposed below the second dielectric layer 400 to further prevent vertical moisture (from above and below) from affecting the sensing results.

[0045] As shown in Figure 2, in some embodiments, a sensing material layer 900 may be formed on a cover layer 800 in a blanket manner to obtain a humidity sensing device 1. In some embodiments, the cover layer 800 may be disposed between the sensing electrode 712 and the sensing material layer 900. In some embodiments, the sensing material layer 900 may have a protrusion 902 extending toward the substrate 100. In some embodiments, the shape of the protrusion 902 of the sensing material layer 900 may correspond to the shape of the trench 720. In some embodiments, the top width of the protrusion 902 of the sensing material layer 900 is greater than the bottom width of the protrusion 902 of the sensing material layer 900. In some embodiments, the protrusion 902 of the sensing material layer 900 may have an inverted trapezoidal shape.

[0046] In some embodiments, the sensing material layer 900 may include a water-absorbing and swelling material. The degree of swelling of the water-absorbing and swelling material varies linearly with the degree of water absorption, allowing humidity to be measured based on this linear change. In some embodiments, the sensing material layer 900 may have a water absorption swelling rate greater than 0% and less than or equal to 20%. In some embodiments, the water absorption swelling rate of the sensing material layer 900 may be 1%, 5%, 10%, 15%, 20%, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. In some embodiments, the water absorption swelling rate refers to the volume change of the material of the sensing material layer 900 before and after water absorption. In some embodiments, the sensing material layer 900 may include a photosensitive material to facilitate a patterning process to form the sensing area SA and the logic area LA in the humidity sensing device 1. The area where the sensing material layer 900 is disposed may be defined as the sensing area SA, and the area where the sensing material layer 900 is not disposed may be defined as the logic area LA. In some embodiments, the sensing material layer 900 may include photosensitive polyimide, benzocyclobutene, sodium polystyrenesulfonate, poly(methyl methacrylate), cellulose acetate-butyrate, analogues thereof, or combinations thereof, but this disclosure is not limited thereto.

[0047] Referring to Figure 1, in some embodiments, in a top view, the projection range of the sensing material layer 900 onto the substrate 100 may be located within the projection range of the first metal layer 300 onto the substrate 100. In some embodiments, in a top view, the sensing electrode 712 may include a first electrode 712a and a second electrode 712b. In some embodiments, one of the first electrode 712a and the second electrode 712b may be a positive electrode, and the other of the first electrode 712a and the second electrode 712b may be a negative electrode. In some embodiments, the shape of the first electrode 712a may correspond to the shape of the second electrode 712b. In some embodiments, the first electrode 712a and the second electrode 712b may each be a comb-shaped electrode, and the comb portion in the comb-shaped electrode may be correspondingly provided, but this disclosure is not limited thereto. In other embodiments, the first electrode 712a and the second electrode 712b may each be a linear electrode, an arc-shaped electrode, or an electrode with other suitable shapes.

[0048] As shown in Figures 1 and 2, in some embodiments, the humidity sensing element 10 may include a first signal portion 152, a second signal portion 312, a third signal portion 512, and a sensing electrode 712 connected to each other. In some embodiments, the logic element 20 may include a gate electrode 154, an interconnect 314, an interconnect 514, and an interconnect 714 connected to each other. In some embodiments, the logic element 20 may include a complementary metal oxide semiconductor (CMOS). In some embodiments, the isolation element 30 may include a first isolation portion 156, a second isolation portion 316, a third isolation portion 516, and a fourth isolation portion 716 connected to each other. Accordingly, the isolation element 30 can prevent unnecessary flow of moisture in the logic element 20 and moisture in the humidity sensing element 10.

[0049] In the following text, the same or similar component symbols and descriptions are omitted.

[0050] Referring to Figure 3, which is a cross-sectional schematic diagram of a humidity sensing device 2 according to an embodiment of the present disclosure. As shown in Figure 3, in some embodiments, the first via 216 may include a plurality of first isolation strips. In some embodiments, the number of first isolation strips may be N1, and N1 may be a positive integer greater than or equal to 2 and less than or equal to 20. In some embodiments, the first dielectric layer 200 may be located between two adjacent first isolation strips among the plurality of first isolation strips. In some embodiments, the first via 216 may include three first isolation strips 216a to 216c, but the present disclosure is not limited thereto. In some embodiments, the first dielectric layer 200 may be located between first isolation strips 216a and 216b, and between first isolation strips 216b and 216c. Accordingly, the plurality of first isolation strips may form a multilayer waterproof structure in the first dielectric layer 200 to improve the isolation between the humidity sensing element 10 and the logic element 20.

[0051] As shown in Figure 3, in some embodiments, the second via 416 may include a plurality of second isolation strips. In some embodiments, the number of second isolation strips may be N2, and N2 may be a positive integer greater than or equal to 2 and less than or equal to 20. In some embodiments, the second isolation portion 316 may be located between a plurality of first isolation strips and a plurality of second isolation strips. In some embodiments, N1 and N2 may be the same or different. In some embodiments, N1 may be greater than N2. In some embodiments, the second dielectric layer 400 may be located between two adjacent second isolation strips among the plurality of second isolation strips. In some embodiments, the second via 416 may include two second isolation strips 416a and 416b, but this disclosure is not limited thereto. In some embodiments, the second dielectric layer 400 may be located between second isolation strips 416a and second isolation strips 416b. Accordingly, the plurality of second isolation strips may form a multilayer waterproof structure in the second dielectric layer 400 to improve the isolation between the humidity sensing element 10 and the logic element 20.

[0052] As shown in Figure 3, in some embodiments, each of the plurality of first isolation strips 216a-216c does not overlap with each of the plurality of second isolation strips 416a, 416b in the normal direction of the substrate 100. In some embodiments, the projection range of the plurality of first isolation strips 216a-216c onto the substrate 100 is separate from the projection range of the plurality of second isolation strips 416a, 416b onto the substrate 100. Accordingly, by staggering the isolation strips in different layers, the isolation between the humidity sensing element 10 and the logic element 20 can be further improved.

[0053] As shown in Figure 3, in some embodiments, the third via 616 may include a plurality of third isolation strips. In some embodiments, the number of third isolation strips may be N3, and N3 may be a positive integer greater than or equal to 2 and less than or equal to 20. In some embodiments, the third isolation portion 516 may be located between a plurality of second isolation strips and a plurality of third isolation strips. In some embodiments, N2 and N3 may be the same or different. In some embodiments, N3 may be greater than N2. In some embodiments, the third dielectric layer 600 may be located between two adjacent third isolation strips among the plurality of third isolation strips. In some embodiments, the third via 616 may include three third isolation strips 616a to 616c, but this disclosure is not limited thereto. In some embodiments, the third dielectric layer 600 may be located between third isolation strips 616a and 616b, and between third isolation strips 616b and 616c. Accordingly, a plurality of third isolation strips can form a multi-layer waterproof structure in the third dielectric layer 600 to improve the isolation between the humidity sensing element 10 and the logic element 20.

[0054] As shown in Figure 3, in some embodiments, each of the plurality of third isolation strips 616a-616c does not overlap with each of the plurality of second isolation strips 416a, 416b in the normal direction of the substrate 100. In some embodiments, the projection range of the plurality of third isolation strips 616a-616c onto the substrate 100 is separate from the projection range of the plurality of second isolation strips 416a, 416b onto the substrate 100. Accordingly, by staggering the isolation strips in different layers, the isolation between the humidity sensing element 10 and the logic element 20 can be further improved.

[0055] Referring to Figures 4 and 5, which are respectively a perspective view and a top view of the isolation element 30 of a humidity sensing device 2 according to an embodiment of the present disclosure. As shown in Figure 4, in some embodiments, the isolation element 30 may have a tower-like structure. As shown in Figure 5, in some embodiments, a plurality of first isolation strips 216a-216c may be disposed in a first dielectric layer 200. In some embodiments, the first dielectric layer 200 may be located between the two ends of each first isolation strip. For example, the first dielectric layer 200 may be located between one end of the first isolation strip 216a and the other end of the first isolation strip 216a. That is, the first isolation strip 216a does not completely surround the humidity sensing element. In some embodiments, the first signal portion 152 may extend through the first dielectric layer 200 to transmit the signal sensed by the sensing electrode to a logic element.

[0056] In some embodiments, the humidity sensing device 1 may be suitable for home applications such as dehumidifiers and moisture-proof boxes; medical applications such as ear thermometers; transportation applications such as food storage and transportation; agricultural applications such as hygrometers; and automotive applications such as defogging devices.

[0057] Accordingly, the humidity sensing device disclosed herein may include an isolation element to improve the isolation between the humidity sensing element and the logic element. For example, the isolation element may serve as a waterproof ring to prevent unnecessary flow of moisture in the logic element to the humidity sensing element. This improves the accuracy and / or reliability of humidity sensing. For example, the isolation element may surround the humidity sensing element to improve isolation on each side of the humidity sensing element. For example, a plurality of isolation strips may be included to provide a multi-layer waterproof structure. For example, staggered isolation strips may be included to provide different waterproof structures for different locations. For example, the isolation element may be formed simultaneously with the humidity sensing element and the logic element, such that the isolation element can be formed of a conductive material. That is, the isolation element disclosed herein can be formed by simply adjusting the mask pattern, thus the humidity sensing device disclosed herein has good process compatibility. For example, the isolation element may be grounded (potential may be 0). Therefore, discrete charges generated by the resonance of the sensing electrode can be discharged by the isolation element to avoid interference of discrete charges with the accuracy of humidity sensing.

[0058] Furthermore, the first signal portion in the humidity sensing element and the first isolation portion of the isolation element can be disposed in the same layer, thus allowing adjustment of the signal transmission path (i.e., the wire path) to prevent moisture from seeping in from adjacent signal portions. Specifically, since the first signal portion can be located in the first dielectric layer, and the first dielectric layer is denser than the second and third dielectric layers, moisture is less likely to seep in through the first dielectric layer. Additionally, the humidity sensing element may include a blocking portion in the first metal layer, and the blocking portion can serve as a vertical waterproof layer and / or an etching stop layer to improve the reliability of the humidity sensing device.

[0059] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it. The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps in the specific embodiments described in the specification. Anyone skilled in the art can understand from the content of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, and any substantially the same functions or results can be implemented in the embodiments described herein and used according to this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0060] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0061] This disclosure can be more fully understood from the following detailed description when read in conjunction with the drawings. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced. Figures 1 and 2 are respectively a top view and a cross-sectional view of a humidity sensing device according to an embodiment of this disclosure. Figure 3 is a cross-sectional view of a humidity sensing device according to an embodiment of this disclosure. Figure 4 is a perspective view of an isolation element of a humidity sensing device according to an embodiment of this disclosure. Figure 5 is a top view of an isolation element of a humidity sensing device according to an embodiment of this disclosure.

Claims

1. A humidity sensing device, comprising: A substrate includes a sensing area and a logic area adjacent to the sensing area; a humidity sensing element is disposed in the sensing area; A logic element is disposed in the logic area; an isolation element is disposed in the sensing area and located between the humidity sensing element and the logic element, wherein, in a top view, the isolation element surrounds the humidity sensing element, wherein the humidity sensing element includes a first signal portion, the logic element includes a gate electrode, the isolation element includes a first isolation portion, and the first signal portion, the gate electrode and the first isolation portion are disposed on the same layer.

2. The humidity sensing device as claimed in claim 1, wherein the potential of the isolation element is 0.

3. The humidity sensing device as claimed in claim 1, further comprising: A first dielectric layer is disposed on the first signal portion, the gate electrode, and the first isolation portion; A first metal layer is disposed on the first dielectric layer and includes a second signal portion and a second isolation portion that are separated from each other. The humidity sensing element includes the second signal portion and the second signal portion is connected to the first signal portion. The isolation element includes the second isolation portion and the second isolation portion is connected to the first isolation portion.

4. The humidity sensing device as claimed in claim 3, wherein the isolation element further includes a first guide hole connecting the first isolation portion and the second isolation portion.

5. The humidity sensing device as claimed in claim 4, wherein the first guide hole further comprises: A plurality of first isolation strips, wherein the first dielectric layer is located between two adjacent first isolation strips in the plurality of first isolation strips.

6. The humidity sensing device as claimed in claim 5, wherein the isolation element further comprises: A plurality of second isolation strips, wherein the second isolation portion is located between the plurality of first isolation strips and the plurality of second isolation strips, and the plurality of first isolation strips and the plurality of second isolation strips do not overlap in a normal direction of the substrate.

7. The humidity sensing device as claimed in claim 3, wherein the first metal layer further comprises: A blocking portion is separated from the second signal portion and the second isolation portion, and the second isolation portion surrounds the second signal portion and the blocking portion.

8. The humidity sensing device as claimed in claim 7, further comprising: A second dielectric layer is disposed on the first metal layer; A second metal layer is disposed on the second dielectric layer, wherein the second metal layer does not overlap with the blocking portion of the first metal layer in a normal direction of the substrate.

9. The humidity sensing device as claimed in claim 8, further comprising: A third dielectric layer is disposed on the second metal layer; A third metal layer is disposed on the third dielectric layer, including a sensing electrode; A sensing material layer is disposed on the sensing electrode, wherein the sensing electrode is disposed on the second signal portion and the blocking portion.

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