Adder tree device, multiply-accumulate circuit and operating method of the same

Abstract

Full adder tree devices, circuits, and an operating method of the same are disclosed. In one aspect, an adder tree device can include a first adder circuit configured to receive a first operand and a second operand as input and generate a negative sum value, wherein the negative sum value is a logical inversion of a sum of the first operand and the second operand. The adder tree device can further include a second adder circuit configured to receive the negative sum value and an additional operand as input and generate a positive sum value as output. The positive sum value can be equal to the sum of the first operand and the second operand plus a logical inversion of the additional operand.

Description

[Technical Field]

[0001] This disclosure document relates to adder tree devices, multiply-accumulate circuits and their operation methods. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integrated density is mainly due to the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. [Summary of the Invention]

[0003] This disclosure provides an adder tree apparatus. The adder tree apparatus includes a first adder circuit and a second adder circuit. The first adder circuit receives a first operand and a second operand as inputs to the first adder circuit and generates a negative sum value, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand. The second adder circuit receives the first negative sum value and an additional operand as inputs to the second adder circuit and generates a positive sum value as outputs to the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0004] This disclosure provides a multiplication-accumulation circuit. The multiplication-accumulation circuit includes a multiplier circuit and an adder tree circuit. The multiplier circuit is used to generate multiple partial products. The adder tree circuit is used to receive the multiple partial products, generate an intermediate sum corresponding to a first corresponding sum of at least two of the multiple partial products after logical inversion, and generate an output sum based on the intermediate sum and a second operand. The output sum corresponds to a second corresponding sum of the intermediate sum and the second operand after logical inversion.

[0005] This disclosure provides an operation method for a multiply-accumulate circuit. The operation method of the multiply-accumulate circuit includes the following steps: receiving a first operand and a second operand as inputs to a first adder circuit of an adder tree circuit; generating a negative sum value by the first adder circuit, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand; receiving the negative sum value and a second value as inputs to a second adder circuit of the adder tree circuit; and generating a positive sum value as the output of the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the second value.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatially relative terms (such as "below," "under," "below," "above," "top," "bottom," and similar) may be used herein to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein may be interpreted similarly.

[0008] Digital compute-in-memory (DCIM) circuits reduce memory activity and improve the efficiency of various operations (such as matrix-matrix operations) by performing operations within or near memory elements. An example of an operation that can be performed in a DCIM circuit is the multiply-accumulate (MAC) operation, which is helpful for applications such as neural network inference or scientific computing. In traditional DCIM implementations, MAC operations consume a significant amount of power, with multiplier circuits and adder trees accounting for more than 75% of the total power consumption. Adder units (including half-adders and full-adder (FA) units) constitute most of the components in the multiplier and adder trees, and their contribution to dynamic power consumption is significant due to frequent state transitions and buffering operations within the logic path. Traditional adder circuits use output buffers for summation and carry to maintain signal integrity and polarity consistency between operation stages. However, these buffers introduce additional capacitors and switching activity, thereby increasing power consumption without a corresponding improvement in performance.

[0009] The techniques described in this disclosure introduce FA circuit topologies that modify the output polarity of the summing and carry paths to reduce power consumption in the DCIM adder tree. These techniques eliminate or reconfigure output buffers in FA cells based on predefined polarity configurations, thereby minimizing unnecessary switching activity. The techniques described in this disclosure can be used to implement adder trees with various configurations, including: configurations containing only FA cells with summing and carry paths having negative outputs, configurations containing FA cells with negative summing outputs and positive carry outputs, and configurations containing FA cells with positive summing outputs and negative carry outputs. In some implementations, one or more of these configurations can be combined to implement various different adder trees, as described further in detail in this disclosure. Compared to circuits implementing conventional FA circuits, the techniques described in this disclosure significantly reduce power consumption in DCIM MAC operations.

[0010] Referring to Figure 1, Figure 1 illustrates an example full adder circuit 100 according to some embodiments. Each component shown in the full adder circuit 100 may receive power from one or more voltage sources (such as power supply voltage VDD). The full adder circuit 100 may include one or more logic gates and sub-circuits, wherein each sub-circuit may be composed of one or more logic gates. Logic gates are electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0011] Various embodiments of the circuitry and logic gates implementing the full adder circuit 100 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the full adder circuit 100 shown in Figure 1 may be part of a DCIM circuit, a MAC circuit, an adder tree circuit, or any other type of circuit that implements adder operations. In some implementations, the full adder circuit 100 may be included in one or more memory circuits. The full adder circuit 100 is illustrated as including transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20. The full adder circuit 100 is illustrated as including a first inverter 102 and a second inverter 104.

[0012] Although each transistor M1 to M20 in the full adder circuit 100 is illustrated as a single transistor, the embodiments are not limited thereto. For example, each transistor may comprise multiple transistors ("sub-transistors") connected in parallel. For example, each sub-transistor of any transistor described in this disclosure may comprise a corresponding gate, drain, and source terminal, each of which may be connected in parallel. Each of transistors M1 to M20 comprises a gate, a first source / drain, and a second source / drain. Transistors M1, M2, M5, M6, M9, M11, M12, M15, M16, and M17 are illustrated as p-type MOSFET transistors. Transistors M3, M4, M7, M8, M10, M13, M14, M18, M19, and M20 are illustrated as n-type MOSFET transistors. In some implementations, transistors M1 to M20 may include other types of transistors, such as bipolar junction transistors or high electron mobility transistors, but these are still within the scope of this disclosure.

[0013] The gates of transistors M2, M3, M6, M7, M12, M13, M17, and M18 are shown as being coupled to the first input operand A. The gates of transistors M1, M4, M8, M5, M11, M14, M16, and M19 are shown as being coupled to the second input operand B. The gates of transistors M9, M15, M10, and M20 are coupled to the carry input CI. The gates of transistors M1 to M20 are used to receive corresponding input signals to control the conduction state of the transistors.

[0014] The first source / drain terminals of transistors M1, M2, M5, M9, M11, M12, and M15 are connected to the power supply voltage VDD. The second source / drain terminals of transistors M3, M4, M8, M10, M13, M14, and M20 are coupled to the ground voltage. The second source / drain terminal of transistor M1 is coupled to the power supply terminal of the first inverter 102. The second source / drain terminal of transistor M2 is also coupled to the power supply terminal of the first inverter 102. The first source / drain terminals of transistors M3 and M4 are coupled to the ground terminal of the first inverter 102.

[0015] The second source / drain terminal of transistor M5 is coupled to the first source / drain terminal of transistor M6. The second source / drain terminal of transistor M6 is coupled to the output terminal of the first inverter 102, the first source / drain terminal of transistor M7, and the input terminal of the second inverter 104. The second source / drain terminal of transistor M7 is coupled to the first source / drain terminal of transistor M8. The second source / drain terminals of transistors M9, M11, and M12 are coupled to the power supply terminal of the second inverter 104. The first source / drain terminals of transistors M10, M13, and M14 are coupled to the ground terminal of the second inverter 104.

[0016] The second source / draw terminal of transistor M16 is coupled to the first source / draw terminal of transistor M17. The second source / drawer terminal of the transistor M17 is coupled to the output of the second inverter 104 . The first source / draw terminal of the transistor M18 is coupled to the output of the second inverter 104 . The first source / draw terminal of transistor M19 is coupled to the second source / draw terminal of transistor M18. The first source / draw terminal of transistor M20 is coupled to the second source / draw terminal of transistor M19. The negative carry output CB of the full adder circuit 100 is provided at the output of the first inverter 102 , and the negative sum output SB of the full adder circuit 100 is provided at the output of the second inverter 104 .

[0017] During the operation of the full adder circuit 100, when the first input operator A is in a logic low state, the second input operator B is in a logic low state, and the carry input CI is in a logic low state, transistors M2, M6, M12, and M17 are turned on because their gates are coupled to the first input operator A that is in a logic low state. Similarly, the transistors M1, M5, M11, and M16 are turned on because their gates are coupled to the second input operator B which is in the logic low state. In addition, n-type transistors M3, M7, M13, and M18 are turned off, while transistors M4, M8, M14, and M19 are turned on. Transistors M9 and M15 are on and on, and transistors M10 and M20 are off because their gates are coupled to the carry input CI.

[0018] In these states, the power supply terminal of the first inverter 102 is connected to the power supply voltage VDD via the connected transistors M1 and M2. The ground terminal of the first inverter 102 is disconnected from ground due to the off transistors M3 and M4. According to the carry input CI, the input terminal of the first inverter 102 is in a grounded state. This configuration results in the output of the first inverter 102 being in a logic high state, thereby providing a negative carry output CB in a logic high state that is the inverting of the actual carry value "0" (e.g., negative output). Furthermore, the nodes connected to the carry output CB and the inputs of the second inverter 104 are pulled to the logic high state since transistors M5 and M6 are on and transistors M7 and M8 are off.

[0019] Furthermore, in these input states, due to the on transistors M9, M11, and M12, the power supply terminal of the second inverter 104 is connected to the power supply voltage VDD. The ground terminal of the second inverter 104 is disconnected from ground via the off transistors M10, M13, and M14. The output node of the second inverter and the negative sum output SB of the circuit are pulled to a logic high state (e.g., the logic inversion of the actual sum value "0"). Since the second inverter 104 is disconnected from ground, the output terminal of the second inverter 104 will be a floating output (e.g., not pulled to ground). However, since transistors M15, M16, and M17 are on and conducting, while transistors M18, M19, and M20 are off, the negative sum output is pulled to a logic high state.

[0020] In another example, when the first input operand A is in a logic high state, the second input operand B is in a logic high state, and the carry input CI is in a logic high state, transistors M3, M7, M13, and M18 will be turned on because their gates are coupled to the first input operand A in a logic high state. Transistors M4, M8, M14, and M19 will also be turned on because their gates are coupled to the second input operand B in a logic high state. In addition, transistors M10 and M20 will be turned on, while transistors M9 and M15 will be turned off because their gates are coupled to the carry input CI in a logic high state. Transistors M1, M2, M5, M6, M11, M12, M16, and M17 will be turned off because their gates are coupled to the corresponding input operands A or B in a logic high state, while transistors M18 and M19 will be turned on.

[0021] In these states, due to the off transistors M1 and M2, the power supply terminal of the first inverter 102 is disconnected from the power supply voltage VDD. The ground terminal of the first inverter 102 is grounded via the on transistors M3 and M4. The output terminal of the first inverter 102 is pulled to a logic low state via a conductive path formed by the grounded on transistors M7 and M8. Furthermore, the first inverter 102 receives a carry input CI that is in a logic high state and pulls that output terminal to ground. This configuration causes the output of the first inverter 102 (e.g., a negative carry output CB) to be in a logic low state, which is the inversion of the actual carry value "1".

[0022] Due to the off transistors M9, M11, and M12, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded via the on transistors M10, M13, and M14. The output node of the second inverter and the negative sum output SB of the circuit are pulled to a logic low state (the inversion of the actual sum value "1"). Since the second inverter 104 is disconnected from the power supply voltage VDD, its output will be a floating output. However, when the on transistors M18, M19, and M20 are turned on, they pull the negative sum output SB to a logic low state (via ground connection), representing the inversion of the actual sum value "1".

[0023] In some implementations, when the first input operand A is in a logic high state, the second input operand B is in a logic low state, and the carry input CI is in a logic low state, transistors M3, M7, M13, and M18 (n-type, with their gates coupled to the first input operand A) will be turned on. Transistors M2, M6, M12, and M17 (p-type, with their gates coupled to the first input operand A) will be turned off. Transistors M1, M5, M11, and M16 (p-type, with their gates coupled to the second input operand B) will be turned on. Transistors M4, M8, M14, and M19 (n-type, with their gates coupled to the second input operand B) will be turned off. Transistors M9 and M15 (p-type, with their gates coupled to the carry input CI) will be turned on, and transistors M10 and M20 (n-type, with their gates coupled to the carry input CI) will be turned off.

[0024] The power supply terminal of the first inverter 102 is connected to the power supply voltage VDD via a switched-on transistor M1. The ground terminal of the first inverter 102 is grounded via a switched-on transistor M3. The input terminal of the first inverter 102 is pulled to a logic low state via a conductive path formed by a grounded switched-on transistor M7 (n-type). This configuration causes the output terminal of the first inverter 102 to be in a logic high state, thereby providing a negative carry output CB (the inversion of the actual carry value "0") in a logic high state.

[0025] The input terminal of the second inverter 104 is pulled to a logic low state via the on transistor M7 (n-type). Because transistors M2, M6, M12, and M17 are off, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded via the on transistor M13 (n-type). Therefore, the output terminal of the second inverter 104 is pulled to a logic high state (the inversion of the actual sum value "1").

[0026] To further illustrate, if the input operands A and B are in a logic high state, while the carry input CI is in a logic low state, then the power supply terminal of the second inverter 104 will be connected to the power supply voltage VDD, causing it to operate and pull the negative sum output SB to a logic high state (the inversion of the actual sum value "0"). Since the carry input CI is in a logic high state, the transistor M20 will be turned off, and therefore the negative sum output SB will not be pulled to ground as described above.

[0027] In some implementations, when one of the first input operand A or the second input operand B is in a logic high state and the other is in a logic low state, and the carry input CI is in a logic high state, the transistor coupled to the high operand (e.g., an n-type transistor used to make the first input operand A high or the second input operand B high) is turned on, thereby grounding the ground terminal of the first inverter 102. The transistor coupled to the low operand (e.g., a p-type transistor used to make the second input operand B low or the first input operand A low) is turned on, thereby connecting the power supply terminal of the first inverter 102 to the power supply voltage VDD. This configuration pulls the output terminal of the first inverter 102 to a logic low state, causing the negative carry output CB to be in a logic low state (the inversion of the actual carry value "1"). The ground terminal of the second inverter 104 is connected via a transistor (e.g., transistor M10 or M20) coupled to the carry input CI, while the power supply terminal of the second inverter 104 is connected via one of transistors M11 or M12, depending on which input operand is in a logic low state. This configuration will activate the second inverter 104, causing the negative sum output SB to be in a logic high state (the inversion of the actual sum value "0").

[0028] In some implementations, when one of the input operands A or B is in a logic high state and the other is in a logic low state, and the carry input CI is in a logic low state, the transistor coupled to the low operand (e.g., a p-type transistor used to bring the second input operand B low or the first input operand A low) is turned on, thereby connecting the power supply terminals of the first inverter 102 and the second inverter 104 to the power supply voltage VDD. The ground terminals of the first inverter 102 and the second inverter 104 are also grounded via one of transistors M3 and M4 or one of transistors M13 and M14, respectively. The first inverter 102 is activated and generates a negative carry output CB (the inverted version of the carry value "0") in a logic high state. The second inverter 104 is also activated and generates a negative sum output SB (the inverted version of the actual sum value "1") in a logic low state.

[0029] In another example, when the carry input CI is in a logic high state, and the first input operand A and the second input operand B are in a logic low state, transistors M10 and M20 (n-type, with their gates coupled to the carry input CI) are turned on, while transistors M9 and M15 (p-type, with their gates coupled to the carry input CI) are turned off. Due to the off transistors M9, M11, and M12, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded through the turned-on transistor M10. The input terminal of the second inverter 104 is pulled to a logic low state through a conductive path formed by the turned-on transistor M10, causing the output (negative sum output SB) to be in a logic high state (the inverted version of the actual sum value "1"). The negative carry output CB of the first inverter 102 is determined by the states of the input operands A and B.

[0030] The truth table of the negative full adder circuit 100 is as follows. Input operand A Input operand B Carry Input CI Negative total output SB Negative carry output CB 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0

[0031] The negative full adder circuit 100 can be implemented in any suitable circuit, including any adder tree circuit, MAC circuit, or multiplication circuit described in this disclosure. Although the full adder circuit 100 is described as a "negative" adder circuit (e.g., logically inverting the sum and carry as described in this disclosure), the full adder circuit 100 may include inverters to produce one or more "positive" (e.g., uninverted) outputs. Without additional output inverters, the full adder circuit 100 may include 24 transistors (e.g., 20 transistors M1 to M20, with inverters 102 and 104 each having two transistors, etc.).

[0032] In one example, the negative sum output SB can be used as an input to an inverter to produce a positive sum output that reflects the actual sum value corresponding to the input operands A and B and the carry input CI. Furthermore, the negative carry output CB can be used as an input to an inverter to produce a positive carry output that reflects the actual sum value corresponding to the input operands A and B and the carry input CI. Different configurations of the negative full adder circuit 100 (including zero, one, or more additional inverters) can be implemented in various circuits described in this disclosure. For a single-output inverter, the full adder circuit 100 may include 26 transistors (e.g., 20 transistors M1 to M20 in total, where inverters 102 and 104 each contain two transistors, and the output inverter also contains two transistors, etc.).

[0033] Referring to Figure 2, Figure 2 illustrates a schematic diagram of an example adder tree circuit 200 according to some embodiments, the adder tree circuit 200 including a full adder circuit with a negative output. Each component shown in the adder tree circuit 200 can receive power from one or more voltage sources (such as power supply voltage VDD, illustrated here as "V" for simplicity, which can be interpreted as a logic high input in this disclosure). The adder tree circuit 200 may include one or more logic gates and sub-circuits, wherein each sub-circuit may be composed of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0034] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 200 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the adder tree circuit 200 shown in Figure 2 may be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuitry that implements addition operations.

[0035] In this example, the adder tree circuit 200 is illustrated as comprising three stages, wherein the first stage adds 3-bit input values ​​A (represented in bits as A1, A2, and A3) to 3-bit input values ​​B (represented in bits as B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented in bits as C1, C2, and C3) and 3-bit input values ​​D (represented in bits as D1, D2, and D3).

[0036] The adder tree circuit 200 can be implemented using the full adder circuit 100 of Figure 1. The adder tree circuit 200 is illustrated as including a set of first negative full adders 202A~201I (sometimes collectively referred to as "first negative full adder 202") and a set of second negative full adders 204A~204F (sometimes collectively referred to as "second negative full adder 204"). Each of the first negative full adder 202 and the second negative full adder 204 may include the full adder circuit 100 of Figure 1 and implement any function of the full adder circuit 100 of Figure 1. In this way, the first negative full adder 202 and the second negative full adder 204 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure).

[0037] In the adder tree circuit 200 of Figure 2, due to the configuration of simultaneously generating a negative sum output and a negative carry output, and due to its connection with other negative adders within the adder tree circuit 200, the first negative full adder 202 receives a "positive" input (e.g., a logic-uninverted input) and generates a "negative" output (e.g., a logic-inverted output). For example, the first negative full adder 202A can receive positive inputs "1" and "0" and generate a negative output sum value "0" (e.g., the inverted version of the true sum value "1") and a negative output carry value "1" (e.g., the inverted version of the true carry value "0").

[0038] Furthermore, due to the configuration that simultaneously generates a negative sum output and a negative carry output, and its connection with other negative adders within the adder tree circuit 200, the second negative full adder 204 receives a "negative" input (e.g., a logically inverted input) and generates a corresponding "positive" output (e.g., a logically uninverted output). For example, the second negative full adder 204A can receive inverted inputs "0" and "1", an inverted carry input of "1", and generate a positive output sum value "1" (e.g., a true sum value "1", considering that the input carry itself represents the value "0") and a negative output carry value "0" (e.g., a true carry "0"). It should be noted that although the first full adder 202 and the second full adder 204 have the same structure, the second full adder 204 can generate an output that is logically uninverted relative to the value it represents, while the first full adder 202 can generate an output that remains inverted. This difference arises because the second full adder 204 receives an inverted input, so its output returns to a non-inverted logic state, while the first full adder 202 processes a non-inverted input and maintains an inverted state in its output.

[0039] In the example implementation shown in Figure 2, the adder tree circuit 200 can sum four 3-bit values ​​A, B, C, and D via a hierarchical configuration of a first negative full adder 202 and a second negative full adder 204. Figure 2 illustrates each 3-bit value A, B, C, and D, where bit identifiers are used to identify the index of the corresponding bit. For example, A0 corresponds to the least significant bit in value A, B2 corresponds to the most significant bit in value B, and so on. The first stage of the adder tree circuit 200 includes first full adders 202A~202D and second full adders 204A, 204B. Depending on inputs A and B, the first negative full adder 202A can receive positive inputs A0, B0 and a ground level carry input (G) representing a logic low state (e.g., a positive carry value of zero). The second negative full adder 204A can receive inverted inputs A1 and B1 (e.g., logical NOT versions of actual values ​​A1 and B1) and a negative carry output generated by the first negative full adder 202A. The inverted states of inputs A1 and B2 are visually represented by the horizontal line above the signal label in Figure 2. The second negative full adder 204B can process positive inputs A2 and B2 using the positive carry output from the second negative full adder 204A, as shown in the figure.

[0040] For inputs C and D, the first negative full adder 202C can similarly receive positive inputs C0, D0 and a level carry input (G). The second negative full adder 204B can receive inverted inputs C1 and D1 (logical inversions of the actual values ​​C1 and D1) and is coupled to the negative carry output from the first negative full adder 202C. The second negative full adder 204B can receive and process positive inputs C2 and D2 using the positive carry output from the previous second negative full adder 204B. The first stage is used to generate a sum representing inputs A+B and inputs C+D, and these sums are provided to the next stage of the adder tree circuit 200.

[0041] In the second stage of the adder tree circuit 200, the second negative full adder 204C sums the negative sum output of the first negative full adders 202A and 202C in the first stage and the logic high carry input (V), wherein the logic high carry input (V) is the inverted signal of the actual carry value "0". The second negative full adder 204C generates a positive sum output that is sent to the third stage adder in the adder tree circuit 200, and generates a positive carry output that is provided to the first negative full adder 202E. The first negative full adder 202E receives the positive sum output of the second negative full adders 204A and 204B in the first stage and the positive carry output of the second negative full adder 204C. The first negative full adder 202E generates a negative sum output that is provided to the third stage, and generates a negative carry output that is sent to the second negative full adder 204D.

[0042] The second negative full adder 204D adds the negative sum output of the first negative full adders 202B and 202D in the first stage to the negative carry output of the first negative full adder 202E, thereby generating a positive sum output for the third stage and a positive carry output provided to the first negative full adder 202F. The first negative full adder 202F can also process the negative sum output of the first negative full adders 202B and 202D and the positive carry output of the second negative full adder 204D to accommodate two-complement arithmetic. The alternating structure of inverting and non-inverting inputs and outputs on the first negative full adder 202 and the second negative full adder 204 enables the entire adder tree circuit 200 to transmit carry signals and intermediate sums, while maintaining operational accuracy through multiple adder stages.

[0043] The third stage of the adder tree circuit 200 serves as the final summing layer, and in this example includes first negative full adders 202G and 202H, and second negative full adders 204E and 204F. The first negative full adder 202G receives the negative sum output from the second negative full adder 204C of the second stage, a logic low value (G) as the second operand, and a logic low carry input (G). The logic low second operand is used as a logic zero operation to maintain the equality of the input sum. The first negative full adder 202G generates a negative sum output, which can be inverted using an inverter (as shown) to produce the final logically correct sum value. The negative carry output of the first negative full adder 202G can be provided to the second negative full adder 204E to transmit the carry signal via the third stage.

[0044] The second negative full adder 204E can process the negative sum output of the first negative full adder 202E in the second stage, and combine it with the logic high value (V) as the second operand (as an inverted logic zero, essentially adding a logic zero) and the negative carry input from the first negative full adder 202G. The second negative full adder 204E can produce a positive sum output (which can be part of the final output) and produce a positive carry output provided to the first negative full adder 202H. The first negative full adder 202H can receive the negative sum output of the second negative full adder 204D in the second stage, and pair it with the logic low value (G) as the second identity operand, and the positive carry input from the second negative full adder 204E. The first negative full adder 202H can produce a negative sum output, which is inverted to produce the correct (positive) final sum value, and can transmit the negative carry output to the second negative full adder 204F.

[0045] The second negative full adder 204F can process the negative sum output from the first negative full adder 202F in the second stage, the logic high value (V) as the second operand (e.g., the identity operator), and the negative carry input from the first negative full adder 202H. The second negative full adder 204F can produce a positive sum as part of the final output and produce a positive carry output provided to the first negative full adder 202I. The first negative full adder 202I can also process the negative sum output from the first negative full adder 202F in the second stage, and combine it with the logic high value (V) and the positive carry input from the second negative full adder 204E. The inputs of the first negative full adder 202I are the same as those of the second negative full adder 204F to be compatible with two-complement arithmetic. As shown, the first negative full adder 202I can produce a negative sum output, which is inverted to form the final logically accurate result.

[0046] Referring to Figure 3, Figure 3 illustrates a schematic diagram of an example adder tree circuit 300 according to some embodiments, the adder tree circuit 300 comprising a full adder circuit having a negative sum output and a positive carry output. Each component shown in the adder tree circuit 300 may receive power from one or more voltage sources (such as power supply voltage VDD, illustrated herein as "V" for simplicity, which may be interpreted in this disclosure as a logic high input). The adder tree circuit 300 may include one or more logic gates and sub-circuits, wherein each sub-circuit may be composed of one or more logic gates. The logic gates may be electronic devices for performing logical operations on one or more input signals to produce a single output signal.

[0047] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 300 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the adder tree circuit 300 shown in Figure 3 may be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0048] Similar to the example shown in Figure 2, in this example, the adder tree circuit 300 is illustrated as comprising three stages, wherein the first stage adds 3-bit input values ​​A (represented in bits as A1, A2, and A3) to 3-bit input values ​​B (represented in bits as B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented in bits as C1, C2, and C3) and 3-bit input values ​​D (represented in bits as D1, D2, and D3).

[0049] Similar to the adder tree circuit 200 in Figure 2, the adder tree circuit 300 can be implemented using one or more full adder circuits 100 in Figure 1. The adder tree circuit 300 is illustrated as including a set of first negative full adders 302A~302K (sometimes collectively referred to as "first negative full adders 302") and a set of second negative full adders 304A~304D (sometimes collectively referred to as "second negative full adders 304"). Each of the first negative full adders 302 and the second negative full adders 304 can include the full adder circuit 100 in Figure 1 and implement any of the functions of the full adder circuit 100 in Figure 1.

[0050] In the illustrated example, the first negative full adder 302 and the second negative full adder 304 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure). However, the logically inverted carry outputs of the first negative full adder 302 and the second negative full adder 304 are respectively used as inputs to the inverter 306, such that the carry output of the first negative full adder 302 is a positive carry output, and the carry output of the second negative full adder 304 is a negative carry output. It should be noted that, for clarity, the reference numbers of some inverters 306 are omitted in Figure 3.

[0051] In the first stage of the adder tree circuit 300, the first negative full adders 302A-302C can process individual bits of the input values ​​A and B (e.g., positive inputs A0+B0, A1+B1, A2+B2), as shown in the figure. For example, the first negative full adder 302A can receive positive inputs A0, B0 and a level carry input (G), and (via an inverter 306 applied to the carry output) generate a negative sum output (e.g., a logical inversion of the true sum) and a positive carry output. The first negative full adder 302B can similarly receive positive inputs A1, B1 and a positive carry output from the first negative full adder 302A via an inverter 306 to generate a negative sum output and a positive carry output. The first negative full adder 302C can process the positive inputs A2 and B2 via inverter 306 and couple them with the positive carry output from the first negative full adder 302B to produce a negative sum output and a positive carry output.

[0052] The first stage of the adder tree circuit 300 is illustrated as including first negative full adders 302D~302F for processing individual bits of input values ​​C and D (e.g., positive inputs C0+D0, C1+D1, C2+D2). The first negative full adder 302D can receive positive inputs C0, D0 and a level carry input (G), and generate a negative sum output and a positive carry output. The first negative full adder 302E can process positive inputs C1 and D1, and combine the positive carry output of the first negative full adder 302D to generate a negative sum output and a positive carry output (via inverter 306). Similarly, the first negative full adder 302F can receive positive inputs C2, D2 and the positive carry output of the first negative full adder 302E via inverter 306 to generate a negative sum output and a positive carry output via inverter 306.

[0053] In the second stage of the adder tree circuit 300, the second negative full adders 304A-304D can sum the intermediate sum generated by the first negative full adder 302 in the first stage. The second negative full adder 304A can receive the negative sum output from the first negative full adders 302A and 302D and the logic zero logic high carry input (V) representing inversion. The second negative full adder 304A can generate a positive sum output (e.g., a combination of the logic inversion of the negative sum input and the inverted carry input) and a negative carry output (via an inverter 306 applied to the carry output). The second negative full adder 304B can receive the negative sum output from the first negative full adders 302B and 302E and couple it with the negative carry output from the second negative full adder 304A to generate a positive sum output and a negative carry output.

[0054] The second negative full adder 304C can process the negative sum output from the first negative full adders 302C and 302F and the negative carry output from the second negative full adder 304B to generate a positive sum output (provided to the third stage of the adder tree circuit 300) and a negative carry output via the corresponding inverter 306. The second negative full adder 304D can similarly receive the negative sum output from the first negative full adders 302B and 302D and combine it with the negative carry output from the second negative full adder 304C to generate a positive sum output (provided to the third stage of the adder tree circuit 300) and a negative carry output.

[0055] In the third stage, the first negative full adder 302G can receive the positive sum output of the second negative full adder 304A in the second stage, as well as the level value (G) and level carry input (G) as the second operand (used as the identity operation input). The first negative full adder 302G can generate a negative sum output, which can be inverted by inverter 306 to generate the final logically correct least significant bit of the sum. The negative carry output of the first negative full adder 302G can be inverted by inverter 306 to generate a positive carry signal provided to the first negative full adder 302H.

[0056] The first negative full adder 302H can receive the positive sum output from the second negative full adder 304B of the second stage, pair it with the access level value (G) as the second operand, and receive the positive carry input from the first negative full adder 302G via inverter 306. The first negative full adder 302H can generate a negative sum output, which is inverted by inverter 306 to form the next significant bit of the final output. The negative carry output of the first negative full adder 302H is inverted by inverter 306 to generate a positive carry signal provided to the first negative full adder 302I.

[0057] The first negative full adder 302I can process the positive sum output from the second negative full adder 304C of the second stage, combined with the ground level value (G) as the second operand and the positive carry input from the inverter 306 coupled to the carry output of the first negative full adder 302H. The first negative full adder 302I can generate a negative sum output, which is inverted by the inverter 306 to generate subsequent bits of the final output. The negative carry output of the first negative full adder 302I is inverted by the inverter 306 to generate a positive carry signal provided to the first negative full adder 302J.

[0058] The first negative full adder 302J can receive the positive sum output from the second negative full adder 304D of the second stage, the access level value (G) as the second operand, and the positive carry input from the inverter 306 coupled to the carry output of the first negative full adder 302J. The first negative full adder 302J can generate a negative sum output, which is inverted by the inverter 306 to form the most significant bit of the final output. The negative carry output of the first negative full adder 302J is inverted by the inverter 306 to pass the remaining carry signal to the higher-order bits.

[0059] The first negative full adder 302K can receive a positive sum output (the same as the first negative full adder 302J) from the second negative full adder 304D, paired with the access level value (G) as the second operand, and receive the positive carry output from the first negative full adder 302J via inverter 306. The first negative full adder 302K receives the output to maintain compatibility with two-complement arithmetic by preserving the state of the most significant bit for correct sign and overflow handling. The first negative full adder 302K can produce a negative sum output, which is inverted by inverter 306 to produce the final logically accurate result of the most significant bit. The negative carry output of the first negative full adder 302K can be ignored or retained as part of the overflow state signal.

[0060] Referring to Figure 4, Figure 4 illustrates a schematic diagram of an example adder tree circuit 400 according to some embodiments, the adder tree circuit 400 comprising a full adder circuit having a positive sum output and a negative carry output. Each component shown in the adder tree circuit 400 may receive power from one or more voltage sources (such as power supply voltage VDD, illustrated herein as "V" for simplicity, which may be interpreted in this disclosure as a logic high input). The adder tree circuit 400 may include one or more logic gates and sub-circuits, each sub-circuit consisting of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0061] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 400 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the adder tree circuit 400 shown in Figure 4 may be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0062] Similar to the example shown in Figure 2, in this example, the adder tree circuit 400 is illustrated as comprising three stages, wherein the first stage adds 3-bit input values ​​A (represented in bits as A1, A2, and A3) to 3-bit input values ​​B (represented in bits as B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented in bits as C1, C2, and C3) and 3-bit input values ​​D (represented in bits as D1, D2, and D3).

[0063] Similar to the adder tree circuit 200 in Figure 2, the adder tree circuit 400 can be implemented using one or more full adder circuits 100 in Figure 1. The adder tree circuit 400 is illustrated as including a set of first negative full adders 402A~402I (sometimes collectively referred to as "first negative full adders 402") and a set of second negative full adders 404A~404F (sometimes collectively referred to as "second negative full adders 404"). Each of the first negative full adders 402 and the second negative full adders 404 can include the full adder circuit 100 in Figure 1 and implement any of the functions of the full adder circuit 100 in Figure 1.

[0064] In the illustrated example, the first negative full adder 402 and the second negative full adder 404 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure). However, the logically inverted carry outputs of the first negative full adder 402 and the second negative full adder 404 are respectively used as inputs to the inverter 406, such that the sum output of the first negative full adder 402 is a positive sum output, and the sum output of the second negative full adder 404 is a negative sum output. It should be noted that, for clarity, the reference numbers of some inverters 406 are omitted in Figure 4.

[0065] In the first stage, similar to the example arrangement described in conjunction with Figures 2 and 3, the example adder tree circuit 400 can sum four 3-bit values ​​A, B, C, and D via a hierarchical configuration of a first negative full adder 402 and a second negative full adder 404. The first stage of the adder tree circuit 400 includes first negative full adders 402A, 402B, 402C, 402D and second negative full adders 404A and 404B. For inputs A and B, the first negative full adder 402A can receive positive inputs A0, B0 and a level carry input (G), and generate a positive sum output via an inverter 406 coupled to the output. The second negative full adder 404A can receive inverted inputs A1 and B1 (e.g., logically inverted versions of the actual values ​​A1 and B1, indicated by the horizontal lines above each value) and a negative carry output from the first negative full adder 402A, and generate a negative sum output via an inverter 406 coupled to the output. The first negative full adder 402B can process positive inputs A2 and B2 and a positive carry output from the second negative full adder 404A to generate a negative sum output, which is inverted by the inverter 406 to generate a positive sum output. As shown, the sum output generated by adders 402A, 404A, and 402B is provided as an operand to the second stage.

[0066] In the first stage, for inputs C and D, the first negative full adder 402C can similarly receive positive inputs C0, D0 and a level carry input (G), and produce a negative sum output, which is inverted by inverter 406 to produce a positive sum output. The second negative full adder 404B can receive the logical inversion of inputs C1 and D1 (indicated by the horizontal line above each value) and the negative carry output from the first negative full adder 402C, and produce a negative sum output via inverter 406 coupled to the output. The first negative full adder 402D can process positive inputs C2 and D2 and the positive carry output from the second negative full adder 404B to produce a negative sum, which is inverted by inverter 406 to produce a positive sum output. As shown, the sum output produced by adders 402C, 404B and 402D is provided as an operand to the second stage.

[0067] In the second stage, the adder tree circuit 400 includes first negative full adders 402E and 402F and second negative full adders 404C and 404D. The first negative full adder 402E can receive the positive sum output from the first negative full adders 402A and 402C of the first stage and connect to the level carry input (G). As shown, the first negative full adder 402E can generate a positive sum output provided to the third stage via inverter 406. The second negative full adder 404C can (via inverter 406) receive the negative sum output from the second negative full adders 404A and 404B of the first stage and the negative carry output from the first negative full adder 402E, and generate a negative sum output via the corresponding inverter. The first negative full adder 402F can (via inverter 406) process the negative sum output from the first negative full adders 402B and 402D in the first stage and the positive carry output from the second negative full adder 404C to produce a positive sum value via inverter 406. The second negative full adder 404D can receive the same negative sum output from the first negative full adders 402B and 402D and the negative carry output from the first negative full adder 402F to produce a negative sum output via inverter. The second negative full adder 404D receives the same input as the first negative full adder 402F to maintain two's complement compatibility.

[0068] The third stage (and the last stage in this example) of the adder tree circuit 400 is illustrated as comprising first negative full adders 402G~402I and second negative full adders 404E, 404F. The first negative full adder 402G can (via inverter 406) receive the positive sum output from the first negative full adder 402E of the second stage, paired with the logic low value (G) and logic low carry input (G) as the second operand. The first negative full adder 402G can generate a negative sum output, which is inverted by inverter 406 to produce the final positive sum value for the least significant bits of the output. The negative carry output of the first negative full adder 402G can be provided to the second negative full adder 404E. The second negative full adder 404E can process the negative sum output from the second negative full adder 404C of the second stage, and combine it with the logic high value (V) as the inverted identity operand and the negative carry input from the first negative full adder 402G to produce a positive sum output, which is the next least significant bit of the resulting output.

[0069] The first negative full adder 402H can (via inverter 406) receive the negative sum output from the first negative full adder 402F of the second stage and the logic low value (G) as the identity operand, and receive the positive carry output from the second negative full adder 404E to generate a negative sum output, which is inverted by inverter 406 to become the positive output bit value of the third least significant bit of the output sum. The second negative full adder 404F can process the negative sum output from the second negative full adder 404D of the second stage, pair it with the logic high value (V) as the inverted identity operand, and process the negative carry output from the first negative full adder 402H to generate a positive sum output as the second most significant bit of the output sum. The first negative full adder 402I can process the same input as the second negative full adder 404F, similar to other configurations described in this disclosure, to produce the most significant bit of the output sum while maintaining two's complement compatibility.

[0070] Although the adder tree circuits 200, 300, and 400 in Figures 2, 3, and 4 are described as having three stages, it should be understood that each stage of the adder tree circuits 200, 300, and 400 in Figures 4, 5, and 6 may contain any number of inputs, thereby producing more stages than the three stages shown in Figures 2, 3, and 4. For example, in some implementations, additional two-stage portions similar to the first two stages shown in Figures 2, 3, and 4 may be included to facilitate addition of four additional values. For example, the outputs of two second stages may be combined in the third stage shown in Figures 2, 3, and 4. For example, the outputs of the additional second stages may be provided as second input operands to each adder in the third stage, rather than the identity inputs described in this disclosure. The outputs of the third stage may then be provided to the fourth stage, and so on, to combine any number of values. Furthermore, although the example described in conjunction with Figures 2, 3 and 4 is described as adding a 3-bit operand, it should be noted that the full adder circuit 100 of Figure 1 (or a variant thereof) can be used to accumulate operands with any bit width, for example by including additional adder circuitry in each adder stage to accommodate additional bits for each operand.

[0071] Referring to Figure 5, Figure 5 illustrates a schematic diagram of an example MAC circuit 500 according to some embodiments, which can implement one or more adder tree circuits described in conjunction with Figures 2, 3, and 4. Each component shown in the MAC circuit 500 can receive power from one or more voltage sources (such as power supply voltage VDD). The MAC circuit 500 may include one or more logic gates and sub-circuits, each sub-circuit being composed of one or more logic gates. The logic gates can be electronic devices used to perform logical operations on one or more input signals to generate a single output signal.

[0072] The MAC circuit 500 is illustrated as including a MAC operand memory 502, an operand input register 504, a multiplier circuit 506, a first adder tree circuit 508, a set of partial sum registers 510, a second adder tree circuit 512, and a set of output registers 514. Various embodiments of the circuitry and logic gates implementing the MAC circuit 500 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the MAC circuit 500 shown in Figure 5 may be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operations.

[0073] The MAC operand memory 502 may include any type of memory circuitry, including but not limited to static random-access memory (SRAM) arrays, dynamic random-access memory (DRAM) circuitry, or other storage media capable of storing MAC operands. In some implementations, the MAC operand memory 502 may organize the stored data into columns and rows corresponding to the dimensions of the weight matrix or tensor, including but not limited to 8-bit weight values ​​used for machine learning operations. In some implementations, the MAC operand memory 502 may provide a read port to output selected 8-bit weight values ​​in parallel to the multiplier circuit 506, thereby enabling simultaneous access to multiple operands during operation.

[0074] The operand input register 504 may include a set of flip-flop circuits for storing the elements of the input vector. For example, the operand input register 504 may include eight parallel 8-bit registers. In some implementations, the operand input register 504 may align the stored 8-bit values ​​with corresponding 8-bit weight values ​​from the MAC operand memory 502, such that each register pair forms a multiplicand-multiplier pair for the multiplier circuit 506. In some implementations, the operand input register 504 may include or be coupled to multiplexers that can dynamically select input data from external memory interfaces and / or previous processing stages.

[0075] The multiplier circuit 506 can be any type of multiplier circuit, and can generate a product using a first operand stored in the MAC operand memory 502 and a second operand stored in the operand input temporary register 504. In some implementations, the multiplier circuit 506 may include an array of multiplier cells based on a lookup table (LUT). The multiplier cells can operate in parallel to improve overall multiplication performance. A portion of the product generated by the multiplier circuit 506 can be provided as input to the first adder tree circuit 508.

[0076] The first adder tree circuit 508 may include a hierarchical structure of full adder levels, such as the full adders described in conjunction with adder tree circuits 200, 300, and 400 of Figures 2, 3, and 4. In one example, the first adder tree circuit 508 may receive a set of 17-bit partial sums of inputs, which are then simplified to an intermediate value via the first stage of a 2:1 adder. Subsequent stages may further halve the number of partial sums while increasing the bit width of the multiple partial sums, such that after three stages, the output becomes a 19-bit value. In some implementations, pipeline registers may be included between each stage of the first adder tree circuit 508 to synchronize timing with the clock cycle of the MAC circuit 500. The partial sum register 510 may, for example, use a D-type flip-flop array to store the 19-bit value.

[0077] The second adder tree circuit 512 may include a set of summing stages for combining 19-bit partial sums from the partial sum register 510. The second adder tree circuit 512 may include a hierarchical structure of full adder levels, such as the full adders described in conjunction with adder tree circuits 200, 300, and 400 of Figures 2, 3, and 4. For example, the second adder tree circuit 512 may sum eight 19-bit values ​​into a single 22-bit result via two stages of processing, where the first stage reduces the input to 20-bit terms, the subsequent stage reduces the input to 21-bit terms, and the final output stage produces the final 22-bit output. The output register 514 may use, for example, one or more flip-flop circuits to obtain the output. In some implementations, the output register 514 may include error detection circuitry, such as parity check bits, to verify the integrity of the computed output value before transmission.

[0078] Figure 6 illustrates a schematic diagram of a portion of a multiplier circuit 600 according to some embodiments, which may be included in the MAC circuit 500 described in conjunction with Figure 5. The multiplier circuit 600 may be any structure and / or function of, or include, the multiplier circuit 506 of the MAC circuit 500 described in conjunction with Figure 5. Each component shown in the multiplier circuit 600 may receive power from one or more voltage sources, such as the power supply voltage VDD. The multiplier circuit 600 may include one or more logic gates and sub-circuits, each sub-circuit consisting of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0079] The multiplier circuit 600 is illustrated as including a multiplexer array 602, a set of 11-bit adder circuits 604A-604D, a set of 13-bit adder circuits 606A, 606B, and a 17-bit adder circuit 608. Any adder circuit in the multiplier circuit 600 can be implemented using any adder circuit described in conjunction with Figures 1, 2, 3, and 4. Various embodiments of the circuitry and logic gates implementing the multiplier circuit 600 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the multiplier circuit 600 shown in Figure 6 can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operations.

[0080] In this example, the multiplexer array 602 can provide outputs as part of the multiplier circuit 600 to produce partial sums, which are accumulated using 11-bit adder circuits 604A-604D, 13-bit adder circuits 606A, 606B, and 17-bit adder circuit 608. In one example, the multiplexer array 602 (e.g., a MUX4 array) can provide eight 9-bit outputs. Each 11-bit adder circuit 604A-604D can accumulate a corresponding pair of 9-bit outputs from the multiplexer array 602. Each 11-bit adder circuit 604A-604D can be implemented using one or more of the adder circuit configurations described in conjunction with Figures 2, 3, and 4. For example, 11-bit adder circuits 604A-604D may include a multi-stage adder tree that adds each output of the multiplexer array 602 to produce an 11-bit output. Each 11-bit output can be provided as input to a corresponding 13-bit adder circuit 606A, 606B, which in turn can be provided as input to a 17-bit adder circuit 608. The 17-bit adder circuit 608 can accumulate the outputs of the 13-bit adder circuits 606A, 606B to produce a 17-bit partial product output.

[0081] Figure 6 illustrates a schematic diagram of a portion of a multiplier circuit 600 according to some embodiments, which may be included in the MAC circuit 500 described in conjunction with Figure 5. The multiplier circuit 600 may be, or include, any structure and / or function of the multiplier circuit 506 described in conjunction with the MAC circuit 500. Each component shown in the MAC circuit 500 may receive power from one or more voltage sources, such as the power supply voltage VDD. The MAC circuit 500 may include one or more logic gates and sub-circuits, each sub-circuit consisting of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0082] The multiplier circuit 600 is illustrated as including a multiplexer array 602, a set of 11-bit adder circuits 604A-604D, a set of 13-bit adder circuits 606A, 606B, and a 17-bit adder circuit 608. Various embodiments of the circuitry and logic gates implementing the MAC circuit 500 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the MAC circuit 500 shown in Figure 5 may be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operation.

[0083] Referring to Figure 7, which illustrates a schematic diagram of an example adder tree circuit 700 according to some embodiments, the adder tree circuit 700 may include one or more adder tree circuits (e.g., a first adder tree circuit 508, a second adder tree circuit 512, etc.) in conjunction with the MAC circuit 500 described in Figure 5. Each component shown in the adder tree circuit 700 may receive power from one or more voltage sources (such as power supply voltage VDD). The MAC circuit 500 may include one or more logic gates and sub-circuits, each sub-circuit being composed of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0084] The adder tree circuit 700 is illustrated as comprising a set of 17-bit partial product circuits 702, a set of 17-bit adder circuits 704, a set of 18-bit adder circuits 706, a set of 19-bit adder circuits 708, a set of 20-bit adder circuits 710, a set of 21-bit adder circuits 712, and a set of 22-bit adder circuits 714. Any adder circuit in the adder tree circuit 700 may be implemented using any adder circuit described in conjunction with Figures 1, 2, 3, and 4. Various embodiments of the circuitry and logic gates implementing the adder tree circuit 700 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the adder tree circuit 700 shown in Figure 7 can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit implementing MAC operations.

[0085] The 17-bit partial product 702 can be generated by one or more multiplier circuits 600, such as those in Figure 6, which can be part of the MAC circuit 500 in Figure 5. To accumulate the partial product, the adder tree circuit 700 can implement a hierarchical structure of multiple adder circuits. For example, any one of the following can be implemented using the adder tree circuits 200, 300, or 400 described in conjunction with Figures 4, 5, and 6: 17-bit adder circuit group 704, 18-bit adder circuit group 706, 19-bit adder circuit group 708, 20-bit adder circuit group 710, 21-bit adder circuit group 712, and 22-bit adder circuit group 714. In some implementations, the output of the adder tree circuit 700 can be a 23-bit output value, which can be stored as part of a 32-bit floating-point value in, for example, an output register (e.g., output register 514 in Figure 5).

[0086] Referring to Figure 8, Figure 8 illustrates a schematic diagram of an example two-stage adder tree circuit 800 according to some embodiments, the two-stage adder tree circuit 800 including a full adder circuit (e.g., adder tree circuit 100 in Figure 1) having a negative sum output and a negative carry output. Each component shown in the adder tree circuit 800 may receive power from one or more voltage sources (such as power supply voltage VDD, referred to herein as "V" for simplicity, which may be interpreted as a logic high input in this disclosure). The adder tree circuit 800 may include one or more logic gates and sub-circuits, each sub-circuit may be composed of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0087] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 800 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. It should be understood that the adder tree circuit 800 shown in Figure 8 may be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0088] Similar to the example shown in Figure 2, in this example, the adder tree circuit 800 illustrates the summation in the first stage. In the summation in the first stage, the 3-bit input value A (represented by A1, A2, and A3 in bits) is added to the 3-bit input value B (represented by B1, B2, and B3 in bits). The adder tree circuit 800 is illustrated as comprising a set of first negative full adders 802A~802D (sometimes collectively referred to as "first negative full adder 802") and a set of second negative full adders 804A~804C (sometimes collectively referred to as "second negative full adder 804"). Each of the first negative full adder 802 and the second negative full adder 804 may include the full adder circuit 100 of Figure 1 and implement any of the functions of the full adder circuit 100 of Figure 1.

[0089] In the first stage, the operation of the instance adder tree circuit 800 is similar to that of the adder tree circuit 200 in Figure 2, wherein the first adder 802A calculates the negative sum of A0 and B0, the second adder 804A calculates the positive output sum of negative A1 and negative B1, and the first adder 802B calculates the negative sum of A2 and B2. Each sum transmits the corresponding carry value (as described in conjunction with Figure 2) and provides the corresponding sum output to the second stage.

[0090] Similar to the example in Figure 2, the example adder tree circuit 800 includes second negative adders 804B and 804C and first negative adders 802C and 802D. As shown, the first negative adder 804B receives the negative sum, the identity value (e.g., illustrated here as "V", or logic high, indicating that the actual sum is zero) and the logic high carry input (indicating that the actual carry input is zero) from the first adder 802A. The second negative adder 804B generates the least significant positive sum output and passes the positive carry to the first adder 802C.

[0091] The first negative adder 802C receives the positive sum from the second adder 804A, the positive carry output from the second adder 804B, and a logic low identity input (indicating that the actual sum input is zero). The first negative adder 802C generates the next least significant negative sum output and the negative carry passed to the second adder 804C. In some implementations, an inverter may be provided to invert the negative sum output of the first negative adder 802C to a positive output. In some implementations, an inverter may not be provided, allowing the negative sum output to be provided as an input to the next stage in the adder tree circuit.

[0092] The second negative adder 804C receives the negative sum from the first adder 802B, the negative carry output from the first adder 802C, and a high logic identity input (indicating that the actual sum input is zero). The second negative adder 804C generates the next least significant positive sum output and the positive carry passed to the first negative adder 802D. The first negative adder 802D receives the same negative sum from the first adder 802B, the positive carry output from the second negative adder 804C, and a high logic identity input. The first negative adder 802D generates the most significant positive sum output. The first negative adder 802D receives the same operand input as the second negative adder 804C to maintain two's complement compatibility, as described in this disclosure. In some implementations, an inverter may be provided to invert the negative sum output of the first negative adder 802C to a positive output. In some implementations, an inverter may not be provided, allowing the negative sum output to be used as input to the next stage in the adder tree circuit.

[0093] Figure 9 illustrates a flowchart of an example method 900 for operating one or more adder circuits described in this disclosure. Method 900 or portions thereof may be performed by one or more components of an arithmetic system (e.g., MAC circuit 500 in Figure 5, etc.), one or more adder tree circuits described in this disclosure (e.g., adder tree circuits 200, 300, 400, 800, etc. in Figures 2, 3, 4, and 8), and / or using adder circuits (e.g., adder circuit 100 in Figure 1). It should be noted that method 900 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that additional operations may be provided before, during, and after method 900 in Figure 9, and this disclosure may only briefly describe some other operations.

[0094] In short, method 900 begins with operation 902, which includes the following steps: receiving a first operand and a second operand as input via a first adder circuit of the adder tree circuit. Method 900 continues with operation 904, which includes the following steps: generating a first negative sum value via the first adder circuit, wherein the first negative sum value is the logical inversion of the first operand and the second operand. Method 900 continues with operation 906, which includes the following steps: receiving a negative sum value and an additional operand as input via a second adder circuit of the adder tree circuit. Method 900 continues with operation 908, which includes the following steps: generating a positive sum value as output via the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0095] Referring to operation 902, method 900 may include the following steps: a first adder circuit (e.g., first adder 202A, etc.) of an adder tree circuit (e.g., any one of adder tree circuits 200, 300, 400, 800, etc. in Figures 2, 3, 4, and 8) receives a first operand (e.g., A0, etc.) and a second operand (e.g., B0, etc.) as inputs. The first adder circuit may be a negative full adder (e.g., the first negative full adder 202A of adder tree circuit 200) for processing inputs that are not logically inverted. For example, the first operand and the second operand may be single bits of the input values ​​provided to the first adder circuit (e.g., positive inputs A0 and B0 of input values ​​A and B, respectively). The first adder circuit may also receive carry inputs, such as a level carry input (G). Operands can be transferred from upstream components (such as input registers or the front stage of adder tree circuits) and can be coupled to the first adder circuit via conductive paths or signal lines.

[0096] Referring to operation 904, method 900 may include the following steps: generating a first negative sum value by means of a first adder circuit, wherein the first negative sum value is a logical inversion of a first operand and a second operand. The first negative sum value may be generated by the first adder circuit using its internal logic gates and transistors (e.g., as implemented in the full adder circuit 100 of Figure 1), as described in this disclosure. The first adder circuit may also generate a corresponding negative carry output, which may be transmitted to subsequent adder circuits in the adder tree, as described in conjunction with Figures 2, 3, 4, and 8. In some implementations, the first adder circuit may include up to 24 transistors, as described in conjunction with Figure 1.

[0097] Referring to operation 906, method 900 may include the following steps: receiving a negative sum value and an additional operand as input via a second adder circuit of the adder tree circuit. The second adder circuit may be a negative full adder that processes inverted inputs (e.g., the second negative full adder 204A of adder tree circuit 200). For example, the negative sum value of the first adder circuit may be provided as input, along with the additional operand, to the second adder circuit, which may be another logic inverted input (e.g., another negative sum output of another adder circuit in the adder tree, etc.). In some implementations, the additional operand may include an identity operand (e.g., a logic high or low value) to preserve intermediate values ​​during hierarchical summation. The second adder circuit may receive the input via a conductive path or signal line coupled to the input, as described in this disclosure.

[0098] Referring to operation 908, method 900 may include the following steps: generating a positive sum value as an output by a second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand. The second adder circuit may be a negative adder circuit, thus processing negative values ​​(e.g., active low operands) according to the circuit of Figure 1 to produce a positive (active high) output. For example, a second negative full adder may add the negative sum value from the first adder circuit to the additional operand (e.g., another inverted sum from another carry circuit, a logic high identity signal, etc.) to produce a positive sum output. The negative adder effectively cancels the initial inversion applied by the first adder circuit, thereby obtaining the correct logical sum of the original operands. The positive sum value may then be passed to downstream components, such as subsequent stages of the adder tree or an output register, for further processing.

[0099] One embodiment of this disclosure provides an adder tree apparatus. The adder tree apparatus includes a first adder circuit and a second adder circuit. The first adder circuit receives a first operand and a second operand as inputs to the first adder circuit and generates a negative sum value, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand. The second adder circuit receives the first negative sum value and an additional operand as inputs to the second adder circuit and generates a positive sum value as outputs to the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0100] In some embodiments of this type of adder tree device, one or more of the first adder circuit and the second adder circuit include up to 24 transistors.

[0101] In some embodiments of this type of adder tree device, both the first adder circuit and the second adder circuit contain up to 24 transistors.

[0102] In some embodiments of this type of adder tree device, the adder tree device further includes a third adder circuit. The third adder circuit is used to receive a third operand, a fourth operand, and a carry output from the first adder circuit.

[0103] In some embodiments of the adder tree device of this type, the first adder circuit and the third adder circuit are part of the first stage, and the second adder circuit is part of the second stage.

[0104] In some embodiments of this type of adder tree device, the adder tree device further includes an inverter. The inverter is used to receive the negative sum output generated by the first adder circuit. The third adder circuit is used to receive the carry output via the output of the inverter.

[0105] In some embodiments of the adder tree device of this type, the first operand and the second operand are logically inverted.

[0106] In some embodiments of the adder tree device of this type, the first adder circuit is coupled to the multiplier circuit to receive the first operand and the second operand from the multiplier circuit.

[0107] In some embodiments of this type of adder tree device, the adder tree device further includes a third adder circuit. The third adder circuit is used as part of a third stage and is used to receive a positive sum value as input to the third adder circuit.

[0108] In some embodiments of the adder tree device of this type, the third adder circuit is further configured to receive a logic low input as a second additional operand, and to use the second additional operand to generate a negative sum value as the output of the third adder circuit.

[0109] Another embodiment of this disclosure provides a multiply-accumulate (MAC) circuit. The MAC circuit includes a multiplier circuit and an adder tree circuit. The multiplier circuit generates multiple partial products. The adder tree circuit receives the multiple partial products, generates an intermediate sum corresponding to a first corresponding sum of at least two of the multiple partial products after logical inversion, and generates an output sum based on the intermediate sum and a second operand. The output sum corresponds to a second corresponding sum of the intermediate sum and the second operand after logical inversion.

[0110] In some embodiments of this other type of MAC circuit, the multiplier circuit includes at least one lookup table.

[0111] In some embodiments of this alternative MAC circuit, the adder tree circuit includes multiple adder circuits. Each of the adder circuits includes up to 24 transistors.

[0112] In some embodiments of this other type of MAC circuit, the intermediate sum is generated by a first adder circuit in a plurality of adder circuits and provided as input to a second adder circuit in a plurality of adder circuits having a second operand to generate an output sum.

[0113] In some embodiments of this other type of MAC circuit, the multiply-accumulate circuit further includes a second adder tree circuit. The second adder tree circuit is used to receive the output sum of the adder tree circuit and to generate a second output sum based on the output sum.

[0114] In some embodiments of this other type of MAC circuit, the second operand is a logic high operand. The adder tree circuit is further used to provide the intermediate sum as input to the adder circuit having a logic high operand, and to use the adder circuit to generate the output sum.

[0115] In some embodiments of this other type of MAC circuit, the adder tree circuit is further used to generate at least one of the intermediate sum and carry value via the inverter of the corresponding output of the adder circuit.

[0116] In another embodiment of this disclosure, a method for operating a multiplication-accumulation circuit is provided. The method includes the following steps: receiving a first operand and a second operand as inputs to a first adder circuit of an adder tree circuit; generating a negative sum value by the first adder circuit, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand; receiving the negative sum value and a second value as inputs to a second adder circuit of the adder tree circuit; and generating a positive sum value as the output of the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the second value.

[0117] In some embodiments of the operation method of the multiplication accumulation circuit of the other state, the operation method further includes the following steps: generating a negative carry value by means of a first adder circuit, wherein the negative carry value is the logical inversion of the sum of the first operand and the second operand.

[0118] In some embodiments of the operation method of the multiplication-accumulation circuit of the other state, the operation method further includes the following step: providing a negative carry value to a third adder circuit by means of a first adder circuit.

[0119] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0120] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0121] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a schematic diagram of an example circuit implementing a full adder with an inverting output according to some embodiments; Figure 2 illustrates a schematic diagram of an example adder tree circuit including a full adder circuit with a negative sum output and a negative carry output according to some embodiments; Figure 3 illustrates a schematic diagram of an example adder tree circuit including a full adder circuit with a negative sum output and a positive carry output according to some embodiments; Figure 4 illustrates a schematic diagram of an example adder tree circuit including a full adder circuit with a positive sum output and a negative carry output according to some embodiments; Figure 5 illustrates a schematic diagram of an example multiply-accumulate (MAC) circuit that can implement one or more adder tree circuits described in conjunction with Figures 2, 3, and 4 according to some embodiments; Figure 6 illustrates a schematic diagram of a portion of a multiplier circuit that can be included in the MAC circuit described in conjunction with Figure 5 according to some embodiments. Figure 7 illustrates a schematic diagram of an example adder tree circuit that may include one or more adder tree circuits in conjunction with the MAC circuit described in Figure 5, according to some embodiments; Figure 8 illustrates a schematic diagram of an example two-stage adder tree circuit that includes a full adder circuit with a negative sum output and a negative carry output, according to some embodiments; and Figure 9 illustrates a flowchart of an example method of operating one or more adder circuits described in this disclosure according to some embodiments. [Biomaterial Storage]

[0123] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An adder tree apparatus, comprising: a first adder circuit for: receiving a first operand and a second operand as an input to the first adder circuit; and generating a negative sum value, wherein the negative sum value is a logical inversion of the sum of the first operand and the second operand; and a second adder circuit for: receiving the negative sum value and an additional operand as an input to the second adder circuit; and generating a positive sum value as an output of the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus a logical inversion of the additional operand.

2. The adder tree apparatus as claimed in claim 1, wherein one or more of the first adder circuit and the second adder circuit comprise up to 24 transistors.

3. The adder tree apparatus as claimed in claim 1 further includes a third adder circuit for receiving a third operand, a fourth operand, and a carry output from the first adder circuit.

4. The adder tree apparatus as claimed in claim 3, wherein the first adder circuit and the third adder circuit are part of a first stage, and the second adder circuit is part of a second stage.

5. The adder tree apparatus as claimed in claim 3, further comprising an inverter for receiving a negative sum output generated by the first adder circuit, wherein the third adder circuit is configured to receive the carry output via an output of the inverter.

6. The adder tree apparatus as claimed in claim 1, wherein the first adder circuit is coupled to a multiplier circuit to receive the first operand and the second operand from the multiplier circuit.

7. The adder tree apparatus as claimed in claim 1, further comprising a third adder circuit that is used as part of a third stage and for receiving the positive sum value as an input to the third adder circuit.

8. A multiply-accumulate circuit, comprising: a multiplier circuit for generating a plurality of partial products; and an adder tree circuit for: receiving the plurality of partial products; generating an intermediate sum corresponding to a first corresponding sum of at least two of the plurality of partial products after logical inversion; and generating an output sum based on the intermediate sum and a second operand, wherein the output sum corresponds to a second corresponding sum of the intermediate sum and the second operand after logical inversion.

9. The multiply-accumulate circuit as claimed in claim 8, wherein the multiplier circuit includes at least one lookup table.

10. A method of operating a multiply-accumulate circuit, comprising the following steps: receiving a first operand and a second operand as inputs of a first adder circuit of an adder tree circuit; generating a negative sum value by the first adder circuit, wherein the negative sum value is a logical inversion of the sum of the first operand and the second operand; receiving the negative sum value and a second value as inputs of a second adder circuit of the adder tree circuit; and generating a positive sum value as an output of the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus a logical inversion of the second value.

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