Instruction Distributor

Abstract

This application discloses an instruction distributor comprising: a load control module for responding to instruction requests from one or more processing elements (PEs) and formulating a scheduling strategy for scheduling instructions based on link serial information from a double data rate storage device (DDR), the link serial information including a single instruction multiple thread (SIMT) mode and a multiple instruction multiple thread (MIMT) mode for dividing instructions into instruction blocks; a request arbitrator for generating corresponding scheduling information for the SIMT mode and MIMT mode based on the scheduling strategy; a direct memory access (DMA) controller for controlling the DMA module to load instruction information from the DDR according to the scheduling information; an instruction decision module for analyzing the instruction information to obtain instructions; and an L2 cache for distributing instructions received from the instruction decision module to one or more PEs.

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