Memory access instruction reordering

Abstract

An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry. The processing circuitry imposes an ordering requirement on one or more memory access instructions to prevent said one or more memory access instructions being reordered with respect to an ordering instruction. In response to an ordering limit hint instruction associated with a given ordering instruction, the processing circuitry relaxes the ordering requirement for a memory access instruction for which the ordering limit hint instruction appears in program order between the memory access instruction and the given ordering instruction.

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