Interrupt translation

Abstract

An apparatus comprises base address registers, each corresponding to a respective one of a plurality of interrupt domains. Interrupt translation circuitry detects a given incoming event received from an interrupt source, indicative of a source interrupt domain associated with the interrupt source and a target interrupt domain for which an interrupt event is to be signalled to a target processor. When the source interrupt domain is different to the target interrupt domain, the interrupt translation circuitry determines, based on cross-domain interrupt permission information associated with the target interrupt domain, whether the given incoming event is permitted to be translated for the target interrupt domain when associated with the source interrupt domain, and if so translates the given incoming event into the interrupt event based on mapping information specified in a target domain interrupt translation control structure accessed using a base address from the base address register corresponding to the target interrupt domain.

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