Interrupt management
TW202634436APending Publication Date: 2026-08-16ARM LTD
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Patent Information
- Application Number
- TW115105167
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-14
- Filing Date
- 2026-02-10
- Publication Date
- 2026-08-16
Smart Images
Figure TWG2TA001073495_001 
Figure TWG2TA001073495_002 
Figure TWG2TA001073495_003
Abstract
An apparatus comprises processing circuitry configured to perform data processing, and instruction decoding circuitry configured to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to one or more types of memory access instruction associated with a target address to control the processing circuitry to perform an access to a location associated with the target address. The instruction decoding circuitry is responsive to an interrupt management instruction identifying an interrupt management operation to control the processing circuitry to perform the interrupt management operation. The interrupt management instruction has a different instruction encoding from the one or more types of memory access instruction.
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