Decode control method, memory storage device and memory control circuit unit

Abstract

A decode control method, a memory storage device and a memory control circuit unit are provided. The decode control method includes: in response to a first decoding operation performed according to a writing data and a first parity data is failing, reading a second parity data; performing a second decoding operation according to the second parity data; in response to the second decoding operation is successful, increasing a log likelihood ratio corresponding to the second parity data; and performing a third decoding operation according to the writing data, the first parity data, and the second parity data.

Description

[Technical Field]

[0001] This invention relates to a memory management technology, and more particularly to a decoding control method, a memory storage device, and a memory control circuit unit. [Previous Technology]

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, to maintain data reliability, data is encoded to generate corresponding error correction codes before being stored in a rewritable non-volatile memory module. These error correction codes are then stored in the rewritable non-volatile memory module along with the corresponding data. Subsequently, when data is read from the rewritable non-volatile memory module, the corresponding error correction codes can be used to correct any errors that may exist in the data. Improving the ability to perform decoding operations based on data read from a rewritable non-volatile memory module is one of the key issues of concern to those skilled in the art. [Summary of the Invention]

[0004] The present invention provides a decoding control method, a memory storage device, and a memory control circuit unit, which can improve decoding capabilities.

[0005] An exemplary embodiment of the present invention provides a decoding control method for a rewritable non-volatile memory module, the decoding control method comprising: reading second parity data in response to a first decoding operation performed based on written data and first parity data failing; performing a second decoding operation based on the second parity data; increasing the log-probability ratio corresponding to the second parity data in response to the second decoding operation succeeding; and performing a third decoding operation based on the written data, the first parity data, and the second parity data.

[0006] In an exemplary embodiment of the present invention, the decoding control method further includes: in response to the first decoding operation failing, reducing the log probability ratio corresponding to the written data and the log probability ratio corresponding to the first odd-even data.

[0007] In an exemplary embodiment of the present invention, the decoding control method further includes: reading third parity data in response to the failure of the third decoding operation; performing a fourth decoding operation based on the third parity data; increasing the log-probability ratio corresponding to the third parity data in response to the success of the fourth decoding operation; and performing a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

[0008] In an exemplary embodiment of the present invention, the decoding control method further includes: recording the decoding results of the first decoding operation and the second decoding operation; and adjusting the logarithmic probability ratio based on the decoding results.

[0009] An exemplary embodiment of the present invention provides a decoding control method for a rewritable non-volatile memory module, the decoding control method comprising: performing a decoding operation based on serial data; and in the decoding operation, performing the decoding operation on a first portion of the serial data using a first logarithmic probability ratio, and performing the decoding operation on a second portion of the serial data using a second logarithmic probability ratio, wherein the first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table, wherein the second portion has been decoded successfully before the decoding operation is performed.

[0010] In an exemplary embodiment of the present invention, the first part has been decoded and the decoding failed before the decoding operation is performed.

[0011] In an exemplary embodiment of the present invention, the first portion and the second portion are read from different entity units.

[0012] An exemplary embodiment of the present invention further provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. In response to a failure of a first decoding operation performed based on written data and first parity data, the memory control circuit unit is configured to read second parity data. In response to a success of the second decoding operation, the memory control circuit unit is further configured to increase the log-probability ratio corresponding to the second parity data. The memory control circuit unit includes a decoding circuit. The decoding circuit is configured to perform a second decoding operation based on the second parity data. The decoding circuit is further configured to perform a third decoding operation based on the written data, the first parity data, and the second parity data.

[0013] In an exemplary embodiment of the present invention, in response to the failure of the first decoding operation, the memory control circuit unit is further configured to reduce the log probability ratio corresponding to the written data and the log probability ratio corresponding to the first odd-even data.

[0014] In an exemplary embodiment of the present invention, in response to the failure of the third decoding operation, the memory control circuit unit is further configured to read the third parity data. In response to the success of the fourth decoding operation, the memory control circuit unit is further configured to increase the log-probability ratio corresponding to the third parity data. The decoding circuit is further configured to perform the fourth decoding operation based on the third parity data. The decoding circuit is further configured to perform a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to record the decoding results of the first decoding operation and the second decoding operation. The memory control circuit unit is further configured to adjust the logarithmic probability ratio value according to the decoding results.

[0016] An exemplary embodiment of the present invention further provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a decoding circuit. The decoding circuit is configured to perform a decoding operation based on serial data. In the decoding operation, the decoding circuit is further configured to perform the decoding operation on a first portion of the serial data using a first logarithmic probability ratio, and to perform the decoding operation on a second portion of the serial data using a second logarithmic probability ratio. The first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table. Before performing the decoding operation, the second portion has been decoded successfully.

[0017] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, a decoding circuit, and a memory management circuit. The host interface is coupled to a connection interface unit. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the decoding circuit. In response to a failure of a first decoding operation performed based on written data and first parity data, the memory management circuit reads second parity data. In response to a success of the second decoding operation, the memory management circuit further increases the log-probability ratio corresponding to the second parity data. The decoding circuit performs the second decoding operation based on the second parity data. The decoding circuit further performs a third decoding operation based on the written data, the first parity data, and the second parity data.

[0018] In an exemplary embodiment of the present invention, in response to the failure of the first decoding operation, the memory management circuit is further configured to reduce the log probability ratio corresponding to the written data and the log probability ratio corresponding to the first parity data.

[0019] In an exemplary embodiment of the present invention, in response to the failure of the third decoding operation, the memory management circuit is further configured to read the third parity data. In response to the success of the fourth decoding operation, the memory management circuit is further configured to increase the log-probability ratio corresponding to the third parity data. The decoding circuit is further configured to perform the fourth decoding operation based on the third parity data. The decoding circuit is further configured to perform a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to record the decoding results of the first decoding operation and the second decoding operation. The memory management circuit is further configured to adjust the logarithmic probability ratio based on the decoding results.

[0021] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, a decoding circuit, and a memory management circuit. The host interface is coupled to a connection interface unit. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the decoding circuit. The decoding circuit is used to perform a decoding operation based on serial data. In the decoding operation, the decoding circuit is further used to perform the decoding operation on a first portion of the serial data using a first logarithmic probability ratio, and to perform the decoding operation on a second portion of the serial data using a second logarithmic probability ratio. The first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table. Before performing the decoding operation, the second portion has been decoded successfully.

[0022] Based on the above, the decoding control method, memory storage device and memory control circuit unit of the present invention can dynamically adjust the reliability information (i.e., the logarithmic probability ratio) according to the decoding result to improve the decoding capability.

Implementation Method

[0023] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0024] FIG1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. FIG2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention.

[0025] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0026] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0027] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0028] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0029] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0030] FIG3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0031] FIG4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0032] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0033] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0034] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0035] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in that memory cell.

[0036] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in MLC NAND flash memory, the write rate of lower physical programming units is greater than that of upper physical programming units, and / or the reliability of lower physical programming units is higher than that of upper physical programming units.

[0037] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0038] FIG5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0039] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0040] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0041] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory management circuit 51 has a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0042] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit processes data to be written to and read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0043] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0044] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0045] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0046] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0047] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0048] In one exemplary embodiment, the rewritable non-volatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0049] FIG6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0050] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0051] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0052] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In an exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logic addresses.

[0053] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0054] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0055] In one exemplary embodiment, the error checking and correction circuit 54 may include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 is used to encode data. The decoding circuit 542 is used to decode data. In one exemplary embodiment, the encoding circuit 541 and the decoding circuit 542 may also be combined into a single encoding / decoding circuit.

[0056] In one exemplary embodiment, the error checking and correction circuit 54 may support low-density parity-check (LDPC) codes. For example, the error checking and correction circuit 54 may use low-density parity-check codes to decode and encode data. Those skilled in the art should understand how to use low-density parity-check codes for decoding and encoding, and will not be described in detail here. In another exemplary embodiment, the error checking and correction circuit 54 may also support BCH codes, convolutional codes, or turbo codes, without limitation by the present invention.

[0057] In an exemplary embodiment, the error checking and correction circuit 54 (or decoding circuit 542) can decode data read from a physical cell in the rewritable non-volatile memory module 43 to attempt to correct errors in the data. Assuming the bit error rate (BER) of the data is low, the error checking and correction circuit 544 (or decoding circuit 542) can decode the data based on hard decoding mode to attempt to quickly correct a small number of errors in the data. Assuming the bit error rate of the data is high, the error checking and correction circuit 54 (or decoding circuit 542) can decode the data based on soft decoding mode to improve the decoding success rate of the data. Further, in hard decoding mode, the memory management circuit 51 only needs to read the hard bits corresponding to each memory cell from this physical cell, and the error checking and correction circuit 54 (or decoding circuit 542) can decode based on the aforementioned hard bits. In addition, in the soft decoding mode, the memory management circuit 51 needs to read one hard bit and multiple soft bits corresponding to a single memory cell from this physical unit at the same time. The error checking and correction circuit 54 (or decoding circuit 542) can perform decoding based on the aforementioned hard bits and soft bits.

[0058] In general, the soft decoding mode requires more data (i.e., soft bits) to assist decoding than the hard decoding mode in order to improve the success rate of decoding this data.

[0059] Figure 7 is a schematic diagram illustrating the critical voltage distribution of a first physical cell and the use of multiple read voltage levels to read the first physical cell according to an exemplary embodiment of the present invention. Referring to Figure 7, assume that the first physical cell includes multiple memory cells, and the critical voltage distribution of these memory cells includes states 701 and 702. For example, state 701 corresponds to bit "1", and state 702 corresponds to bit "0". That is, if the critical voltage of a memory cell belongs to state 701, it means that this memory cell is used to store bit "1". If the critical voltage of a memory cell belongs to state 702, it means that this memory cell is used to store bit "0". It should be noted that states 701 and 702 may also correspond to other bits or combinations of bits, which is not limited by the present invention.

[0060] It should be noted that the overlapping area between states 701 and 702 will expand with the degree of use (or wear) of the rewritable non-volatile memory module 43, thereby reducing the accuracy of determining whether a memory cell belongs to state 701 or state 702. For example, when the overlapping area expands, after applying the read voltage level V(HB) to the first physical unit, the critical voltage of a memory cell that originally belonged to state 701 will be greater than the read voltage level V(HB), so this memory cell will be misjudged as belonging to state 702 (that is, the bits stored in this memory cell will be misjudged as bit "0"). For example, when the overlapping area expands, after applying the read voltage level V(HB) to the first physical unit, the critical voltage of a memory cell that originally belonged to state 702 will be less than the read voltage level V(HB), so this memory cell will be misjudged as belonging to state 701 (that is, the bits stored in this memory cell will be misjudged as bit "1"). At this time, the data read from the first physical unit may have a large number of erroneous bits. The error checking and correction circuit 54 (or decoding circuit 542) can decode this data based on the soft decoding mode, thereby improving the decoding success rate of this data.

[0061] In an exemplary embodiment, in soft decoding mode, memory management circuitry 51 may send at least one read instruction sequence to rewritable nonvolatile memory module 43. The read instruction sequence may instruct rewritable nonvolatile memory module 43 to read data in the first physical cell based on multiple read voltage levels. Specifically, the multiple read voltage levels may include read voltage level V(HB) and read voltage levels V(SB1) to V(SB4) of FIG. 7. The data read from the first physical cell may include hard bit HB, soft bit SB(1), and soft bit SB(2) of FIG. 7.

[0062] In an exemplary embodiment, the rewritable non-volatile memory module 43 can sequentially apply read voltage level V(HB) and read voltage levels V(SB1) to V(SB4) to a memory cell in the first physical unit to obtain the read result of the memory cell, and accordingly send back the hard bit HB, soft bit SB(1) and soft bit SB(2) to the memory management circuit 51. For example, the hard bit HB can reflect the read result of the memory cell using the read voltage level V(HB). If the threshold voltage of the memory cell is lower than the read voltage level V(HB), the rewritable non-volatile memory module 43 can send back the hard bit HB with a bit value of "1" to the memory management circuit 51. Conversely, if the threshold voltage of the memory cell is higher than the read voltage level V(HB), the rewritable non-volatile memory module 43 can send back the hard bit HB with a bit value of "0" to the memory management circuit 51. Similarly, soft bits SB(1) and SB(2) can reflect the reading results of this memory cell using the reading voltage levels V(SB1) to V(SB4).

[0063] In an exemplary embodiment, the read voltage levels V(SB1) to V(SB4) can be divided into multiple voltage intervals 711 to 716. For example, voltage interval 712 is between read voltage levels V(SB1) and V(SB3), and so on. The hard bit HB, soft bit SB(1), and soft bit SB(2) obtained by reading a memory cell can reflect the voltage interval (e.g., voltage interval 712) where the critical voltage of this memory cell is located. To further explain, assuming that the hard bit HB, soft bit SB(1), and soft bit SB(2) obtained by reading a memory cell are "110", it reflects that the critical voltage of this memory cell is located in voltage interval 712. The number of read voltage levels V(SB1) to V(SB4) and the number of voltage intervals 711 to 716 can be designed according to actual needs, and the present invention does not limit them.

[0064] In one exemplary embodiment, the error checking and correction circuit 54 supporting low-density parity checking can use reliability information to perform the decoding operation. The reliability information may be, for example, the Log Likelihood Ratio (LLR). Specifically, in the decoding operation, the error checking and correction circuit 54 (or the decoding circuit 542) can use the LLR to decode the data read by the memory management circuit 51. In another exemplary embodiment, the error checking and correction circuit 54 (or the decoding circuit 542) may also use other types of reliability information to perform the decoding operation; this invention is not limited thereto.

[0065] In an exemplary embodiment, the larger the absolute value of the logarithmic probability ratio (which may be positive or negative) corresponding to a piece of data (or a bit value), the higher the reliability of the data, meaning that the bit value of the data has a high probability of being correct. Conversely, the smaller the absolute value of the logarithmic probability ratio corresponding to the data, the lower the reliability of the data, meaning that the bit value of the data has a high probability of being incorrect. For example, when the logarithmic probability ratio is 0, it means that the probability of the corresponding data (or bit value) being 0 is the same as the probability of it being 1. For example, when the logarithmic probability ratio is positive and the larger the value, the higher the probability that the corresponding data (or bit value) is 0. For example, when the logarithmic probability ratio is negative and the smaller the value, the higher the probability that the corresponding data (or bit value) is 1. If the data has a high probability of being incorrect, the decoding circuit 542 can correct this error during the decoding operation, that is, change the bit value of the data. In one exemplary embodiment, the range of the logarithmic probability ratio is determined by the bit width supported by the decoding circuit 542 of the error checking and correction circuit 54. For example, with a bit width of 5 bits, the range of the logarithmic probability ratio is -15 to +15.

[0066] It should be noted that as the usage time and frequency of the rewritable non-volatile memory module 43 increase, the wear and tear, read count, erase count, and other variables of each physical unit in the rewritable non-volatile memory module 43 will vary. In other words, the reliability of each physical unit will also vary. Therefore, the logarithmic probability ratios corresponding to the data stored in different physical units may be derived from different lookup tables.

[0067] Figure 8 is a schematic diagram of a first lookup table corresponding to a first entity unit according to an exemplary embodiment of the present invention. Referring to Figure 8, the first lookup table 81 can be used to record hard bits HB, soft bits SB(1), soft bits SB(2), and logarithmic probability ratios LLR(1) to LLR(6) corresponding to each voltage range 711 to 716. In an exemplary embodiment, it is assumed that the bit width supported by the decoding circuit 542 is 5 bits, and the range of the logarithmic probability ratios LLR(1) to LLR(6) is -15 to +15.

[0068] In one exemplary embodiment, the memory management circuit 51 may update (or adjust) the reliability information (i.e., log probability ratio) corresponding to the data based on the decoding result of the decoding operation for a certain data.

[0069] In one exemplary embodiment, before the memory management circuit 51 writes data into the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data, and the data and parity data are then stored in the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 wants to read a physical cell, it can read the data and its corresponding parity data from the physical cell. The decoding circuit 542 in the error checking and correction circuit 54 can perform a decoding operation based on the data and parity data read from the physical cell to detect and correct errors in the data.

[0070] In one exemplary embodiment, memory management circuit 51 acquires write data. Encoding circuit 541 can perform an encoding operation based on the write data to generate first parity data and second parity data. In one exemplary embodiment, the second parity data is generated based on the write data and the first parity data. Specifically, encoding circuit 541 can perform an encoding operation based on the write data to generate the first parity data, and encoding circuit 541 can further perform another encoding operation based on the write data and the first parity data to generate the second parity data. In another exemplary embodiment, the second parity data is not generated based on the first parity data. Specifically, encoding circuit 541 may, for example, have a first encoding circuit (not shown) and a second encoding circuit (not shown) that operate independently of each other. The first encoding circuit in encoding circuit 541 can perform the first encoding operation based on the write data to generate the first parity data, and the second encoding circuit in encoding circuit 541 can perform the second encoding operation based on the write data to generate the second parity data. In addition, the first parity data can be decoded alone or in combination with the second parity data and the write data. The second odd / even data cannot be decoded separately from the written data.

[0071] After encoding and writing data, the memory management circuit 51 may send a write instruction sequence (also referred to as the first write instruction sequence) to the rewritable non-volatile memory module 43. The first write instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to store the written data, the first parity data, and the second parity data. In an exemplary embodiment, the memory management circuit 51 may store the written data and the first parity data in the same physical unit (e.g., the first physical unit), and store the second parity data in another physical unit (also referred to as the second physical unit).

[0072] In one exemplary embodiment, the encoding circuit 541 may perform an encoding operation based on the written data to generate third parity data. In one exemplary embodiment, the third parity data is generated based on the written data, the first parity data, and the second parity data. Specifically, after the encoding circuit 541 sequentially generates the first parity data and the second parity data, the encoding circuit 541 may further perform an encoding operation based on the written data, the first parity data, and the second parity data to generate the third parity data. In another exemplary embodiment, the third parity data is not generated based on the first parity data and the second parity data. Specifically, the encoding operation may further include a third encoding operation. In addition to the first encoding circuit and the second encoding circuit described above, the encoding circuit 541 may further include a third encoding circuit (not shown). The third encoding circuit in the encoding circuit 541 may perform the third encoding operation based on the written data to generate the third parity data. Furthermore, the first parity data may be decoded alone, in combination with the second parity data, or in combination with the second parity data and the third parity data, along with the written data. The second parity data needs to be used in conjunction with the first parity data and the written data to perform a decoding operation. The third parity data needs to be used in conjunction with the first parity data, the second parity data, and the written data to perform a decoding operation.

[0073] After encoding and writing data, the memory management circuit 51 may send a write instruction sequence (also referred to as a second write instruction sequence) to the rewritable non-volatile memory module 43. The second write instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to store the written data, the first parity data, the second parity data, and the third parity data. In an exemplary embodiment, the memory management circuit 51 may store the written data and the first parity data in the same physical unit (i.e., the first physical unit), and store the second parity data and the third parity data in another physical unit (i.e., the second physical unit). In an exemplary embodiment, the second parity data and the third parity data are stored in different physical units, wherein the physical unit used to store the third parity data is also referred to as the third physical unit.

[0074] Subsequently, the memory management circuit 51 may send at least one read instruction sequence to the rewritable non-volatile memory module 43. The read instruction sequence may instruct the rewritable non-volatile memory module 43 to read data from a specific physical cell. When reading the written data from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read first parity data (and second and third parity data) from the rewritable non-volatile memory module 43. The decoding circuit 542 may perform a decoding operation based on the first parity data (and second and third parity data) and the written data read from the rewritable non-volatile memory module 43 to detect and correct errors in the written data.

[0075] It should be noted that when reading the written data from the rewritable non-volatile memory module 43, the memory management circuit 51 may read the first parity data first, and in the case where a higher error correction capability is required (i.e., the first parity data fails to be decoded), the second parity data (and the third parity data) may be read depending on the decoding situation to improve the decoding speed.

[0076] In other words, the error checking and correction circuit 54 can perform an iterative decoding operation. An iterative decoding operation is used to decode a piece of data from the rewritable non-volatile memory module 43. In the iterative decoding operation, the parity checking operation for checking the correctness of the data and the decoding operation for correcting errors in the data can be repeated and alternately executed until decoding is successful or the number of iterations reaches a predetermined number. If the number of iterations reaches the predetermined number, it indicates that decoding has failed. If decoding is successful, the error checking and correction circuit 54 can stop the decoding operation and output the successfully decoded data.

[0077] In an exemplary embodiment, when reading the written data from the rewritable non-volatile memory module 43, the error checking and correction circuit 54 (or decoding circuit 542) may first decode the written data and the first parity data based on a preset reliability information (i.e., logarithmic probability ratio) in a hard decoding mode. If decoding fails, the error checking and correction circuit 54 (or decoding circuit 542) may switch to a soft decoding mode using an updated (or adjusted) logarithmic probability ratio to decode the written data, the first parity data, and the second parity data (and the third parity data) to improve the decoding success rate.

[0078] Figure 9 is a schematic diagram illustrating the decoding process according to an exemplary embodiment of the present invention. Referring to Figure 9, it is assumed that the first parity data P(1), the second parity data P(2), and the third parity data P(3) are all generated by encoding the write data 901 stored in the rewritable non-volatile memory module 43. The relevant operational details have been described above and will not be repeated here.

[0079] In an exemplary embodiment, the memory management circuit 51 may send a first read instruction sequence to the rewritable non-volatile memory module 43 to read write data 901 and first parity data P(1) from the rewritable non-volatile memory module 43. When the memory management circuit 51 reads write data 901 and first parity data P(1) from the rewritable non-volatile memory module 43, the memory management circuit 51 also obtains the logarithmic probability ratio corresponding to write data 901 and the logarithmic probability ratio corresponding to first parity data P(1). In an exemplary embodiment, the memory management circuit 51 may obtain the logarithmic probability ratio by looking up a table. Specifically, since write data 901 and first parity data P(1) are stored in the same physical unit (i.e., the first physical unit), the memory management circuit may obtain the logarithmic probability ratio corresponding to write data 901 and first parity data P(1) from the first lookup table 81 corresponding to the first physical unit. Since the written data 901 and the first parity data P(1) have not been decoded, the memory management circuit 51 can obtain the preset logarithmic probability ratio from the first lookup table 81.

[0080] Subsequently, the error checking and correction circuit 54 can perform a decoding operation (also known as a first decoding operation) based on the written data 901 and the first parity data P(1). Specifically, the memory management circuit 51 can provide the obtained logarithmic probability ratio (i.e., the logarithmic probability ratio corresponding to the written data 901 and the first parity data P(1)) to the error checking and correction circuit 54. Accordingly, the decoding circuit 542 of the error checking and correction circuit 54 can use the logarithmic probability ratio provided by the memory management circuit 51 to perform the first decoding operation on the written data 901 and the first parity data P(1) to improve decoding efficiency.

[0081] If decoding is successful (meaning the first decoding operation is successful), the error checking and correction circuit 54 can stop the decoding operation and output the data indicating successful decoding.

[0082] On the other hand, if decoding fails (i.e., the first decoding operation fails), the memory management circuit 51 can send a second read instruction sequence to the rewritable non-volatile memory module 43 to read the second parity data P(2) from the rewritable non-volatile memory module 43. When the memory management circuit 51 reads the second parity data P(2) from the rewritable non-volatile memory module 43, the memory management circuit 51 also obtains the logarithmic probability ratio corresponding to the second parity data P(2). Specifically, since the second parity data P(2) and the written data 901 (and the first parity data P(1)) are stored in different physical units (i.e., the second physical unit), the memory management circuit 51 can obtain the logarithmic probability ratio corresponding to the second parity data P(2) from a second lookup table corresponding to the second physical unit, wherein the second lookup table is different from the aforementioned first lookup table 81. The contents recorded in the second lookup table are similar to those in the first lookup table 81, and will not be repeated here. Since the second odd-even data P(2) has not been decoded, the memory management circuit 51 can obtain the preset logarithmic probability ratio from the second lookup table.

[0083] Next, the decoding circuit 542 can perform a decoding operation (also called a second decoding operation) based on the second parity data P(2). Specifically, the memory management circuit 51 can provide the obtained logarithmic probability ratio (i.e., the logarithmic probability ratio corresponding to the second parity data P(2)) to the error checking and correction circuit 54. Accordingly, the decoding circuit 542 of the error checking and correction circuit 54 can use the logarithmic probability ratio provided by the memory management circuit 51 to perform a second decoding operation on the second parity data P(2) to improve decoding efficiency.

[0084] If decoding fails (i.e., the second decoding operation fails), the memory management circuit 51 may reduce the log-probability ratio corresponding to the second parity data P(2). In an exemplary embodiment, the memory management circuit 51 may record a decoding result of a decoding operation (e.g., a first decoding operation and / or a second decoding operation) and adjust the log-probability ratio based on the decoding result. Specifically, since the first decoding operation fails, the memory management circuit 51 may reduce the log-probability ratio corresponding to the written data 901 and the log-probability ratio corresponding to the first parity data P(1). Similarly, since the second decoding operation also fails, the memory management circuit 51 may reduce the log-probability ratio corresponding to the second parity data P(2). Accordingly, the decoding circuit 542 may use the reduced log-probability ratio to perform decoding operations on the written data 901, the first parity data P(1), and the second parity data P(2) to improve decoding efficiency. It is worth mentioning that by increasing the data length of the parity data (that is, merging the first parity data P(1) and the second parity data P(2) into parity data P(12)), the decoding circuit 542 can improve its error correction capability for the written data 901.

[0085] On the other hand, if decoding is successful (i.e., the second decoding operation is successful), the memory management circuit 51 can increase the logarithmic probability ratio corresponding to the second parity data P(2). Specifically, the memory management circuit 51 can adjust the logarithmic probability ratio according to the decoding result. Since the second decoding operation for the second parity data P(2) is successful (i.e., the second parity data P(2) is correct), the memory management circuit 51 can increase the logarithmic probability ratio corresponding to the second parity data P(2) (e.g., "1001") to "-15, +15, +15, -15". In addition, since the first decoding operation fails, the memory management circuit 51 can decrease the logarithmic probability ratio corresponding to the written data 901 and the logarithmic probability ratio corresponding to the first parity data P(1).

[0086] Accordingly, the decoding circuit 542 can use the adjusted logarithmic probability ratio to perform decoding operations (i.e., the third decoding operation) on the written data 901, the first parity data P(1) and the second parity data P(2) to improve decoding efficiency.

[0087] From the perspective of the decoding circuit 542, the written data 901, the first parity data P(1), and the second parity data P(2) can be regarded as a serial data. Assuming that the written data 901 is "1010", the first parity data P(1) is "1100" and the second parity data P(2) is "1001", then the serial data is "101011001001". Since the written data 901 and the first parity data P(1) are stored in the same physical unit (i.e., the first physical unit), the written data 901 and the first parity data P(1) can be regarded as the first part of the serial data (i.e., the first 8 bits of the serial data "10101100"). Similarly, since the second parity data P(2) and the written data 901 (and the first parity data P(1)) are stored in different physical units (i.e., the second physical unit), the second parity data P(2) can be regarded as the second part of the serial data (i.e., the last 4 bits "1001" of the serial data). That is, the decoding circuit 542 can perform a decoding operation (i.e., a third decoding operation) based on the serial data.

[0088] In an exemplary embodiment, the decoding circuit 542 may perform a third decoding operation on the first portion using a first logarithmic probability ratio, and perform a third decoding operation on the second portion using a second logarithmic probability ratio. The logarithmic probability ratio corresponding to the written data 901 and the first odd-even data P(1) is the first logarithmic probability ratio, and the logarithmic probability ratio corresponding to the second odd-even data P(2) is the second logarithmic probability ratio. As mentioned above, the logarithmic probability ratio corresponding to the written data 901 and the first odd-even data P(1) originates from the first lookup table 81, and the logarithmic probability ratio corresponding to the second odd-even data P(2) originates from the second lookup table. That is, the first logarithmic probability ratio originates from the first lookup table 81, and the second logarithmic probability ratio originates from the second lookup table.

[0089] Here, the first part has been decoded and the decoding failed (i.e., the first decoding operation failed), and the second part has been decoded and the decoding succeeded (i.e., the second decoding operation succeeded). The decoding circuit 542 can use the reduced first logarithmic probability ratio to perform a third decoding operation on the written data 901 and the first parity data P(1), and use the increased second logarithmic probability ratio to perform a third decoding operation on the second parity data P(2) to improve decoding efficiency.

[0090] If decoding is successful (meaning the third decoding operation is successful), the error checking and correction circuit 54 can stop the decoding operation and output the data indicating successful decoding.

[0091] On the other hand, if decoding fails (i.e., the third decoding operation fails), the memory management circuit 51 may send a third read instruction sequence to the rewritable non-volatile memory module 43 to read the third parity data P(3) from the rewritable non-volatile memory module 43. When the memory management circuit 51 reads the third parity data P(3) from the rewritable non-volatile memory module 43, the memory management circuit 51 also obtains the logarithmic probability ratio corresponding to the third parity data P(3). Specifically, since the third parity data P(3) and the second parity data P(2) and the written data 901 (and the first parity data P(1)) are stored in different physical units (i.e., the third physical unit), the memory management circuit 51 may obtain the logarithmic probability ratio corresponding to the third parity data P(3) from the third lookup table corresponding to the physical unit used to store the third parity data P(3), wherein the third lookup table is different from the aforementioned first lookup table and second lookup table. The contents of the third lookup table are similar to those of the first lookup table 81, so they will not be repeated here.

[0092] Next, the decoding circuit 542 can perform a decoding operation (also known as a fourth decoding operation) based on the third odd data P(3). Specifically, the decoding circuit 542 of the error checking and correction circuit 54 can use the log probability ratio corresponding to the third odd data P(3) to perform a fourth decoding operation on the third odd data P(3) to improve decoding efficiency.

[0093] If decoding fails (i.e., the fourth decoding operation fails), the memory management circuit 51 may reduce the log-probability ratio corresponding to the third parity data P(3). In an exemplary embodiment, the memory management circuit 51 may record the decoding result of the decoding operation and adjust the log-probability ratio accordingly. Specifically, since the third decoding operation fails, the memory management circuit 51 further reduces the log-probability ratio corresponding to the written data 901 and the log-probability ratio corresponding to the first parity data P(1). Similarly, since the fourth decoding operation also fails, the memory management circuit 51 may reduce the log-probability ratio corresponding to the third parity data P(3). Accordingly, the decoding circuit 542 may use the reduced log-probability ratio to perform decoding operations on the written data 901, the first parity data P(1), the second parity data P(2), and the third parity data P(3) to improve decoding efficiency. Here, the decoding circuit 542 can combine the first odd data P(1), the second odd data P(2) and the third odd data P(3) into odd data P(13), and perform a decoding operation based on the written data 901 and the odd data P(13) to improve the error correction capability of the written data 901.

[0094] On the other hand, if decoding is successful (i.e., the fourth decoding operation is successful), the memory management circuit 51 can increase the logarithmic probability ratio corresponding to the third parity data P(3). Taking the range of the logarithmic probability ratio as -15 to +15 as an example, assuming the third parity data P(3) is "1001", then the logarithmic probability ratio corresponding to the third parity data P(3) is "-15, +15, -15, +15". In addition, since the third decoding operation failed, the memory management circuit 51 again decreases the logarithmic probability ratio corresponding to the written data 901 and the logarithmic probability ratio corresponding to the first parity data P(1).

[0095] Accordingly, the decoding circuit 542 can use the adjusted logarithmic probability ratio to perform decoding operations (i.e., the fifth decoding operation) on the written data 901, the first odd data P(1), the second odd data P(2), and the third odd data P(3) to improve decoding efficiency. It is worth mentioning that the decoding circuit 542 can combine the first odd data P(1), the second odd data P(2), and the third odd data P(3) into a longer data length odd data P(13), and perform the fifth decoding operation based on the written data 901 and the odd data P(13) to improve the error correction capability of the written data 901.

[0096] The subsequent operations for the fifth decoding operation as successful or unsuccessful can be referred to, for example, the subsequent operations for the third decoding operation as successful or unsuccessful, and will not be elaborated here.

[0097] It should be noted that, in an exemplary embodiment, if the third decoding operation fails, the memory management circuit 51 may not adjust the logarithmic probability ratio corresponding to the written data 901 and the logarithmic probability ratio corresponding to the first odd-even data P(1). That is, the memory management circuit 51 may only adjust (i.e., increase) the logarithmic probability ratio of the successfully decoded data, thereby improving the decoding capability.

[0098] It should be noted that Figure 9 uses parity data P(1)~P(3) as an example. In an exemplary embodiment, the encoding circuit 541 can also perform more encoding operations on the written data 901 to generate more parity data. Accordingly, when decoding the written data 901 in the subsequent process, in response to decoding failure, more parity data can be used to extend the parity data P(1) to effectively improve the decoding success rate of the written data 901.

[0099] FIG10 is a flowchart illustrating a decoding control method according to an exemplary embodiment of the present invention. Referring to FIG10, in step S1001, a decoding operation is performed based on serial data. In step S1002, in the decoding operation, a first logarithmic probability ratio is used to perform a decoding operation on a first portion of the serial data, and a second logarithmic probability ratio is used to perform a decoding operation on a second portion of the serial data, wherein the first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table, wherein the second portion has been decoded successfully before the decoding operation is performed.

[0100] FIG11 is a flowchart illustrating a decoding control method according to an exemplary embodiment of the present invention. Referring to FIG11, in step S1101, in response to the failure of the first decoding operation performed based on the written data and the first parity data, the second parity data is read. In step S1102, a second decoding operation is performed based on the second parity data. In step S1103, in response to the success of the second decoding operation, the log-probability ratio corresponding to the second parity data is increased. In step S1104, a third decoding operation is performed based on the written data, the first parity data, and the second parity data.

[0101] However, the steps in Figures 10 and 11 have been described in detail above, and will not be repeated here. It is worth noting that the steps in Figures 10 and 11 can be implemented as multiple programs or circuits, and the present invention is not limited thereto. In addition, the methods in Figures 10 and 11 can be used in conjunction with the above exemplary embodiments, or they can be used alone, and the present invention is not limited thereto.

[0102] In summary, the exemplary embodiments of the present invention can effectively improve decoding capabilities by recording the decoding results of each decoding operation and dynamically adjusting reliability information (i.e., the log-probability ratio) based on the decoding results. Furthermore, the exemplary embodiments of the present invention can also store multiple parity data in different entity units to improve decoding capabilities based on the different reliability characteristics of the different entity units.

[0103] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0104] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7 is a schematic diagram of the critical voltage distribution of a first physical cell and the use of multiple read voltage levels to read the first physical cell according to an exemplary embodiment of the present invention. Figure 8 is a schematic diagram of a first lookup table corresponding to the first physical cell according to an exemplary embodiment of the present invention. Figure 9 is a schematic diagram of a decoding process according to an exemplary embodiment of the present invention. Figure 10 is a flowchart of a decoding control method according to an exemplary embodiment of the present invention. Figure 11 is a flowchart illustrating a decoding control method according to an exemplary embodiment of the present invention.

Claims

1. A decoding control method for a rewritable non-volatile memory module, the decoding control method comprising: In response to the failure of the first decoding operation performed based on the written data and the first parity data, the second parity data is read. Perform a second decoding operation based on the second parity data; in response to the second decoding operation being successful, increase the log-probability ratio corresponding to the second parity data; and perform a third decoding operation based on the written data, the first parity data, and the second parity data.

2. The decoding control method as described in claim 1 further includes: In response to the failure of the first decoding operation, the log probability ratio corresponding to the written data and the log probability ratio corresponding to the first odd-even data are reduced.

3. The decoding control method as described in claim 1 further includes: In response to the failure of the third decoding operation, read the third parity data; perform a fourth decoding operation based on the third parity data; in response to the success of the fourth decoding operation, increase the log-probability ratio corresponding to the third parity data; and perform a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

4. The decoding control method as described in claim 1 further includes: Record the decoding results of the first decoding operation and the second decoding operation; And adjust the log-probability ratio based on the decoding result.

5. A decoding control method for a rewritable non-volatile memory module, the decoding control method comprising: Perform decoding operations based on serial data; In the decoding operation, the decoding operation is performed on a first portion of the serial data using a first logarithmic probability ratio, and the decoding operation is performed on a second portion of the serial data using a second logarithmic probability ratio, wherein the first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table, wherein the second portion has been decoded successfully before the decoding operation is performed.

6. The decoding control method as described in claim 5, wherein the first part has been decoded and the decoding failed before the decoding operation is performed.

7. The decoding control method as described in claim 5, wherein the first part and the second part are read from different entity units.

8. A memory storage device, comprising: Connect the interface unit, which is coupled to the host system; Rewritable non-volatile memory modules; The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: read second parity data in response to a failure of a first decoding operation performed based on the written data and the first parity data; and increase the log-probability ratio corresponding to the second parity data in response to a success of the second decoding operation. The memory control circuit unit includes a decoding circuit configured to: perform the second decoding operation based on the second parity data; and perform a third decoding operation based on the written data, the first parity data, and the second parity data.

9. The memory storage device as claimed in claim 8, wherein the memory control circuit unit is further configured to: reduce the log-probability ratio corresponding to the written data and the log-probability ratio corresponding to the first parity data in response to the first decoding operation failing.

10. The memory storage device as claimed in claim 8, wherein the memory control circuit unit is further configured to: read third parity data in response to the failure of the third decoding operation; and increase the log-probability ratio corresponding to the third parity data in response to the success of the fourth decoding operation, and the decoding circuit is further configured to: perform the fourth decoding operation based on the third parity data; and perform a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

11. The memory storage device as claimed in claim 8, wherein the memory control circuit unit is further configured to: record the decoding results of the first decoding operation and the second decoding operation; and adjust the logarithmic probability ratio based on the decoding results.

12. A memory storage device, comprising: Connect the interface unit, which is coupled to the host system; Rewritable non-volatile memory modules; The system also includes a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a decoding circuit configured to: perform a decoding operation based on serial data; and in the decoding operation, perform the decoding operation on a first portion of the serial data using a first logarithmic probability ratio, and perform the decoding operation on a second portion of the serial data using a second logarithmic probability ratio, wherein the first logarithmic probability ratio originates from a first lookup table, and the second logarithmic probability ratio originates from a second lookup table, wherein the second portion has been decoded successfully before the decoding operation is performed.

13. The memory storage device as claimed in claim 12, wherein the first portion has been decoded and the decoding failed before the decoding operation is performed.

14. The memory storage device as claimed in claim 12, wherein the first portion and the second portion are read from different physical units.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising: The host interface is coupled to the connection interface unit; The memory interface is coupled to the rewritable non-volatile memory module; Decoding circuit; The system includes a memory management circuit coupled to the host interface, the memory interface, and the decoding circuit. The memory management circuit is configured to: read second parity data in response to a failure of a first decoding operation performed based on the written data and the first parity data; and increase the log-probability ratio corresponding to the second parity data in response to a success of the second decoding operation. The decoding circuit is configured to: perform the second decoding operation based on the second parity data; and perform a third decoding operation based on the written data, the first parity data, and the second parity data.

16. The memory control circuit unit as claimed in claim 15, wherein the memory management circuit is further configured to: reduce the log-probability ratio corresponding to the written data and the log-probability ratio corresponding to the first parity data in response to the first decoding operation failing.

17. The memory control circuit unit as claimed in claim 15, wherein the memory management circuit is further configured to: read third parity data in response to the failure of the third decoding operation; and increase the log-probability ratio corresponding to the third parity data in response to the success of the fourth decoding operation, wherein the decoding circuit is further configured to: perform the fourth decoding operation based on the third parity data; and perform a fifth decoding operation based on the written data, the first parity data, the second parity data, and the third parity data.

18. The memory control circuit unit as claimed in claim 15, wherein the memory management circuit is further configured to: record the decoding results of the first decoding operation and the second decoding operation; and adjust the logarithmic probability ratio based on the decoding results.

19. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising: The host interface is coupled to the connection interface unit; The memory interface is coupled to the rewritable non-volatile memory module; Decoding circuit; and a memory management circuit, coupled to the host interface, the memory interface and the decoding circuit, wherein the decoding circuit is used to: perform a decoding operation based on serial data; In the decoding operation, the decoding operation is performed on a first portion of the serial data using a first logarithmic probability ratio, and the decoding operation is performed on a second portion of the serial data using a second logarithmic probability ratio, wherein the first logarithmic probability ratio is derived from a first lookup table, and the second logarithmic probability ratio is derived from a second lookup table, wherein the second portion has been decoded successfully before the decoding operation is performed.

20. The memory control circuit unit as claimed in claim 19, wherein the first portion has been decoded and the decoding failed before the decoding operation is performed.

21. The memory control circuit unit as claimed in claim 19, wherein the first portion and the second portion are read from different physical units.

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