Inter-integrated circuit sound (I2S) audio device and method for i2s audio device misalignment recovery

Abstract

An I2S audio device including FIFO circuits and shift registers is provided. The FIFO circuits include memories, FIFO synchronize logic circuits, and FIFO misalignment flags. When a logic level of a left-right clock signal changes, the FIFO synchronize logic circuits move data from a corresponding location in the memories to the shift registers or move the data from the shift registers to a corresponding location in the memory according to locations of the data. In response to misalignments of the FIFO circuits, set the corresponding FIFO misalignment flags to a first logic level. When a logic level of a bit clock signal changes, the shift registers output the data from the memories or move the data into the memories. In response to the FIFO misalignment flags having the first logic level, the I2S audio device resets to recover the misalignment.

Description

[Technical Field]

[0001] This invention relates to an inter-integrated circuit sound (I2S) audio device, and more particularly to an I2S audio device and misalignment recovery method that can recover from misalignment without adding additional control lines. [Previous Technology]

[0002] Inter-integrated circuit sound (I2S) is a widely used audio transmission interface in various audio devices, and many audio devices are connected solely through I2S without any additional control lines. If channel misalignment occurs during the use of these audio devices, such as reversed channels or incorrect channel order, the misalignment cannot be recovered without additional control lines or manual reset of the I2S receiver or transmitter. Therefore, a solution is needed to restore channel misalignment without additional control lines or manual reset. [Summary of the Invention]

[0003] According to some embodiments of the present invention, an inter-integrated circuit sound (I2S) audio device is provided, including multiple first-in-first-out (FIFO) circuits and multiple shift registers. Each of the FIFO circuits has at least one memory, at least one FIFO synchronization logic circuit, and at least one FIFO misalignment flag. The FIFO synchronization logic circuit is configured to, in response to a change in the logic level of a left or right clock signal, shift output data out of the corresponding position in the memory according to the position of output data, or shift input data into the corresponding position in the memory according to the position of input data. Wherein, in response to a misalignment occurring in at least one of the FIFO circuits, the logic level of the corresponding FIFO misalignment flag is set to a first logic level.

[0004] The shift register is configured to output data from memory or shift input data into memory based on a change in the logic level of a bit clock signal. Specifically, in response to the FIFO misalignment flag being set to the first logic level, the I2S audio device is reset to restore the misalignment.

[0005] According to other embodiments of the present invention, a method for I2S misalignment recovery is provided, comprising: determining a corresponding logical level change of a left and right clock signal according to a data format of an I2S audio device; responding to the corresponding logical level change of the left and right clock signals, and according to the position of the data of a first frame, moving the data of the first frame out of the corresponding position in the I2S audio device, or moving the data of the first frame into the corresponding position in the I2S audio device; responding to the fact that the position of the data of the first frame is the same as the corresponding position in the I2S audio device, setting at least one FIFO misalignment flag of the I2S audio device to a first logical level, indicating that the I2S audio device has not misaligned.

[0006] According to other embodiments of the present invention, the method further includes, in response to the fact that the position of the data in the first frame is different from the corresponding position in the I2S audio device, setting the FIFO misalignment flag of the I2S audio device to a second logic level different from the first logic level, indicating that the I2S audio device has misaligned.

Implementation Method

[0007] To make the present invention and other objects, features and advantages more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0008] The following outlines some embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. However, these embodiments are merely exemplary and not intended to limit the scope of the present invention. It is understood that those skilled in the art can modify the embodiments described below as needed, such as changing the process sequence and / or including more or fewer steps than described herein, and these modifications do not exceed the scope of the embodiments of the present invention.

[0009] Inter-integrated circuit sound (I2S) audio devices can function as receivers or transmitters and operate based on bit clock signals and left and right clock signals. For example, the bit clock signal can be used to trigger (e.g., positive or negative edge triggering) the transmission or reception of data in bits. The left and right clock signals can be used to trigger (e.g., positive or negative edge triggering) the I2S audio device to align it according to the position of the data received or to be transmitted by the I2S audio device.

[0010] For example, if the I2S audio device is configured as a two-channel transmitter, the pointer in the I2S audio device can point to an even address based on the positive edge (rising from a logic low level to a logic high level) or negative edge (falling from a logic high level to a logic low level) of the left and right clock signals. This causes the left channel data to be moved from the even address to the output (e.g., through a shift register), and the right channel data immediately following the left channel data to be moved from the odd address to the output. Similarly, if the I2S audio device is configured as a two-channel receiver, the left channel data can be written to an even address from the input, and the right channel data can be written to an odd address.

[0011] However, when an I2S audio device transmits or receives data from a location other than its original position due to noise or other reasons, channel misalignment may occur. For example, assuming that during normal data transmission and reception, the left channel data corresponds to an even-numbered address, then the right channel data normally corresponds to an odd-numbered address. When the left channel data is misaligned and corresponds to an odd-numbered address, the right channel data will also be misaligned and correspond to an even-numbered address, resulting in reversed channels. In this case, if the devices are connected solely via I2S, channel reset cannot be performed to restore the misalignment to normal.

[0012] Figure 1 is a schematic diagram of an I2S audio device 100 described according to an embodiment of the present invention. The I2S audio device 100 includes an interface / register 110, a master clock generator 120, a transmit (TX) shift register 130, a receive (RX) shift register 140, multiplexers (MUX) 150 and 160, buffers 155 and 165, a TX first-in-first-out (FIFO) circuit 170, and an RX FIFO circuit 180.

[0013] Interface / register 110 may be an advanced peripheral bus (APB) interface or control register, configured to receive or transmit data with peripheral circuitry (e.g., other devices connected to the I2S audio device), for example, enabling the TXFIFO circuit 170 to enable the I2S audio device 100 to perform a transmission operation, or enabling the RXFIFO circuit 180 to enable the I2S audio device 100 to perform a reception operation. TX shift register 130 is configured to output an output data DO from the I2S audio device 100 according to a bit clock signal BCLK. RX shift register 140 is configured to input an input data DI to the I2S audio device 100 according to the bit clock signal BCLK. Master clock generator 120 is configured to generate a master clock signal MCLK. The master clock signal MCLK and the control signal SV output by the interface / snap register 110 are used to control the I2S audio device 100, so that the I2S audio device 100 operates in master mode or slave mode.

[0014] The TXFIFO circuit 170 includes a transmission controller 172 and a memory 178, wherein the transmission controller 172 further includes a TXFIFO synchronization logic circuit 174 and a TXFIFO misalignment flag 176. The RXFIFO circuit 180 includes a receiver controller 182 and a memory 188, wherein the receiver controller 182 further includes an RXFIFO synchronization logic circuit 184 and an RXFIFO misalignment flag 186.

[0015] The operation flow of the TXFIFO circuit 170 is described below with reference to Figure 1. Buffer 155 receives a left and right clock signal LRCLK. Multiplexer 150 outputs the left and right clock signals LRCLK to the TXFIFO circuit 170 according to the master clock signal MCLK and the control signal SV. Next, the TXFIFO synchronization logic circuit 174 aligns the position (e.g., channel or address) corresponding to the output data DO according to the falling edge or rising edge of the left and right clock signals LRCLK, and sequentially moves the output data DO from memory 178 into the TX shift register 130. Then, multiplexer 160 receives the bit clock signal BCLK through buffer 165 and outputs the bit clock signal BCLK to the TX shift register 130 according to the master clock signal MCLK and the control signal SV to control the output operation of the output data DO.

[0016] At this time, if the output data DO is not in the normal position (e.g., the left channel data is moved to the right channel, or the channel order is incorrect), that is, if the position of the output data DO is different from the position corresponding to the TXFIFO circuit 170, it means that the TXFIFO synchronization logic circuit 174 (or TXFIFO circuit 170) is not synchronized with the output data DO. Therefore, the transmission controller 172 sets the TXFIFO misalignment flag 176 to a logic high level (e.g., logic 1) to indicate the occurrence of channel or address misalignment, and then executes the exception handling procedure through software to restore the I2S audio device 100 from the misalignment state. Conversely, if the TXFIFO circuit 170 does not have a misalignment, the TXFIFO misalignment flag 176 is set to a logic low level (e.g., logic 0), indicating that the transmission is proceeding normally.

[0017] Next, the operation flow of the RXFIFO circuit 180 will be described with reference to Figure 1. The left and right clock signals LRCLK are transmitted to the RXFIFO circuit 180 via buffer 155 and multiplexer 150. Multiplexer 160 receives bit clock signal BCLK through buffer 165 and outputs it to RX shift register 140 to control the input operation of input data DI. Then, RXFIFO synchronization logic circuit 184 aligns the position (e.g., channel or address) corresponding to input data DI according to the falling edge or rising edge of the left and right clock signals LRCLK, and sequentially shifts input data DI from RX shift register 140 into memory 188.

[0018] At this time, if the input data DI is not in the normal position (e.g., the channels are reversed or the channel order is incorrect), it means that the RXFIFO synchronization logic circuit 184 (or RXFIFO circuit 180) is not synchronized with the input data DI. Therefore, the receiver controller 182 sets the RXFIFO misalignment flag 186 to a logic high level (e.g., logic 1) to indicate the occurrence of channel or address misalignment, and then executes the exception handling procedure through software to restore the I2S audio device 100 from the misalignment state. Conversely, if the RXFIFO circuit 180 does not have a misalignment, the RXFIFO misalignment flag 186 is set to a logic low level (e.g., logic 0), indicating that the transmission is proceeding normally.

[0019] Figures 2A and 2B are schematic diagrams of I2S dual-channel misalignment recovery as described in the embodiments of the present invention. Referring to Figure 2A, it is assumed that the I2S audio device 100 is configured to be triggered by the negative edges of the bit clock signal BCLK and the left and right clock signals LRCLK, and the I2S audio device 100 is set to perform a transmission operation. Starting from a time t1, the logic level of the left and right clock signals LRCLK gradually decreases (i.e., a negative edge appears), causing the TXFIFO synchronization logic circuit 174 to be triggered by the negative edges of the left and right clock signals LRCLK, aligning the position corresponding to the output data DO. Then, from time t1 to t2, the TXFIFO synchronization logic circuit 174, according to the position of the output data DO, moves the output data DO from the address corresponding to the memory 178 into the TX shift register 130 for transmission through the triggering of the negative edge of the bit clock signal BCLK.

[0020] If the TXFIFO circuit 170 is not misaligned (e.g., channels reversed or channel order incorrect), then as shown in Figure 2A, after the negative edge of the left and right clock signals LRCLK appears and the TXFIFO synchronization logic circuit 174 is aligned, the I2S audio device 100 begins transmission, outputting a left channel frame L(N) and a right channel frame R(N). Then, after the next negative edge of the left and right clock signals LRCLK appears, it continues to output the next set of left channel frames L(N+1) and right channel frames R(N+1). Conversely, referring to Figure 2B, in a segment 202, the I2S audio device 100 normally transmits a set of left channel frames L(N-1) and right channel frames R(N-1). Next, in segment 204, the I2S audio device 100 experiences a misalignment (marked as "xxx", for example, the left and right channels are reversed), indicating that the alignment of the TXFIFO synchronization logic circuit 174 is incorrect. At this time, the TXFIFO misalignment flag 176 is set to a logic high level (e.g., logic 1), allowing the I2S audio device 100 to restore the misalignment state of the TXFIFO synchronization logic circuit 174 (or TXFIFO circuit 170) via software, thereby restoring normal transmission of the next set of left channel frames L (N+1) and right channel frames R (N+1) in segment 206.

[0021] Figures 3A and 3B are schematic diagrams of I2S time-division multiplexing (TDM) mode misalignment recovery as described in the embodiments of the present invention. Referring to Figure 3A, it is assumed that the I2S audio device 100 is configured to be triggered by the negative edge of the bit clock signal BCLK and the positive edges of the left and right clock signals LRCLK, and the I2S audio device 100 is set to perform a receiving operation. At a time t3, the logic level of the left and right clock signals LRCLK rises to a logic high level (e.g., logic 1) at time t3, triggering the RXFIFO synchronization logic circuit 184 to align the position corresponding to the input data DI through the positive edges of the left and right clock signals LRCLK. Then, at a time t4, the RXFIFO synchronization logic circuit 184, based on the position of the input data DI, is triggered by the negative edge of the bit clock signal BCLK, and writes the input data DI from the RX shift register 140 to the corresponding position in the memory 188.

[0022] If the RXFIFO circuit 180 does not misalign (e.g., incorrect channel order), as shown in Figure 3A, after the positive edge of the left and right clock signals LRCLK appears, the I2S audio device 100 begins receiving data sequentially from channels CH0 to CH5. Then, after the next positive edge of the left and right clock signals LRCLK appears, it continues to receive the next set of data from channels CH0 to CH5. Conversely, referring to Figure 3B, in segment 302, the I2S audio device 100 normally receives a set of data from channels CH0 to CH5. Then, in segment 304, the I2S audio device 100 misaligns (marked as "xxx", for example, incorrect channel order), indicating that the alignment of the RXFIFO synchronization logic circuit 184 is incorrect at this time. At this time, the RXFIFO misalignment flag 186 is set to a logic high level (e.g., logic 1), so that the I2S audio device 100 can restore the misalignment state of the RXFIFO synchronization logic circuit 184 (or RXFIFO circuit 180) through software, and then resume normal reception of the next set of channel CH0 to CH5 data in section 306.

[0023] Figure 4 is a flowchart 400 describing a control method for the I2S audio device 100 to perform transmission according to an embodiment of the present invention. Before performing a transmission operation, the I2S audio device 100 performs an initialization operation. The interface / register 110 sets the I2S audio device 100 to master mode or slave mode via the master clock signal MCLK and the control signal SV. Then, since a transmission operation is to be performed, the I2S audio interface is set as a transmitter. After the initialization operation is completed, a step 402 is entered to set the data format of the I2S audio device, such as the number of channels (e.g., mono or multi-channel) and the data length (e.g., the number of frames per channel or the number of bits of channel data). Then, in a step 404, it is determined whether to enable the transmission operation. If not, the operation of the I2S audio device 100 ends. If so, proceed to step 406, and determine whether to wait for the positive or negative edge of the left and right clock signals LRCLK to trigger the TXFIFO synchronous logic circuit 174 to align the position of the output data DO according to the data format set in step 402.

[0024] Assuming step 406 determines that it needs to wait for the positive edge of the left and right clock signals LRCLK, then in step 408, it is determined whether the positive edge of the left and right clock signals LRCLK has occurred. If not, it returns to step 406. If yes, it proceeds to step 410, where the TXFIFO synchronization logic circuit 174 starts shifting the output data DO from the corresponding position in memory 178 into the TX shift register 130 according to the position of the output data DO. Then, it proceeds to step 412 to determine whether the TXFIFO circuit 170 is synchronized (i.e., whether the TXFIFO circuit 170 has misaligned). If it is determined to be synchronized, it means that the TXFIFO circuit 170 is not misaligned, so it proceeds to step 414 to set the TXFIFO misalignment flag 176 to a low logic level (e.g., logic 0). Conversely, if step 412 determines that the TXFIFO circuit 170 is not synchronized, it means that the TXFIFO circuit 170 has misaligned. Therefore, proceed to step 416, and set the TXFIFO misalignment flag 176 to logical high (e.g., logical 1).

[0025] After step 414 or 416, flowchart 400 returns to step 404 to determine whether to enable the transmission operation. If the transmission operation performed by the I2S audio device 100 has ended, or it has switched to other operations (such as receiving operations), then step 404 determines no and ends the operation. If the I2S audio device 100 has not yet ended the transmission operation, then the remaining parts of flowchart 400 as described above are continued.

[0026] Figure 5 is a flowchart illustrating the control of the I2S audio device 100 for receiving data according to an embodiment of the present invention. Before performing the receiving operation, the I2S audio device 100 performs an initialization operation. The interface / register 110 sets the I2S audio device 100 to master mode or slave mode via the master clock signal MCLK and the control signal SV. Then, since the receiving operation is to be performed, the I2S audio interface is set as a receiver. After the initialization operation is completed, step 502 is entered to set the data format of the I2S audio device. Next, in step 504, it is determined whether the receiving operation is enabled. If not, the operation of the I2S audio device 100 ends. If yes, step 506 is entered, and according to the data format set in step 502, it is determined whether to wait for the positive or negative edge of the left and right clock signals LRCLK to trigger the RXFIFO synchronization logic circuit 184 to align the position of the input data DI.

[0027] Assuming step 506 determines that it needs to wait for the negative edge of the left and right clock signals LRCLK, then in step 508, it is determined whether the negative edge of the left and right clock signals LRCLK has occurred. If not, it returns to step 506. If yes, it proceeds to step 510, where the RXFIFO synchronization logic circuit 184 writes the input data DI from the RX shift register 140 to the corresponding position in the memory 188 according to the position of the received input data DI. Then, it proceeds to step 512 to determine whether the RXFIFO circuit 180 is synchronized (i.e., whether the RXFIFO circuit 180 has misaligned). If it is determined to be synchronized, it means that the RXFIFO circuit 180 is not misaligned, so it proceeds to step 514 to set the RXFIFO misalignment flag 186 to a logic low level (e.g., logic 0). Conversely, if step 512 determines that the RXFIFO circuit 180 is not synchronized, it means that the RXFIFO circuit 180 has misaligned. Therefore, proceed to step 516, and set the RXFIFO misalignment flag 186 to logic high (e.g., logic 1).

[0028] After step 514 or 516, flowchart 500 returns to step 504 to determine whether to enable the receiving operation. If the receiving operation performed by the I2S audio device 100 has ended, or has switched to other operations (such as transmission operations), then step 504 determines no and ends the operation. If the I2S audio device 100 has not yet ended the receiving operation, then the remaining parts of flowchart 500 as described above are continued.

[0029] This invention provides an I2S audio device that can align channel data using synchronization logic circuits at the receiving end (e.g., RXFIFO circuit 180) and the transmitting end (e.g., TXFIFO circuit 170) without additional control lines. Furthermore, the I2S audio device provided by this invention can set misalignment flags with different logic levels by controlling whether the synchronization logic circuits are synchronized. Based on the state of the misalignment flags, when a misalignment is detected, the software directly resets the I2S audio device. Thus, the effect of restoring the misalignment state is achieved without the need for additional connection lines. [Simplified Explanation of the Diagram]

[0030] Figure 1 is a schematic diagram of an Inter-integrated circuit sound (I2S) audio device according to an embodiment of the present invention. Figures 2A and 2B are schematic diagrams of I2S dual-channel misalignment recovery according to an embodiment of the present invention. Figures 3A and 3B are schematic diagrams of I2S time-division multiplexing (TDM) mode misalignment recovery according to an embodiment of the present invention. Figure 4 is a flowchart of controlling the I2S audio device to perform transmission according to an embodiment of the present invention. Figure 5 is a flowchart of controlling the I2S audio device to perform reception according to an embodiment of the present invention.

Claims

1. An inter-integrated circuit digital audio standard audio device, comprising: A plurality of first-in-first-out (FIFO) circuits, each of the FIFO circuits having: at least one memory; at least one FIFO synchronous logic circuit configured to, in response to a change in the logic level of a left or right clock signal, shift output data out of a corresponding position in the at least one memory according to the position of output data, or shift input data into a corresponding position in the at least one memory according to the position of input data; and at least one FIFO error flag, wherein, in response to an error occurring in at least one of the FIFO circuits, the logic level of the corresponding at least one FIFO error flag is set to a first logic level; and a plurality of shift registers configured to, in response to a change in the logic level of a one-bit clock signal, output output data from the at least one memory, or shift input data into the at least one memory, wherein, in response to the at least one FIFO error flag being set to the first logic level, the inter-circuit digital audio standard (I2S) audio device is reset to recover from the error.

2. The I2S audio device as described in claim 1, wherein: In response to the fact that at least one of the first-in-first-out circuits has not been misaligned, the logic level of the corresponding first-in-first-out misalignment flag is set to a second logic level different from the first logic level.

3. The I2S audio device as described in claim 1 further includes an interface / register configured to control a master clock generator to output a master clock signal and configured to generate a control signal to cause the I2S audio device to enter a master mode or a slave mode.

4. The I2S audio device as described in claim 3 further includes multiple multiplexers and multiple buffers, wherein the multiplexers and buffers are configured to output the left and right clock signals to the first-in-first-out circuits according to the master clock signal and the control signal, and to output the bit clock signal to the shift registers.

5. The I2S audio device as described in claim 1, wherein: The I2S audio device was reset via software to restore the correct position.

6. The I2S audio device as claimed in claim 1, wherein the at least one first-in-first-out synchronization logic circuit comprises: A transmission first-in-first-out synchronous logic circuit, in response to a change in the logic level of the left and right clock signals, shifts the output data out of the corresponding position in the at least one memory; and a receiving first-in-first-out synchronous logic circuit, in response to a change in the logic level of the left and right clock signals, shifts the input data into the corresponding position in the at least one memory, wherein when the position of the input data or the output data is different from the corresponding position in the at least one memory, the logic level of the at least one first-in-first-out error flag is set to the first logic level.

7. The I2S audio device as described in claim 1, wherein the shift registers comprise: A transfer shift register, in response to a change in the logic level of the bit clock signal, outputs the output data from the at least one memory. And a receive shift register, which, in response to a change in the logic level of the bit clock signal, inputs the input data into the at least one memory, wherein, in response to the at least one first-in-first-out error flag being set to the first logic level, the shift registers either do not output the output data or do not input the input data.

8. A method for recovering misalignment in an integrated circuit digital audio standard audio device, comprising: Based on a data format of an Inter-Integrated Circuits Digital Audio Standard (I2S) audio device, a corresponding logic level change of a left and right clock signal is determined; in response to the corresponding logic level change of the left and right clock signals, and based on the position of data in a first frame, the data in the first frame is either moved out of the corresponding position in the I2S audio device or moved into the corresponding position in the I2S audio device; in response to the position of the data in the first frame being the same as the corresponding position in the I2S audio device, at least one first-in-first-out fault flag of the I2S audio device is set to a first logic level, indicating that the I2S audio device has not experienced a misalignment.

9. The method for I2S audio device misalignment recovery as described in claim 8 further includes: In response to the fact that the position of the data in the first frame is different from the corresponding position in the I2S audio device, the at least one first-in-first-out fault flag of the I2S audio device is set to a second logic level different from the first logic level, indicating that the I2S audio device has misaligned.

10. A method for recovering misalignment of an I2S audio device as described in claim 9, wherein: In response to the at least one first-in-first-out (FIFO) flag being set to the first logical level, the data of the first frame is output from the I2S audio device, or the data of the first frame is input to the I2S audio device; or in response to the at least one FIFO flag being set to the second logical level, the transmission or reception of the data of the second frame following the data of the first frame is stopped, the I2S audio device is reset using software, and the reception or output of the data of the third frame following the data of the second frame continues.

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