Memory circuit and method of programming thereof

TW202634595APending Publication Date: 2026-08-16TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
TW114118598
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-02-10
Filing Date
2025-05-19
Publication Date
2026-08-16

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Abstract

A circuit includes memory cells, each from one of first, second, third, or fourth cells. The first cell includes a transistor having a gate coupled to a first wordline, a first source / drain coupled to a first interconnect carrying a ground voltage, and a second source / drain coupled to the first interconnect. The second cell includes a transistor having a gate coupled to a second wordline, a first source / drain coupled to a second interconnect configured as a bitline, and a second source / drain coupled to the second interconnect. The third cell includes a transistor having a gate coupled to a third wordline, a first source / drain coupled to the first interconnect, and a second source / drain coupled to the second interconnect. The fourth cell includes a transistor having a gate coupled to a fourth wordline, a first source / drain coupled to the second interconnect, and a second source / drain coupled to the first interconnect.
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