Memory device

Abstract

This invention improves the yield of memory devices. One embodiment of the memory device includes: a plurality of first wiring layers, which are arranged apart from each other in a first direction; second, third, and fourth wiring layers, which are arranged sequentially in the first direction along with the plurality of first wiring layers and without being separated by other wiring layers; and memory pillars extending along the first direction, the portions of which intersect with each of the plurality of first, second, and third wiring layers function as memory cells. The plurality of first, second, and third wiring layers each have a plurality of first, second, and third stepped portions that have been thickened. Between each of the plurality of first stepped portions and each of the plurality of other first stepped portions adjacent to each of the plurality of first stepped portions when viewed along the first direction, there is at least one wiring layer other than the two wiring layers having two adjacent first stepped portions. When viewed along the first direction, the third stepped portion is adjacent to the second stepped portion. The third wiring layer has an unthickened portion at the junction of the second and third steps.

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