Memory device

Abstract

The first memory cell of this invention includes a first variable resistor element and a first switching element connected to the first variable resistor element. A first wiring is connected to the first memory cell. The first switch has a first terminal and a second terminal connected to the first wiring. A second wiring is connected to the second terminal. A first pre-charge circuit is connected to the second wiring. A first transistor has a third terminal and a fourth terminal connected to a first node receiving a first voltage, and a gate connected to the first wiring. A third wiring is connected to the fourth terminal of the first transistor. A sensing amplifier circuit is connected to the third wiring.

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