Memory circuits and methods for operating the same

Abstract

A memory circuit includes a memory array comprising a plurality of memory cells arranged across a first number (N) of word lines; a word line driver comprising a second number of logic gates, wherein each of the logic gates is configured to receive a first input signal corresponding to a first one of the word lines and a second input signal corresponding to a second one of the word lines, and configured to provide a boost signal based on respective logic states of the first and second input signals; and a booster circuit comprising pairs of first and second buffers, wherein each of the first buffers is configured to receive the corresponding boost signal and de-assert the corresponding first word line, and each of the second buffers is configured to receive the corresponding boost signal and assert the corresponding second word line.

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