Fail recovery method, memory storage device and memory control circuit unit

Abstract

A fail recovery method, a memory storage device and a memory control circuit unit are provided. The fail recovery method includes: in response to a first operation corresponding to a first physical unit failing, determining whether a current retry count is less than a preset count, wherein the current retry count is used to represent a number of erase retry operation performed on the first physical unit; in response to the current retry count being less than the preset count, performing the erase retry operation on the first physical unit; determining whether the erase retry operation is successful; and in response to the erase retry operation being successful, associating the first physical unit to a spare area.

Description

[Technical Field]

[0001] This invention relates to a memory management technology, and more particularly to an error recovery method, a memory storage device, and a memory control circuit unit. [Previous Technology]

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, during the access process of a memory storage device, when an error occurs in a physical cell, this physical cell is recorded in the Bad Block Table. Subsequently, this physical cell will no longer be accessed. However, some erroneous physical cells can continue to be used to access data in actual use scenarios. For example, the data stored in these physical cells can be successfully decoded during the error correction process in actual use scenarios. [Summary of the Invention]

[0004] In view of this, the present invention provides an error recovery method, a memory storage device, and a memory control circuit unit, which can further analyze whether the physical unit that has erred can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module.

[0005] An exemplary embodiment of the present invention provides an error recovery method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the error recovery method includes: in response to a first operation corresponding to a first physical unit failing, determining whether the current retry count is less than a predetermined count, wherein the current retry count is used to characterize the number of erase retry operations performed for the first physical unit; in response to the current retry count being less than the predetermined count, performing the erase retry operation for the first physical unit; determining whether the erase retry operation is successful; and in response to the erase retry operation being successful, associating the first physical unit with an idle area.

[0006] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the failure of the erase retry operation, determining again whether the current number of retries is less than the predetermined number.

[0007] In an exemplary embodiment of the present invention, the error recovery method further includes: when the current number of retries reaches the predetermined number, obtaining the number of error bits of the first entity cell based on a critical voltage; determining whether the number of error bits is less than the predetermined number of bits; and in response to the number of error bits being not less than the predetermined number of bits, updating the first entity cell to a second-level error in the bad block table.

[0008] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the number of error bits being less than the predetermined number of bits, associating the first entity unit with the idle area again.

[0009] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the first operation being a multi-plane operation, determining whether the number of first entity planes is greater than a predetermined number, wherein the first entity plane is the entity plane where the error occurred; in response to the number being greater than the predetermined number, determining whether the current number of retries is less than the predetermined number; and in response to the current number of retries being less than the predetermined number, performing the erase retry operation on the first entity unit belonging to the first entity plane, wherein the erase retry operation is a single-plane operation.

[0010] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the number not being greater than the predetermined number, updating the first entity unit to a second-level error in the bad block table.

[0011] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the current number of retries being not less than the predetermined number, updating the first entity unit to a second-level error in the bad block table.

[0012] In an exemplary embodiment of the present invention, the error recovery method further includes: in response to the first operation being a failure, recording the first entity unit as a first-level error in the bad block table.

[0013] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. In response to a first operation corresponding to a first physical unit failing, the memory control circuit unit is configured to determine whether the current retry count is less than a predetermined count, wherein the current retry count is used to characterize the number of erase retry operations performed for the first physical unit. In response to the current retry count being less than the predetermined count, the memory control circuit unit is further configured to perform the erase retry operation for the first physical unit. The memory control circuit unit is further configured to determine whether the erase retry operation is successful. In response to the erase retry operation being successful, the memory control circuit unit is further configured to associate the first physical unit with an idle area.

[0014] In an exemplary embodiment of the present invention, in response to the failure of the erase retry operation, the memory control circuit unit is further configured to determine again whether the current number of retries is less than the predetermined number.

[0015] In an exemplary embodiment of the present invention, when the current number of retries reaches the predetermined number, the memory control circuit unit is further configured to obtain the number of error bits of the first physical cell based on a threshold voltage. The memory control circuit unit is further configured to determine whether the number of error bits is less than the predetermined number of bits. In response to the number of error bits not being less than the predetermined number of bits, the memory control circuit unit is further configured to update the first physical cell to a second-level error in the bad block table.

[0016] In an exemplary embodiment of the present invention, in response to the number of error bits being less than the predetermined number of bits, the memory control circuit unit is further configured to associate the first physical unit with the idle area.

[0017] In an exemplary embodiment of the present invention, in response to the first operation being a multi-plane operation, the memory control circuit unit is further configured to determine whether the number of first physical planes is greater than a predetermined number, wherein the first physical plane is the physical plane where the error occurred. In response to the number being greater than the predetermined number, the memory control circuit unit is further configured to determine whether the current number of retries is less than the predetermined number. In response to the current number of retries being less than the predetermined number, the memory control circuit unit is further configured to perform the erase retry operation for the first physical unit belonging to the first physical plane, wherein the erase retry operation is a single-plane operation.

[0018] In an exemplary embodiment of the present invention, in response to the quantity not being greater than the predetermined quantity, the memory control circuit unit is further configured to update the first entity unit to a second-level error in the bad block table.

[0019] In an exemplary embodiment of the present invention, in response to the current number of retries being not less than the predetermined number, the memory control circuit unit is further configured to update the first entity unit to a second-level error in the bad block table.

[0020] In an exemplary embodiment of the present invention, in response to the failure of the first operation, the memory control circuit unit is further configured to record the first physical unit as a first-level error in the bad block table.

[0021] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to the interface unit. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. In response to a first operation corresponding to a first physical unit failing, the memory management circuit determines whether the current retry count is less than a predetermined count, wherein the current retry count represents the number of erase retry operations performed on the first physical unit. In response to the current retry count being less than the predetermined count, the memory management circuit further performs the erase retry operation on the first physical unit. The memory management circuit further determines whether the erase retry operation is successful. In response to a successful erase retry operation, the memory management circuit further associates the first physical cell with an idle area.

[0022] In an exemplary embodiment of the present invention, in response to the failure of the erase retry operation, the memory management circuit is further configured to determine again whether the current number of retries is less than the predetermined number.

[0023] In an exemplary embodiment of the present invention, when the current number of retries reaches the predetermined number, the memory management circuit is further configured to obtain the number of error bits of the first physical cell based on a threshold voltage. The memory management circuit is further configured to determine whether the number of error bits is less than the predetermined number of bits. In response to the number of error bits not being less than the predetermined number of bits, the memory management circuit is further configured to update the first physical cell to a second-level error in the bad block table.

[0024] In an exemplary embodiment of the present invention, in response to the number of error bits being less than the predetermined number of bits, the memory management circuitry is further configured to associate the first physical cell with the idle area.

[0025] In an exemplary embodiment of the present invention, in response to the first operation being a multi-plane operation, the memory management circuit is further configured to determine whether the number of first physical planes is greater than a predetermined number, wherein the first physical plane is the physical plane where the error occurred. In response to the number being greater than the predetermined number, the memory management circuit is further configured to determine whether the current number of retries is less than the predetermined number. In response to the current number of retries being less than the predetermined number, the memory management circuit is further configured to perform the erase retry operation for the first physical unit belonging to the first physical plane, wherein the erase retry operation is a single-plane operation.

[0026] In an exemplary embodiment of the present invention, in response to the quantity not being greater than the predetermined quantity, the memory management circuit is further configured to update the first entity cell to a second-level error in the bad block table.

[0027] In an exemplary embodiment of the present invention, in response to the current number of retries being not less than the predetermined number, the memory management circuit is further configured to update the first entity cell in the bad block table to a second-level error.

[0028] In an exemplary embodiment of the present invention, in response to the failure of the first operation, the memory management circuitry is further configured to record the first physical unit as a first-level error in the bad block table.

[0029] Based on the above, the error recovery method, memory storage device and memory control circuit unit of the present invention can further analyze the entity unit that has erroneous in order to determine whether the entity unit can continue to be used to access data, so as to improve the access performance of the rewritable non-volatile memory module while maintaining the correctness of the data.

Implementation Method

[0030] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0031] FIG1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. FIG2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention.

[0032] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0033] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0034] In an exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0035] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0036] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0037] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0038] FIG4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0039] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0040] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0041] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0042] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in that memory cell.

[0043] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in MLC NAND flash memory, the write rate of lower physical programming units is greater than that of upper physical programming units, and / or the reliability of lower physical programming units is higher than that of upper physical programming units.

[0044] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0045] FIG5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0046] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0047] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0048] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory management circuit 51 has a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0049] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit processes data to be written to and read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0050] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0051] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0052] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0053] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0054] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0055] In one exemplary embodiment, the rewritable non-volatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0056] FIG6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0057] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0058] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 can store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0059] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In an exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logic addresses.

[0060] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0061] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0062] In one exemplary embodiment, when a write, read, or erase operation for a certain physical unit fails, the memory management circuit 51 may record the physical address of this physical unit and the error type in at least one bad block table. Subsequently, the physical unit recorded in the bad block table will no longer be used to access data. In one exemplary embodiment, when an erase operation corresponding to a certain physical unit fails (i.e., an error occurs), the memory management circuit 51 may record the physical address of this physical unit and the error type (e.g., Erase Status Fail (ESF)) in the bad block table. In one exemplary embodiment, when a write operation corresponding to a certain physical unit fails, the memory management circuit 51 may record the physical address of this physical unit and the error type (e.g., Program Status Fail (PSF)) in the bad block table. In one exemplary embodiment, when a read operation corresponding to a certain entity cell fails, the memory management circuit 51 may record the entity address of this entity cell and the error type (e.g., an Uncorrectable Error Correction Code (UECC)) in the bad block table.

[0063] FIG7 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. Referring to FIG7, in step S701, the memory management circuit 51 may record a first physical unit corresponding to a failed first operation as a first-level error in the bad block table, wherein the first operation may be, for example, an erase operation, a write operation, or a read operation. In an exemplary embodiment, the error types in the bad block table may be divided into first-level errors and second-level errors. For example, a first-level error is used to indicate that a physical unit is a bad physical unit that has experienced a write operation error, an erase operation error, or a read operation error; in other words, a first-level error is PSF, ESF, or UECC. For example, a second-level error is used to indicate that a physical unit is a bad physical unit that is determined by the error recovery method provided by the present invention to be unusable for further data access. In detail, the exemplary embodiments of the present invention provide a graded error mechanism. The memory management circuit 51 can record a physical unit that has erred as a first-level error in the bad block table, and then execute the error recovery method of the present invention on this physical unit to determine whether this physical unit can continue to be used to access data in actual use, thereby improving the access performance of the rewritable non-volatile memory module 43. In one exemplary embodiment, the memory management circuit 51 can record the first physical unit that has failed to erase as a first-level error (i.e., ESF) in the bad block table.

[0064] In step S702, the memory management circuit 51 can determine whether the current number of retries is less than a predetermined number. Specifically, the error recovery method shown in FIG7 can determine whether the first physical unit can continue to be used to access data in actual use scenarios by performing an erase retry operation on the first physical unit at most a predetermined number (e.g., 3 times). The predetermined number of retries can be designed by the user according to actual needs, for example, and the present invention does not limit it.

[0065] In an exemplary embodiment, the current retry count is used to characterize the number of erase retry operations performed on the first physical unit. If the current retry count is not less than a predetermined number, that is, the current retry count has reached 3 times, the process proceeds to step S703, whereby the memory management circuit 51 updates the first physical unit to a second-level error in the bad block table. Specifically, if the predetermined number of erase retry operations performed by the memory management circuit 51 on the first physical unit all fail, the memory management circuit 51 can determine that the first physical unit can no longer be used to access data in the actual usage scenario. Accordingly, the memory management circuit 51 can update the first physical unit from a first-level error to a second-level error in the bad block table.

[0066] On the other hand, if the current number of retries (e.g., 0 times) is less than the predetermined number (i.e., 3 times), proceed to step S704. In step S704, the memory management circuit 51 may perform an erase retry operation on the first physical cell. Then, in step S705, the memory management circuit 51 may determine whether the erase retry operation was successful.

[0067] If the erase retry operation is successful, proceed to step S706, whereby the memory management circuit 51 can associate the first physical unit with the idle area 602. Specifically, a successful erase retry operation means that the first physical unit can continue to be used to access data in actual use, so the memory management circuit 51 can remove the successfully erased first physical unit from the bad block table and associate the first physical unit with the idle area 602.

[0068] Conversely, if the erase retry operation fails, the process returns to step S702 to determine again whether the current number of retries is less than the predetermined number. At this time, the current number of retries is 1, so the memory management circuit 51 can continue with steps S704 and S705 to perform the erase retry operation on the first physical unit again and determine whether this erase retry operation is successful. If this erase retry operation is successful, the process proceeds to step S706. Conversely, if this erase retry operation fails, the process returns to step S702. At this point, the current retry count is 2. The memory management circuit 51 can perform steps S704 and S705 again, and enter step S706 based on the success of the erase retry operation to associate the first physical unit with the idle area 602, or return to step S702 based on the failure of the erase retry operation. At this point, the current retry count is 3, so it can enter step S703 to update the first physical unit to the second level error in the bad block table.

[0069] According to the above, the error recovery method shown in FIG7 can perform an erase retry operation for the physical unit that failed to erase, and in response to the success of the erase retry operation, re-associate the physical unit to the idle area 602 so that it can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0070] Figure 8 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. Referring to Figure 8, in step S801, the memory management circuit 51 may record the first physical unit corresponding to the failed erase operation as a first-level error in the bad block table. Details regarding the implementation of step S801 can be found in the aforementioned step S701, and will not be repeated here.

[0071] In step S802, the memory management circuit 51 can obtain the Fail Bit Count (FBC) of the first physical cell. In an exemplary embodiment, the memory management circuit 51 can obtain the FBC of the first physical cell, for example, based on a voltage threshold (VT). For example, the memory management circuit 51 can issue a threshold voltage distribution (VT Distribution) instruction to the first physical cell to read data from the first physical cell and detect the FBC of the first physical cell based on this data. Specifically, if a physical cell has severe physical wear (e.g., large charge loss), then this physical cell has a high FBC and is not suitable for continued data access.

[0072] In step S803, the memory management circuit 51 can determine whether the number of error bits is less than a predetermined number of bits. Specifically, the error recovery method shown in FIG8 can determine whether the first physical unit can continue to be used to access data in actual use scenarios by using the number of error bits of the first physical unit. The predetermined number of bits can be designed by the user according to actual needs, or it can be associated with the number of bits contained in a physical programmable unit, for example, and the present invention does not limit it.

[0073] If the number of error bits is less than the predetermined number of bits, it means that the first physical unit can continue to be used to access data in the actual use scenario, and proceeds to step S804. In step S804, the memory management circuit 51 can associate the first physical unit with the idle area 602.

[0074] On the other hand, if the number of error bits is not less than the predetermined number of bits, it means that the first physical unit cannot continue to be used to access data in the actual use scenario, and proceeds to step S805. In step S805, the memory management circuit 51 can update the first physical unit to a second-level error in the bad block table.

[0075] According to the above, the error recovery method shown in FIG8 can obtain the number of error bits of the entity unit that failed to be erased, and in response to the number of error bits being less than a predetermined number of bits, the entity unit is reassociated with the idle area 602 so that it can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0076] FIG9 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. It should be noted that the error recovery method shown in FIG9 is a combination of the error recovery methods shown in FIG7 and FIG8, which can more accurately determine whether the entity unit that has experienced an erasure error can continue to be used to access data.

[0077] Referring to Figure 9, in step S901, the memory management circuit 51 may record the first physical unit corresponding to the failed erase operation (also known as the first operation) as a first-level error in the bad block table. Details regarding the implementation of step S901 can be found in the aforementioned step S701, and will not be repeated here.

[0078] In step S902, the memory management circuit 51 can determine whether the current retry count has reached a predetermined number. Specifically, the error recovery method shown in FIG9 can perform an erase retry operation on the first physical unit up to a predetermined number (e.g., 3 times), and after performing the predetermined number of erase retry operations, further detect the number of error bits in the first physical unit to determine whether the first physical unit can continue to be used to access data in actual use. The predetermined number of times can be designed by the user according to actual needs, and the present invention does not limit it.

[0079] If the current number of retries reaches the predetermined number, proceed to step S906.

[0080] On the other hand, if the current number of retries (e.g., 0 times) has not reached the predetermined number, that is, the current number of retries is less than 3 times, the process proceeds to step S903, where the memory management circuit 51 can perform an erase retry operation on the first physical unit. Then, in step S904, the memory management circuit 51 can determine whether the erase retry operation was successful. If the erase retry operation is successful (that is, the first physical unit can continue to be used to access data in actual use), the process proceeds to step S905, where the memory management circuit 51 can associate the first physical unit with the idle area 602.

[0081] Conversely, if the erase retry operation fails, the process returns to step S902. At this time, the current retry count is 1, so the memory management circuit 51 can continue to perform steps S903 and S904 to perform the erase retry operation on the first physical unit again, and determine whether the erase retry operation is successful. If the erase retry operation is successful, the process proceeds to step S905. Conversely, if the erase retry operation fails, the process returns to step S902 again. At this time, the current retry count is 2, and the memory management circuit 51 can perform steps S903 and S904 again, and proceed to step S905 based on the success of the erase retry operation to associate the first physical unit with the idle area 602, or return to step S902 based on the failure of the erase retry operation. At this time, the current retry count is 3, that is, the current retry count has reached the predetermined number, and the process proceeds to step S906.

[0082] In step S906, the memory management circuit 51 can obtain the number of error bits in the first physical cell. For example, the memory management circuit 51 can obtain the number of error bits in the first physical cell based on a critical voltage. For example, the memory management circuit 51 can issue a critical voltage distribution command to the first physical cell to read data from the first physical cell and detect the number of error bits in the first physical cell based on this data.

[0083] Subsequently, in step S907, the memory management circuit 51 checks whether the number of error bits is less than a predetermined number of bits. If the number of error bits is less than the predetermined number of bits, it means that the first physical unit can continue to be used to access data in the actual usage scenario, and proceeds to step S905, where the memory management circuit 51 can associate the first physical unit with the idle area 602. Conversely, if the number of error bits is not less than the predetermined number of bits, it means that the first physical unit cannot continue to be used to access data in the actual usage scenario, and proceeds to step S908, where the memory management circuit 51 can update the first physical unit to a second-level error in the bad block table.

[0084] According to the above, the error recovery method shown in FIG9 can perform an erase retry operation (and obtain the number of error bits of the erased entity) for the entity unit that failed to erase, and in response to the success of the erase retry operation (or the number of error bits is less than a predetermined number of bits), the entity unit is reassociated with the idle area 602 so that it can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0085] FIG10 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. In an exemplary embodiment, the rewritable non-volatile memory module 43 may, for example, include multiple physical planes (not shown), and each physical plane includes multiple physical cells. Generally, write, erase, or read operations performed by the memory management circuit 51 are typically multi-plane operations. For example, assuming the rewritable non-volatile memory module 43 has four physical planes, the memory management circuit can perform multi-plane operations to simultaneously perform write, erase, or read operations on physical planes of these four physical planes.

[0086] It should be noted that these four physical planes can interfere with each other. For example, when one physical plane (a physical cell belonging to one physical plane) malfunctions, another adjacent physical plane (a physical cell belonging to another physical plane) may also malfunction due to leakage current from this physical plane. In some cases, physical cells that malfunction due to leakage current can still be used to access data in practical applications. Therefore, the error recovery method of FIG10 provided in the exemplary embodiment of the present invention can further analyze the physical planes that can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0087] Referring to Figure 10, in step S1001, the memory management circuit 51 may record the first entity cell corresponding to the failed multi-plane operation as a first-level error in the bad block table. Specifically, the memory management circuit 51 may record the first entity cell corresponding to the multi-plane operation in the entity plane where the error occurred (also referred to as the first entity plane) as a first-level error. In an exemplary embodiment, the multi-plane operation may include, but is not limited to, write, erase, or read operations performed simultaneously on all entity planes in the rewritable non-volatile memory module 43.

[0088] In step S1002, the memory management circuit 51 can determine that the number of first physical planes that have erred is greater than a predetermined number (e.g., 1). If the number of first physical planes that have erred is not greater than the predetermined number, that is, only one physical plane in the rewritable non-volatile memory module 43 has erred, then proceed to step S1006. In step S1006, the memory management circuit 51 can update the first physical cell belonging to the first physical plane to a second-level error in the bad block table. In detail, since only one physical plane has erred, the first physical cell corresponding to the failed multi-plane operation is not affected by leakage current, so the memory management circuit 51 can, for example, determine that the first physical cell has physical wear and cannot continue to be used to access data. Therefore, the memory management circuit 51 can update the first physical cell to a second-level error in the bad block table.

[0089] Conversely, if the number of the first physical planes that err (e.g., 2) is greater than a predetermined number, that is, multiple physical planes in the rewritable non-volatile memory module 43 err, then proceed to step S1003. The predetermined number can be designed by the user according to actual needs, for example, and the present invention does not limit it.

[0090] In step S1003, the memory management circuit 51 can perform a corresponding single-plane operation on the first physical unit. The memory management circuit 51 can perform single-plane operations on the first physical units in the aforementioned two first physical planes respectively. In an exemplary embodiment, assuming the multi-plane operation is an erase operation, the memory management circuit 51 can perform a single-plane operation on the first physical units in the multiple first physical planes, wherein the single-plane operation is an erase retry operation. In an exemplary embodiment, assuming the multi-plane operation is a write operation or a read operation, the memory management circuit 51 can perform a single-plane operation on the first physical units in the multiple first physical planes, wherein the single-plane operation is an erase retry operation, a write retry operation (Program Retry Operation), or a read retry operation (Read Retry Operation).

[0091] In step S1004, the memory management circuit 51 can determine whether the single-plane operation is successful. If the single-plane operation is successful, proceed to step S1005. In an exemplary embodiment, if the single-plane operation for the first physical unit is successful, it means that the first physical unit is affected by leakage current, so the first physical unit does not have physical wear and can continue to be used to access data. Therefore, in step S1005, the memory management circuit 51 can remove the first physical unit from the bad block table, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0092] Conversely, if the single-plane operation fails, proceed to step S1006. In an exemplary embodiment, if the single-plane operation for the first physical unit fails, it indicates that the first physical unit may have physical wear and tear and cannot be used to access data. Therefore, in step S1006, the memory management circuit 51 can update the first physical unit from a first-level error to a second-level error in the bad block table.

[0093] According to the above, the error recovery method shown in FIG10 can perform corresponding single-plane operations on the entity units in the multiple entity planes where errors have occurred, so as to determine whether the entity units can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0094] FIG11 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. It should be noted that the error recovery method shown in FIG11 is a combination of the error recovery methods shown in FIG7 and FIG10, which can more accurately determine whether the entity unit corresponding to the multi-plane operation that failed to erase can continue to be used to access data.

[0095] Referring to Figure 11, in step S1101, the memory management circuit 51 may record the first physical cell corresponding to the failed erase operation (also referred to as the first operation) as a first-level error in the bad block table. In an exemplary embodiment, the erase operation is a multi-plane operation. The memory management circuit 51 may record the first physical cell belonging to the physical plane where the erase error occurred (i.e., the first physical plane) as a first-level error in the bad block table.

[0096] In step S1102, the memory management circuit 51 can determine whether the number of first physical planes is greater than a predetermined number (e.g., 1). If the number of first physical planes is not greater than the predetermined number, meaning that only one physical plane has an error, proceed to step S1107. In step S1107, the memory management circuit 51 can update the first physical cell to a second-level error in the bad block table. Specifically, since only one physical plane has an error, the first physical cell is not affected by leakage current. That is, the memory management circuit 51 can, for example, determine that the first physical cell has physical wear and cannot continue to be used to access data. Therefore, the memory management circuit 51 can update the first physical cell from a first-level error to a second-level error in the bad block table.

[0097] Conversely, if the number of first entity planes is greater than a predetermined number, meaning that multiple entity planes have encountered errors, then proceed to step S1103. In step S1103, the memory management circuit 51 can determine whether the current number of retries is less than a predetermined number (e.g., 2 times). Specifically, the memory management circuit 51 can determine whether the current number of retries of the first entity units in the multiple first entity planes that have encountered errors is greater than the predetermined number. If the current number of retries of a certain first entity unit is not less than the predetermined number, meaning that the current number of retries of this first entity unit has reached 2 times, the memory management circuit 51 can determine that this first entity unit cannot continue to be used to access data, and proceed to step S1107. In step S1107, the memory management circuit 51 can update this first entity unit from a first-level error to a second-level error in the bad block table.

[0098] On the other hand, if the current number of retries for a certain first entity cell (e.g., 0 times) is less than a predetermined number, the process proceeds to step S1104. In step S1104, the memory management circuit 51 can perform an erase retry operation for this first entity cell, wherein the erase retry operation is a single-plane operation. Subsequently, in step S1105, the memory management circuit 51 can determine whether the single-plane operation (i.e., the erase retry operation) was successful.

[0099] If the single-plane operation (erase retry operation) is successful, the memory management circuit 51 can determine that this first physical unit can continue to be used to access data, and proceed to step S1106. The memory management circuit 51 can associate this first physical unit with the idle area 602.

[0100] Conversely, if the single-plane operation (erase retry operation) fails, the process returns to step S1103 to determine again whether the current number of retries is less than the predetermined number. At this time, the current number of retries is 1, so the memory management circuit 51 can continue with steps S1104 and S1105 to perform the single-plane operation (erase retry operation) again on this first physical unit, and determine whether this single-plane operation (erase retry operation) is successful. If this single-plane operation (erase retry operation) is successful, the process proceeds to step S1106. Conversely, if this single-plane operation (erase retry operation) fails, the process returns to step S1103. At this time, the current number of retries is 2. Since the current number of retries has reached 2 (i.e., the predetermined number), the process proceeds to step S1107 to update this first physical unit from a first-level error to a second-level error in the bad block table.

[0101] According to the above, the error recovery method shown in FIG11 can perform a single-plane operation (erase retry operation) on the entity units in multiple entity planes that failed to erase, and in response to the success of the single-plane operation (erase retry operation), the entity unit is reassociated with the idle area 602 so that it can continue to be used to access data, thereby improving the access performance of the rewritable non-volatile memory module 43.

[0102] FIG12 is a flowchart illustrating an error recovery method according to an exemplary embodiment of the present invention. Referring to FIG12, in step S1201, in response to the failure of the first operation corresponding to the first entity unit, it is determined whether the current retry count is less than a predetermined count, wherein the current retry count is used to characterize the number of erase retry operations performed for the first entity unit. In step S1202, in response to the current retry count being less than the predetermined count, an erase retry operation is performed for the first entity unit. In step S1203, it is determined whether the erase retry operation is successful. In step S1204, in response to the success of the erase retry operation, the first entity unit is associated with the idle area.

[0103] The steps in Figure 12 have been described in detail above, and will not be repeated here. It is worth noting that each step in Figure 12 can be implemented as multiple pieces of code or circuits, and the present invention does not limit this. In addition, the method in Figure 12 can be used in conjunction with the above exemplary embodiments, or it can be used alone, and the present invention does not limit this.

[0104] In summary, the error recovery method, memory storage device, and memory control circuit unit provided in the exemplary embodiments of the present invention can further analyze whether the erroneous physical unit can continue to be used to access data by the number of erroneous physical planes, the number of erroneous bits of the physical unit, and / or by performing a retry operation for the physical unit. This can improve the access performance of the rewritable non-volatile memory module while maintaining the correctness of the data.

[0105] Although the present invention has been disclosed above with reference to exemplary embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0106] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention. Figure 8 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention. Figure 9 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention. Figure 10 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention. Figure 11 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention. Figure 12 is a flowchart of an error recovery method according to an exemplary embodiment of the present invention.

Claims

1. An error recovery method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, the error recovery method comprising: In response to a failure of the first operation corresponding to the first entity unit, the first entity unit is recorded as a first-level error in the bad block table, and it is determined whether the current retry count is less than a predetermined number, wherein the current retry count is used to represent the number of erase retry operations performed for the first entity unit; in response to the current retry count being less than the predetermined number, the erase retry operation is performed for the first entity unit; it is determined whether the erase retry operation is successful; and in response to the erase retry operation being successful, the first entity unit is associated with the idle area.

2. The error recovery method as described in claim 1 further includes: In response to the failure of the erase retry operation, it is determined again whether the current number of retries is less than the predetermined number.

3. The error recovery method as described in claim 1 further includes: When the current number of retries reaches the predetermined number, the number of error bits of the first entity cell is obtained based on the critical voltage. Determine whether the number of error bits is less than a predetermined number of bits; and in response that the number of error bits is not less than the predetermined number of bits, update the first entity unit to a second-level error in the bad block table.

4. The error recovery method as described in claim 3 further includes: In response to the number of error bits being less than the predetermined number of bits, the first entity unit is again associated with the idle area.

5. The error recovery method as described in Request 1 further includes: In response to the first operation being a multi-plane operation, it is determined whether the number of first entity planes is greater than a predetermined number, wherein the first entity plane is the entity plane where the error occurred; in response to the number being greater than the predetermined number, it is determined whether the current number of retries is less than the predetermined number; and in response to the current number of retries being less than the predetermined number, the erase retry operation is performed on the first entity unit belonging to the first entity plane, wherein the erase retry operation is a single-plane operation.

6. The error recovery method as described in claim 5 further includes: In response to the number not being greater than the predetermined number, the first entity unit is updated to a second-level error in the bad block table.

7. The error recovery method as described in claim 1 or 5 further includes: In response to the current number of retries being not less than the predetermined number, the first entity unit is updated to a second-level error in the bad block table.

8. A memory storage device, comprising: A connection interface unit coupled to the host system; a rewritable non-volatile memory module comprising multiple physical units; The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: in response to a failure of a first operation corresponding to a first physical unit, record the first physical unit as a first-level error in a bad block table, and determine whether the current retry count is less than a predetermined count, wherein the current retry count is used to characterize the number of erase retry operations performed for the first physical unit; in response to the current retry count being less than the predetermined count, perform the erase retry operation for the first physical unit; determine whether the erase retry operation is successful; and in response to the success of the erase retry operation, associate the first physical unit with an idle area.

9. The memory storage device as claimed in claim 8, wherein the memory control circuit unit is further configured to: in response to the erase retry operation failing, determine again whether the current number of retries is less than the predetermined number.

10. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: when the current number of retries reaches the predetermined number, obtain the number of error bits of the first physical cell based on a threshold voltage; determine whether the number of error bits is less than the predetermined number of bits; and, in response to the number of error bits being not less than the predetermined number of bits, update the first physical cell to a second-level error in the bad block table.

11. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to: associate the first physical unit with the idle area in response to the number of error bits being less than the predetermined number of bits.

12. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: determine whether the number of first physical planes is greater than a predetermined number in response to the first operation being a multi-plane operation, wherein the first physical plane is the physical plane where the error occurred; determine whether the current number of retries is less than the predetermined number in response to the number being greater than the predetermined number; and perform the erase retry operation for the first physical unit belonging to the first physical plane in response to the current number of retries being less than the predetermined number, wherein the erase retry operation is a single-plane operation.

13. The memory storage device as claimed in claim 12, wherein the memory control circuit unit is further configured to: update the first entity unit to a second-level error in the bad block table in response to the number not being greater than the predetermined number.

14. The memory storage device as claimed in claim 8 or 12, wherein the memory control circuit unit is further configured to: update the first entity unit to a second-level error in the bad block table in response to the current retry count being not less than the predetermined count.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control circuit unit includes: The host interface is coupled to the connection interface unit; The memory interface is coupled to the rewritable non-volatile memory module; The system also includes a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is configured to: in response to a failure of a first operation corresponding to a first physical unit, record the first physical unit as a first-level error in a bad block table, and determine whether the current retry count is less than a predetermined number, wherein the current retry count represents the number of erase retry operations performed on the first physical unit; in response to the current retry count being less than the predetermined number, perform the erase retry operation on the first physical unit; determine whether the erase retry operation is successful; and in response to the success of the erase retry operation, associate the first physical unit with an idle area.

16. The memory control circuit unit as claimed in claim 15, wherein the memory management circuit is further configured to: in response to the erase retry operation failing, determine again whether the current number of retries is less than the predetermined number.

17. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: when the current number of retries reaches the predetermined number, obtain the number of error bits of the first physical cell based on a threshold voltage; determine whether the number of error bits is less than the predetermined number of bits; and, in response that the number of error bits is not less than the predetermined number of bits, update the first physical cell to a second-level error in the bad block table.

18. The memory control circuit unit as claimed in claim 17, wherein the memory management circuit is further configured to: associate the first physical unit with the idle area in response to the number of error bits being less than the predetermined number of bits.

19. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: determine whether the number of first physical planes is greater than a predetermined number in response to the first operation being a multi-plane operation, wherein the first physical plane is the physical plane where the error occurred; determine whether the current number of retries is less than the predetermined number in response to the number being greater than the predetermined number; and perform the erase retry operation for the first physical unit belonging to the first physical plane in response to the current number of retries being less than the predetermined number, wherein the erase retry operation is a single-plane operation.

20. The memory control circuit unit as claimed in claim 19, wherein the memory management circuit is further configured to: update the first entity unit to a second-level error in the bad block table in response to the number not being greater than the predetermined number.

21. The memory control circuit unit as claimed in claim 15 or 19, wherein the memory management circuit is further configured to: update the first entity unit to a second-level error in the bad block table in response to the current retry count being not less than the predetermined count.

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