Reading method, memory storage device and memory control circuit unit

Abstract

The present disclosure provides a reading method, a memory storage device, and a memory control circuit unit. The reading method includes: applying a read pass voltage to multiple memory cells of a first physical unit; for each of multiple bit lines, calculating a cell cutoff number of the memory cells connected to the bit line and cut off when the read pass voltage is applied, wherein the cell cutoff number corresponding to a first bit line is different from the cell cutoff number corresponding to a second bit line; setting multiple different read voltages; and when reading a second physical unit, applying a first read voltage to the memory cells connected to the first bit line in the second physical unit, and applying a second read voltage to the memory cells connected to the second bit line in the second physical unit, thereby obtaining multiple data bits of the second physical unit.

Description

[Technical Field]

[0001] This disclosure relates to a method for reading a rewritable non-volatile memory module, which can solve the problem of loss of rewritable non-volatile memory modules. [Previous Technology]

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] On the other hand, with the development of artificial intelligence technology, the access frequency (especially the data writing frequency) of rewritable non-volatile memory modules by processing circuits such as the Central Processing Unit (CPU), Graphics Processing Unit (GPU), Video Processing Unit (VPU), Neural Network Processing Unit (NPU), and Tensor Processing Unit (TPU) has also greatly increased, resulting in a significant increase in the wear rate of rewritable non-volatile memory modules. Therefore, how to cope with the accelerated wear of rewritable non-volatile memory modules caused by the large number of access operations performed on them during the operation of artificial intelligence models is one of the research topics that those skilled in the art are committed to studying. [Summary of the Invention]

[0004] This disclosure proposes a reading method, a memory storage device, and a memory control circuit unit, which can solve the problem of the critical voltage rising after the physical cell is damaged.

[0005] This disclosure proposes a read method for a rewritable non-volatile memory module, the rewritable non-volatile memory module including multiple physical cells and multiple bit lines. The read method includes: applying a read-on voltage to multiple first memory cells of a first physical cell to determine whether the first memory cell is on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells off when connected to this bit line and turned off by the applied read-on voltage, wherein the number of memory cells off corresponding to the first bit line is different from the number of memory cells off corresponding to the second bit line; setting multiple read voltages, including a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; when reading a second physical cell, applying the first read voltage to a second memory cell in the second physical cell connected to the first bit line, and applying the second read voltage to a second memory cell in the second physical cell connected to the second bit line, thereby obtaining multiple first data bits of the second physical cell.

[0006] In one embodiment of this disclosure, the number of memory cells cut off corresponding to the first bit line is greater than the number of memory cells cut off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

[0007] In one embodiment of this disclosure, the step of setting the read voltage includes: setting the read voltage according to the number of memory cells cut off corresponding to the bit line, wherein the number of memory cells cut off and the read voltage are positively correlated.

[0008] In one embodiment of this disclosure, the above-described reading method further includes: determining whether the first data bit passes an error checking procedure; if the first data bit fails the error checking procedure, applying a read-on voltage to a plurality of third memory cells of the third entity unit to determine whether the third memory cells are on or off, wherein each third memory cell is connected to a bit line; for each bit line, calculating a memory cell cutoff distribution of the first memory cell and the third memory cell connected to the bit line and cut off when a read-on voltage is applied, wherein the memory cell cutoff distribution corresponding to the first bit line is different from the memory cell cutoff distribution corresponding to the second bit line; and applying a third read voltage to the second memory cell in the second entity unit connected to the first bit line, and applying a fourth read voltage to the second memory cell in the second entity unit connected to the second bit line, thereby reading a plurality of second data bits of the second entity unit.

[0009] In one embodiment of this disclosure, the number of first and third memory cells connected to the first bit line and turned off when a read-on voltage is applied is greater than the number of first and third memory cells connected to the second bit line and turned off when a read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

[0010] In one embodiment of this disclosure, the above-described reading method further includes: storing the memory cell cutoff distribution corresponding to the bit line in a buffer memory; and when reading the second physical unit, reading the memory cell cutoff distribution from the buffer memory to determine that the first bit line corresponds to the first reading voltage and the second bit line corresponds to the second reading voltage.

[0011] In one embodiment of this disclosure, the second entity unit described above is different from at least the first entity unit.

[0012] From another perspective, embodiments of the present invention provide a memory storage device, including: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module including multiple physical units and multiple bit lines; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit performs multiple steps: applying a read-on voltage to a plurality of first memory cells of the first physical unit to determine whether the first memory cells are on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells that are off when the first memory cell connected to this bit line is turned off when the read-on voltage is applied, wherein the number of memory cells turned off corresponding to the first bit line is different from the number of memory cells turned off corresponding to the second bit line; setting a plurality of read voltages, including a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; when reading the second physical unit, applying the first read voltage to the second memory cell in the second physical unit connected to the first bit line, and applying the second read voltage to the second memory cell in the second physical unit connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical unit.

[0013] From another perspective, embodiments of the present invention provide a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface. The memory management circuit performs multiple steps: applying a read-on voltage to a plurality of first memory cells of a first physical cell to determine whether the first memory cells are on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells that are off when a read-on voltage is applied to the first bit line, wherein the number of memory cells off corresponding to the first bit line is different from the number of memory cells off corresponding to the second bit line; setting a plurality of read voltages, including a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; when reading a second physical cell, applying the first read voltage to the second memory cells in the second physical cell connected to the first bit line, and applying the second read voltage to the second memory cells in the second physical cell connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical cell.

[0014] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0016] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of systems and methods within the scope of the present invention's patent application.

[0017] The terms "first" and "second" used in this document do not specifically refer to order or sequence, but are used only to distinguish elements or operations described with the same technical terms.

[0018] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0019] FIG1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. FIG2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention.

[0020] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0021] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0022] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0023] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0024] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0025] FIG3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0026] FIG4A is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG4A, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0027] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0028] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0029] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0030] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in that memory cell.

[0031] Figure 4B is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention. Referring to Figure 4B, the memory cell array 44 includes a plurality of memory cells 402 for storing data, a plurality of select gate drain (SGD) transistors 412 and a plurality of select gate source (SGS) transistors 414, a plurality of bit lines 404(1) to 404(3) connecting these memory cells 402, a plurality of word lines 406(1) to 406(N), and a common source line 408, where N is a positive integer. In particular, the memory cells 402 are arranged in an array at the intersections of the bit lines 404(1) to 404(3) and the word lines 406(1) to 406(N), as shown in Figure 4B. Figure 4B is merely an example, and the present invention does not limit the number of word lines and bit lines in a memory cell array 44. In addition, the rewritable non-volatile memory module 43 may include multiple memory cell arrays 44. These memory cell arrays 44 may be stacked horizontally and / or vertically.

[0032] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, the physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0033] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0034] FIG5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0035] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42 and the memory storage device 10.

[0036] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0037] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory management circuit 51 has a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0038] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit processes data to be written to and read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0039] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0040] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0041] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0042] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0043] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0044] In one exemplary embodiment, the rewritable nonvolatile memory module 43 of FIG4A may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4A may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0045] FIG6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG6, the memory management circuit 51 can logically group the physical units 610(0) to 610(C) in the rewritable non-volatile memory module 43 into the storage area 601, the spare area 602 and the system area 603.

[0046] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses.

[0047] In an exemplary embodiment, entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0048] In one exemplary embodiment, the memory management circuit 51 may configure logic units 612(0) to 612(D) to map physical units 610(0) to 610(A) in the storage area 601. In one exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In one exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logic addresses.

[0049] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0050] In one exemplary embodiment, the memory management circuit 51 may record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table (L2P table). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0051] In one exemplary embodiment, the memory management circuit 51 may store specific types of data in the system area 603. For example, physical units 610(B+1) to 610(C) in the system area 603 may be dedicated to storing data of high importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of high importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logic-to-entity mapping table, a bad block management table, a wear leveling table, a valid data management table, and / or other types of management data, which are not limited by the present invention. The logic-to-entity mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between logic units and physical units. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling table may be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table can be used to record information related to the valid count of at least one physical cell in the rewritable non-volatile memory module 43.

[0052] In one exemplary embodiment, the memory management circuit 51 may not map any logic units to physical units in the system area 603. This prevents data stored in the system area 603 from being accessed or modified by the host system 11.

[0053] The read-on voltage is described here. The read-on voltage is applied to other physical cells to turn on the memory cells in other physical cells when reading one physical cell. Figure 7 is a schematic diagram illustrating the read-on voltage according to an embodiment. Referring to Figure 7, when reading a physical cell on word line 406 (5), the memory management circuit 51 applies a read voltage Vr to the memory cell connected to word line 406 (5) and simultaneously applies a read-on voltage Vp to the memory cells on other word lines 406 (1) to 406 (4) and 406 (6) to 406 (N). Generally, the memory cell should be turned on when the read-on voltage is applied. Therefore, multiple bits obtained from bit lines 404 (1) to 404 (3) will reflect whether the memory cell on word line 406 (5) is turned on. For example, when a memory cell on word line 406 (5) is turned on, a bit "1" can be obtained on the corresponding bit line, and vice versa. However, in some applications (such as artificial intelligence), the rewritable non-volatile memory module 43 is frequently read, written, or erased, which raises the critical voltage of the memory cells, even exceeding the read-on voltage, affecting the reading of physical cells. For example, when the critical voltage of one or more memory cells on word line 406(6) exceeds the read-on voltage, these memory cells will be turned off, thus changing the bits obtained on the corresponding bit lines. When the critical voltage of a memory cell exceeds the read-on voltage, this memory cell is called an open bit. In the following embodiments, the read voltage will be determined based on the number or distribution of open bits.

[0054] Figure 8 is a flowchart illustrating a read method according to an embodiment. This method is executed by the memory management circuit 51, and will not be described in detail below. Referring to Figure 8, in step 801, a read turn-on voltage is applied to a plurality of memory cells (also referred to as first memory cells) of the first physical unit to determine whether the first memory cells are turned on or off. Here, the first physical unit is not the physical unit to be read, but as mentioned above, whether there are cut-off bits in other physical units will affect the physical unit to be read. The number of first physical units can be one or more. Here, we will take one first physical unit as an example. Figure 9 is a schematic diagram illustrating the application of a read voltage according to an embodiment. In the embodiment of Figure 9, a read turn-on voltage Vp is applied to the first physical unit on word line 406 (2). For memory cells on other word lines, the same or higher voltage can be applied. When the voltage on word line 406(2) is lower than the voltage on other word lines, the memory cells on other word lines are more likely to be turned on. Thus, based on the bits sensed on bit lines 404(1)~404(3), it can be determined whether each first memory cell on word line 406(2) is turned on. When the voltage on word line 406(2) is the same as the voltage on other word lines, based on the bits sensed on bit lines 404(1)~404(3), it can be determined whether there are any memory cells on the corresponding bit lines that are off. This information also reflects the degree of degradation of this physical block and can be used to determine the read voltage.

[0055] In step 802, for each bit line, the number of first memory cells connected to this bit line and turned off when a read turn-on voltage is applied is calculated (referred to as the number of memory cell turn-offs). Here, it is assumed that the first memory cells connected to bit line 404(1) and word line 406(2) are turned on when a read turn-on voltage Vp is applied; the first memory cells connected to bit line 404(2) and word line 406(2) are turned off when a read turn-on voltage Vp is applied; and the first memory cells connected to bit line 404(3) and word line 406(2) are turned on when a read turn-on voltage Vp is applied. Therefore, the number of memory cell turn-offs corresponding to bit line 404(1) is 0, the number of memory cell turn-offs corresponding to bit line 404(2) is 1, and the number of memory cell turn-offs corresponding to bit line 404(3) is 0. In other words, the number of memory cell cutoffs corresponding to bit lines 404(1) and 404(3) is different from the number of memory cell cutoffs corresponding to bit line 404(2).

[0056] In step 803, multiple different read voltages are set. One of these read voltages may be the same as a preset read voltage, while the other may be greater than the preset read voltage. Here, the two read voltages are referred to as the first read voltage and the second read voltage, respectively.

[0057] In step 804, when reading the second entity unit (e.g., the entity unit on word line 406(5)), a first read voltage V1 is applied to the memory cell in the second entity unit connected to bit line 404(2), and a second read voltage V2 is applied to the memory cell in the second entity unit connected to bit lines 404(1) and 404(3), thereby obtaining multiple data bits of the second entity unit. Here, the first read voltage V1 and the second read voltage V2 are applied to word line 406(5) at different times. For example, firstly, the first read voltage V1 is applied to word line 406(5), a read conduction voltage is applied to other word lines, and one bit is obtained from bit line 404(2); then, the second read voltage V2 is applied to word line 406(5), a read conduction voltage is applied to other word lines, and two bits are obtained from bit lines 404(1) and 404(3). The three bits obtained above are the multiple data bits in the second entity unit.

[0058] In some embodiments, the number of memory cells cutoff is positively correlated with the read voltage. For example, the number of memory cells cutoff corresponding to bit line 404(2) is greater than the number of memory cells cutoff corresponding to bit lines 404(1) and 404(3). Therefore, the first read voltage V1 can be set to be greater than the second read voltage V2.

[0059] As described above, the second physical cell on word line 406(5) is different from the first physical cell on word line 406(2). In other words, when reading a physical cell, the read voltage is determined based on the cutoff bits on other physical cells. In some embodiments, the position of the first physical cell can be predetermined. After the rewritable non-volatile memory module 43 is manufactured, any detection method can be used to determine which memory cells on word lines are prone to defects, and therefore the physical cells on these word lines will be set as the first physical cells described above. In some embodiments, different first physical cells can be set on different physical blocks or different dies to reflect different physical characteristics.

[0060] The number of the first entity units is 1, but in other embodiments the number of the first entity units may be greater than 1. For example, in FIG10, a read turn-on voltage Vp is first applied to the memory cells of the first entity units on word lines 406(2) and 406(7) to determine whether these memory cells are turned on or off. Then, for each bit line, the number of memory cells connected to this bit line and turned off when the read turn-on voltage Vp is applied is calculated (called the memory cell cutoff number). The possible values ​​of the memory cell cutoff number include 0, 1 and 2, and different memory cell cutoff numbers correspond to different read voltages. In some embodiments, the read voltage can be set according to the memory cell cutoff number, such that the memory cell cutoff number and the read voltage are positively correlated. For example, when the memory cell cutoff number is equal to 2, a first read voltage is used; when the memory cell cutoff number is equal to 1, a second read voltage is used; when the memory cell cutoff number is equal to 0, a third read voltage is used, wherein the first read voltage is greater than the second read voltage, and the second read voltage is greater than the third read voltage.

[0061] In some embodiments, if the number of memory cells cut off on two bit lines is the same but the positions of the cut-off bits are different, different read voltages can also be used. For example, referring to FIG11, when a read-on voltage is applied to word lines 406(2) and 406(7), the memory cells connected to word line 406(2) and bit line 404(1) are cut off, the memory cells connected to word line 406(2) and bit line 404(2) are turned on, the memory cells connected to word line 406(2) and bit line 404(3) are turned on, the memory cells connected to word line 406(7) and bit line 404(1) are turned on, the memory cells connected to word line 406(7) and bit line 404(2) are turned on, and the memory cells connected to word line 406(7) and bit line 404(3) are cut off. In such an example, the number of cutoff bits for both bit line 404(1) and bit line 404(3) is 1, but the cutoff bit on bit line 404(1) occurs on word line 406(2), while the cutoff bit on bit line 404(3) occurs on word line 406(7). Multiple groups can be generated based on the distribution of cutoff bits on a bit line, with each bit line belonging to one of these groups. This distribution can be represented by multiple bits, each indicating whether there is a cutoff bit on the corresponding word line. There are 2 groups (cutoff or on) when a read-on voltage is applied to 1 word line, 4 groups when a read-on voltage is applied to 2 word lines, 8 groups when a read-on voltage is applied to 3 word lines, 16 groups when a read-on voltage is applied to 4 word lines, and so on. For example, in the embodiment of Figure 11, the four groups can be represented as shown in Table 1 below. Character line 406(2) Character line 406(7) Group 1 1 1 Second Group 1 0 Third Group 0 1 Group 4 0 0 Table 1

[0062] In Table 1, “1” indicates that the corresponding memory cell is a cutoff bit, and “0” indicates a non-cutoff bit. Specifically, bit line 404(1) belongs to the second group, bit line 404(2) belongs to the fourth group, and bit line 404(3) belongs to the third group. The first to fourth groups mentioned above correspond to the first read voltage V1 to the fourth read voltage V4, respectively. Therefore, when reading the physical unit on word line 406(5), the second read voltage V2, the fourth read voltage V4, and the third read voltage V3 can be applied to word line 406(5) at different time points to read data bits from the memory cells connected to bit lines 404(1) to 404(3), respectively. It is worth noting that Figure 11 shows the application of the first to fourth read voltages V1 to V4 to word line 406(5), because the actual number of bit lines is much greater than 3, so some bit lines will also belong to the first group (using the first read voltage V1).

[0063] FIG12 is a flowchart illustrating a read method according to another embodiment. In the embodiment of FIG12, the number of word lines to which a read turn-on voltage is applied gradually increases. In step 1201, a read turn-on voltage is applied to a plurality of first memory cells of the first physical unit to determine whether the first memory cells are turned on or off. This step 1201 is the same as step 801.

[0064] In step 1202, for each bit line, the distribution of memory cells that are cut off when a read-on voltage is applied to this bit line is calculated (referred to as the memory cell cutoff distribution). Here, the memory cell cutoff distribution may include the location information of each cutoff bit (see Table 1). When the number of the first entity cells is M, there are 2^M different memory cell cutoff distributions, where M is a positive integer.

[0065] In step 1203, multiple different read voltages are set. For example, a different read voltage can be set for each memory cell cutoff distribution.

[0066] In step 1204, when reading the second physical unit, different read voltages are applied to different memory cell cutoff distributions to obtain data bits from the corresponding bit lines. For example, in the embodiment of FIG11, the memory cell cutoff distributions of bit lines 404(1) to 404(3) are different from each other, so three different read voltages are applied to word line 406(5).

[0067] In step 1205, it is determined whether the acquired data bits (also referred to as the first data bits) have passed an error checking procedure, for example, whether these first data bits can be completely corrected according to the error correction code. If the error checking procedure has not passed, in step 1206, another physical unit (referred to as the third physical unit) is selected, and then a read-on voltage is applied to the third physical unit to determine whether the memory cell in the third physical unit is turned on or off. FIG13 is a schematic diagram illustrating the selection of the third physical unit according to an embodiment. FIG13 is a continuation of the embodiment of FIG11, assuming that the additionally selected is word line 406 (8). After applying the read-on voltage Vp to the third physical unit on word line 406 (8), the memory cell connected to bit line 404 (1) is turned on, the memory cell connected to bit line 404 (2) is turned off, and the memory cell connected to bit line 404 (3) is turned off.

[0068] Next, we return to step 1202 and recalculate the memory cell cutoff distribution. This time, we calculate not only the memory cells of word lines 406(2) and 406(7), but also the memory cell of word line 406(8). Since there are currently three word lines with read-on voltage Vp applied, there are a total of 8 memory cell cutoff distributions (i.e., 8 groups), which can be represented as shown in Table 2 below. Character line 406(2) Character line 406(7) Character line 406(8) Group 1 1 1 1 Second Group 1 1 0 Third Group 1 0 1 Group 4 1 0 0 Group 5 0 1 1 Group 6 0 1 0 Group 7 0 0 1 Group 8 0 0 0 Table 2

[0069] Similarly, in Table 2, “1” indicates that the corresponding memory cell is a cutoff bit, and “0” indicates a non-cutoff bit. In the example of Figure 13, bit line 404(1) belongs to the fourth group, bit line 404(2) belongs to the seventh group, and bit line 404(3) belongs to the fifth group. In other words, the cutoff distributions of memory cells of bit lines 404(1) to 404(3) are different from each other.

[0070] In step 1203, multiple read voltages are set. After adding a word line, eight different read voltages can be set, corresponding to the eight groups mentioned above. These eight read voltages can be determined experimentally. Assume that the first to eighth groups correspond to the first to eighth read voltages respectively. In some embodiments, when the number of cutoff bits in a group is large, the corresponding read voltage is also large. For example, the first group has three cutoff bits, the second group has two cutoff bits, and the fourth group has one cutoff bit; therefore, the first read voltage will be greater than the second read voltage, and the second read voltage will be greater than the fourth read voltage.

[0071] In step 1204, when reading the second physical unit on word line 406(5) again, different read voltages are applied for different memory cell cutoff distributions to obtain data bits from the corresponding bit lines. In this example, a fourth read voltage can be applied to word line 406(5) first to obtain a data bit from bit line 404(1), then a fifth read voltage can be applied to word line 406(5) to obtain a data bit from bit line 404(3), and then a seventh read voltage can be applied to word line 406(5) to obtain a data bit from bit line 404(2).

[0072] The three data bits obtained above will be judged in step 1205. If they still fail the error checking procedure, another entity unit will be selected in step 1206. The above approach can gradually increase the decoding capability and avoid reading too many times at the beginning, thus avoiding too much time or computing resources being spent.

[0073] Referring to Figure 5, in some embodiments, the memory management circuit 51 can apply a read on voltage to multiple physical cells in advance (e.g., during idle time). After calculating the number of memory cell cutoffs or the memory cell cutoff distribution corresponding to each bit line, these memory cell cutoffs or memory cell cutoff distributions can be stored in the buffer memory 55. When a physical cell needs to be read, the memory management circuit 51 can read the number of memory cell cutoffs or the memory cell cutoff distribution from the buffer memory 55, thereby determining which read voltage to apply to which memory cell on which bit line. In this way, the read speed can be increased.

[0074] In the above embodiment, when reading the second physical unit, the reading voltage is determined based on the cutoff bits on the first physical unit. In other embodiments, the initial reading voltage of the second physical unit can also be determined based on the number of cutoff bits on the second physical unit. Generally, the larger the number of cutoff bits on the second physical unit, the larger the initial reading voltage. Here, the number of cutoff bits can be converted into the reading voltage through a function or a lookup table.

[0075] In some embodiments, the processes described in Figures 8 and 12 are performed only after a general read procedure fails. For example, the read procedure may include a hardware decoding procedure and a software decoding procedure. In the hardware decoding procedure, a read voltage (i.e., an initial read voltage) is set, and data bits can be obtained based on whether the corresponding memory cell is turned on under this read voltage. Next, an error correction code decoding procedure is performed on these data bits to correct the erroneous bits. If the number of erroneous bits exceeds the correction capability of the error correction code, it indicates that the hardware decoding procedure has failed. When the hardware decoding procedure fails, a software decoding procedure is performed. In the software decoding procedure, multiple read voltages are set, and a probability value can be calculated based on whether the corresponding memory cell is turned on under these read voltages. Next, an error correction code (e.g., LDPC) decoding procedure is performed on these probability values ​​to obtain the final data bits. If these data bits cannot be completely corrected, it indicates that the software decoding procedure has failed. When the software decoding procedure fails, the process described in Figure 8 or Figure 12 is performed. In one embodiment, the software decoding program still has 214 error bits, but by setting 16 groups to adjust the read voltage, the number of error bits is reduced to 131. In other words, the above approach can reduce the number of error bits.

[0076] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0015] FIG1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. FIG2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention. FIG3 is a schematic diagram of a host system and memory storage device according to an exemplary embodiment of the present invention. FIG4A is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG4B is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention. FIG5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. FIG6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG7 is a schematic diagram illustrating a read on voltage according to an embodiment. FIG8 is a flowchart illustrating a read method according to an embodiment. FIG9 is a schematic diagram illustrating applying a read voltage according to an embodiment. FIG10 is a schematic diagram illustrating applying a read voltage according to an embodiment. FIG11 is a schematic diagram illustrating applying a read voltage according to an embodiment. FIG12 is a flowchart illustrating a read method according to another embodiment. Figure 13 is a schematic diagram illustrating the selection of a third entity unit according to one embodiment.

Claims

1. A reading method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical cells and multiple bit lines, and the reading method includes: A read-on voltage is applied to a plurality of first memory cells of at least one first physical cell to determine whether the first memory cells are on or off, wherein each of the first memory cells is connected to one of the bit lines; for each of the bit lines, a number of memory cells that are off when the read-on voltage is applied to the first memory cells connected to the bit line are calculated, wherein the bit lines include a first bit line and a second bit line, and the number of memory cells off corresponding to the first bit line is different from the number of memory cells off corresponding to the second bit line; a plurality of read voltages are set, wherein the read voltages include a first read voltage and a second read voltage, and the first read voltage is different from the second read voltage; when reading a second physical cell of the physical cells, the first read voltage is applied to a second memory cell in the second physical cell connected to the first bit line, and the second read voltage is applied to a second memory cell in the second physical cell connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical cell.

2. The reading method as described in claim 1, wherein the number of memory cells cutoff corresponding to the first bit line is greater than the number of memory cells cutoff corresponding to the second bit line, and the first reading voltage is greater than the second reading voltage.

3. The reading method as described in claim 1, wherein the step of setting the reading voltages includes: The read voltages are set according to the number of memory cells cutoff corresponding to the bit lines, wherein the number of memory cells cutoff and the read voltages are positively correlated.

4. The reading method as described in request item 1 further includes: Determine whether these first data bits have passed an error checking procedure; If the first data bits fail the error checking procedure, the read-on voltage is applied to a plurality of third memory cells in a third entity cell of the physical units to determine whether the third memory cells are on or off, wherein each of the third memory cells is connected to one of the bit lines; for each of the bit lines, a cell cutoff distribution of the first and third memory cells connected to the bit line and cut off when the read-on voltage is applied is calculated, wherein the cell cutoff distribution corresponding to the first bit line is different from the cell cutoff distribution corresponding to the second bit line; and a third read voltage is applied to the second memory cell in the second physical unit connected to the first bit line, and a fourth read voltage is applied to the second memory cell in the second physical unit connected to the second bit line, thereby reading a plurality of second data bits of the second physical unit.

5. The read method as claimed in claim 4, wherein the number of the first memory cells and the third memory cells connected to the first bit line and turned off when the read turn-on voltage is applied is greater than the number of the first memory cells and the third memory cells connected to the second bit line and turned off when the read turn-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

6. The reading method as described in request item 4 further includes: The cutoff distribution of these memory cells corresponding to these bit lines is stored in a buffer memory; And when reading the second physical unit, the cutoff distribution of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

7. The reading method as described in claim 1, wherein the second entity unit is different from the at least one first entity unit.

8. A memory storage device, comprising: A connection interface unit for coupling to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical cells and multiple bit lines; The module includes a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, for performing multiple steps: applying a read-on voltage to a plurality of first memory cells of at least one first physical cell of the physical cells to determine whether the first memory cells are on or off, wherein each of the first memory cells is connected to one of the bit lines; for each of the bit lines, calculating the number of memory cells off when connected to the bit line and turned off by the applied read-on voltage, wherein the bit lines include a first bit line and a second bit line, the number of memory cells off corresponding to the first bit line being different from the number of memory cells off corresponding to the second bit line; setting a plurality of read voltages, wherein the read voltages include a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; When reading a second physical cell among these physical cells, the first read voltage is applied to the second memory cell in the second physical cell connected to the first bit line, and the second read voltage is applied to the second memory cell in the second physical cell connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical cell.

9. The memory storage device as claimed in claim 8, wherein the number of memory cell cutoffs corresponding to the first bit line is greater than the number of memory cell cutoffs corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

10. The memory storage device as claimed in claim 8, wherein the step of setting the read voltages includes: The read voltages are set according to the number of memory cells cutoff corresponding to the bit lines, wherein the number of memory cells cutoff and the read voltages are positively correlated.

11. The memory storage device as claimed in claim 8, wherein the steps further include: Determine whether the first data bits pass an error checking procedure; if the first data bits fail the error checking procedure, apply the read-on voltage to a plurality of third memory cells of a third entity cell in the entity cells to determine whether the third memory cells are on or off, wherein each of the third memory cells is connected to one of the bit lines; for each of the bit lines, calculate a cell cutoff distribution of the first and third memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the cell cutoff distribution corresponding to the first bit line is different from the cell cutoff distribution corresponding to the second bit line; and apply a third read voltage from the read voltages to the second memory cell in the second entity cell connected to the first bit line, and apply a fourth read voltage from the read voltages to the second memory cell in the second entity cell connected to the second bit line, thereby reading a plurality of second data bits of the second entity cell.

12. The memory storage device of claim 11, wherein the number of the first memory cells and the third memory cells connected to the first bit line and turned off when the read-on voltage is applied is greater than the number of the first memory cells and the third memory cells connected to the second bit line and turned off when the read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

13. The memory storage device as claimed in claim 11, wherein the steps further include: The cutoff distribution of these memory cells corresponding to these bit lines is stored in a buffer memory; And when reading the second physical unit, the cutoff distribution of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

14. The memory storage device as claimed in claim 8, wherein the second physical unit is different from the at least one first physical unit.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical cells and a plurality of bit lines, and the memory control circuit unit includes: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit, coupled to the host interface and the memory interface, performs multiple steps: applying a read-on voltage to a plurality of first memory cells of at least one first physical cell to determine whether the first memory cells are on or off, wherein each of the first memory cells is connected to one of the bit lines; for each of the bit lines, calculating the number of memory cells off when connected to the bit line and turned off by the applied read-on voltage, wherein the bit lines include a first bit line and a second bit line, the number of memory cells off corresponding to the first bit line being different from the number of memory cells off corresponding to the second bit line; setting a plurality of read voltages, wherein the read voltages include a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; When reading a second physical cell among these physical cells, the first read voltage is applied to the second memory cell in the second physical cell connected to the first bit line, and the second read voltage is applied to the second memory cell in the second physical cell connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical cell.

16. The memory control circuit unit as claimed in claim 15, wherein the number of memory cells cut off corresponding to the first bit line is greater than the number of memory cells cut off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

17. The memory control circuit unit as claimed in claim 15, wherein the step of setting the read voltages includes: The read voltages are set according to the number of memory cells cutoff corresponding to the bit lines, wherein the number of memory cells cutoff and the read voltages are positively correlated.

18. The memory control circuit unit as claimed in claim 15, wherein the steps further include: Determine whether the first data bits pass an error checking procedure; if the first data bits fail the error checking procedure, apply the read-on voltage to a plurality of third memory cells of a third entity cell in the entity cells to determine whether the third memory cells are on or off, wherein each of the third memory cells is connected to one of the bit lines; for each of the bit lines, calculate a cell cutoff distribution of the first and third memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the cell cutoff distribution corresponding to the first bit line is different from the cell cutoff distribution corresponding to the second bit line; and apply a third read voltage from the read voltages to the second memory cell in the second entity cell connected to the first bit line, and apply a fourth read voltage from the read voltages to the second memory cell in the second entity cell connected to the second bit line, thereby reading a plurality of second data bits of the second entity cell.

19. The memory control circuit unit of claim 18, wherein the number of the first memory cells and the third memory cells connected to the first bit line and turned off when the read turn-on voltage is applied is greater than the number of the first memory cells and the third memory cells connected to the second bit line and turned off when the read turn-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

20. The memory control circuit unit as claimed in claim 18, wherein the steps further include: The cutoff distribution of these memory cells corresponding to these bit lines is stored in a buffer memory; And when reading the second physical unit, the cutoff distribution of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

21. The memory control circuit unit as claimed in claim 15, wherein the second physical unit is different from the at least one first physical unit.

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