Etching through silicon vias having different sizes with minimum depth loading

TW202634659APending Publication Date: 2026-08-16LAM RES CORP
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
TW114139421
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-10-15
Filing Date
2025-10-14
Publication Date
2026-08-16

Smart Images

  • Figure TWG2TA001072749_001
    Figure TWG2TA001072749_001
  • Figure TWG2TA001072749_002
    Figure TWG2TA001072749_002
  • Figure TWG2TA001072749_003
    Figure TWG2TA001072749_003
Patent Text Reader

Abstract

A method for etching a substrate includes providing a substrate including a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively. The first CD and the second CD are different. The method includes depositing a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and performing a rapid alternating process including a plurality of cycles. Each of the plurality of cycles includes a deposition step, a clear step, and an etch step.
Need to check novelty before this filing date? Find Prior Art