Digital-to-analog conversion apparatus and method having signal calibration mechanism

Abstract

A digital-to-analog conversion apparatus having a signal calibration mechanism is provided. A digital-to-analog conversion circuit performs conversion according to signal feeding related to an input digital signal including an odd part that has a rounding error and an even part to generate an output analog signal. An echo transmission circuit processes an echo path to generate an echo signal. An echo calibration circuit performs mapping according to codeword offset tables and performs processing according to response coefficients on the odd and the even parts to generate an echo canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal of between the echo signal and the echo canceling calibration signal and path information related to the echo calibration signal. The echo calibration circuit sets initial values to converge the response coefficients according to the error signal and updates the codeword offset tables according to the offsets.

Claims

1. A digital-to-analog converter with a signal correction mechanism, comprising: a digital-to-analog converter circuit including a complex current source operating at a first frequency to convert based on a signal feed associated with an input digital signal having an input codeword, generating an output analog signal, wherein the signal feed includes an odd portion and an even portion, the odd portion including a round-off error; an echo transmission circuit to process an echo path to downsample and generate an echo signal having a second frequency, wherein the second frequency is half of the first frequency; and an echo correction circuit operating at the second frequency to map based on the odd portion and the even portion using a complex digital character deviation table and to process based on at least one set of response coefficients, respectively, to generate at least one echo cancellation correction signal; A calibration parameter calculation circuit, operating at the second frequency, generates a complex offset based on an error signal of the echo signal relative to one of the at least one echo cancellation correction signals and path information associated with the echo correction circuit, wherein the echo correction circuit sets an initial value for the at least one set of response coefficients to converge the at least one set of response coefficients according to the error signal, and updates the complex codeword offset table according to the offsets; and a signal input circuit configured to transmit the signal feed to the digital-to-analog conversion circuit, comprising: a rounding error calculation circuit; an odd-number filtering circuit that filters the input digital signal according to a set of odd-number filtering coefficients, and superimposes the rounding error by the rounding error calculation circuit to generate the odd-number portion of the signal feed, wherein the set of odd-number filtering coefficients includes a decimal component; and an even-number filtering circuit that filters the input digital signal according to a set of even-number filtering coefficients to generate the even-number portion of the signal feed, wherein the set of even-number filtering coefficients does not include the decimal component.

2. The digital-to-analog conversion device as claimed in claim 1, wherein the echo correction circuit comprises: an odd correction circuit, comprising: an odd mapping circuit that receives the odd portion minus the rounding error and maps it according to an odd digit offset table in the codeword offset table to generate an odd mapping signal; and an odd response circuit that receives the odd mapping signal and processes it according to a set of odd response coefficients in the at least one set of response coefficients to generate an odd correction signal included in the at least one echo cancellation correction signal; and an even correction circuit, comprising: an even mapping circuit that receives the even portion and maps it according to an even digit offset table in the codeword offset table to generate an even mapping signal; and an even response circuit that receives the even mapping signal and processes it according to a set of even response coefficients in the at least one set of response coefficients to generate an even correction signal included in the at least one echo cancellation correction signal.

3. The digital-to-analog conversion device as described in claim 2 further includes a residual echo cancellation circuit, comprising: a residual echo filtering circuit that receives the input digital signal and filters it according to the set of odd filter coefficients and the set of even filter coefficients to generate a filtering result; a residual echo response circuit that receives the filtering result and processes it according to the set of odd response coefficients and the set of even response coefficients to generate a residual echo cancellation signal; and a cancellation circuit that subtracts the residual echo cancellation signal from the error signal to generate a final error signal; wherein the correction parameter calculation circuit actually converges the at least one set of response coefficients according to the final error signal and generates the offsets according to the final error signal and the path information associated with the echo correction circuit.

4. The digital-to-analog conversion device described in claim 1 further includes a residual echo cancellation circuit; wherein the echo correction circuit includes: an odd mapping circuit that receives the odd portion minus the rounding error and maps it according to an odd digit offset table in the codeword offset table to generate an odd mapping signal; an even mapping circuit that receives the even portion and maps it according to an even digit offset table in the codeword offset table to generate an even mapping signal; an odd filtering circuit that filters the even mapping signal according to a set of odd filtering coefficients to generate a filtered signal; a merging circuit that subtracts the odd mapping signal and the filtered signal to generate a merged signal; and an odd response circuit that receives the merged signal and processes it according to a set of odd response coefficients to generate the at least one echo cancellation correction signal; and the residual echo cancellation circuit includes: a residual echo even mapping circuit that receives the input digital signal and maps it according to an even digit offset table to generate a residual echo even mapping signal; A residual echo filter circuit receives the input digital signal and the residual echo even-number mapping signal, and filters them according to a set of odd-number filtering coefficients and a set of even-number filtering coefficients to produce a filtering result; a residual echo response circuit receives the filtering result and processes it according to a set of odd-number response coefficients and a set of even-number response coefficients to produce a residual echo cancellation signal; and a cancellation circuit subtracts the residual echo cancellation signal and an error signal of the echo signal relative to the echo cancellation correction signal to produce a final error signal; wherein the correction parameter calculation circuit actually converges the at least one set of response coefficients according to the final error signal, and generates the offsets according to the final error signal and the path information associated with the echo correction circuit.

5. A digital-to-analog conversion method with a signal correction mechanism, comprising: filtering an input digital signal having an input codeword according to a set of odd-numbered filtering coefficients by an odd-numbered filtering circuit included in a signal input circuit configured to feed a signal into a digital-to-analog conversion circuit, and superimposing a rounding error by a rounding error calculation circuit included in the signal input circuit to generate an odd-numbered portion of the signal feed, wherein the set of odd-numbered filtering coefficients includes a decimal component; filtering the input digital signal according to a set of even-numbered filtering coefficients by an even-numbered filtering circuit included in the signal input circuit to generate an even-numbered portion of the signal feed, wherein the set of even-numbered filtering coefficients does not include the decimal component; and converting the digital-to-analog conversion circuit including a complex current source operating at a first frequency according to the signal feed associated with the input digital signal to generate an output analog signal. An echo transmission circuit processes an echo path to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency; an echo correction circuit operating at the second frequency maps the odd and even portions of the echo signal to a complex codeword offset table and processes it with at least one set of response coefficients to generate at least one echo cancellation correction signal; and a correction parameter calculation circuit operating at the second frequency generates a complex offset based on an error signal of the echo signal relative to the at least one echo cancellation correction signal and path information associated with the echo correction circuit, wherein the echo correction circuit sets an initial value for the at least one set of response coefficients to converge the at least one set of response coefficients according to the error signal, and updates the complex codeword offset table according to the offsets.

6. The digital-to-analog conversion method as described in claim 5 further comprises: an odd-mapping circuit included in an odd-correction circuit of the echo correction circuit receiving the odd portion minus the rounding error and mapping it according to an odd-numbered character deviation table in the codeword deviation table to generate an odd-numbered mapping signal; an odd-response circuit included in the odd-correction circuit receiving the odd-numbered mapping signal and processing it according to a set of odd-numbered response coefficients in the at least one set of response coefficients to generate an odd-numbered correction signal included in the at least one echo cancellation correction signal; an even-mapping circuit included in an even-correction circuit of the echo correction circuit receiving the even portion and mapping it according to an even-numbered character deviation table in the codeword deviation table to generate an even-numbered mapping signal; and an even-response circuit included in the even-correction circuit receiving the even-numbered mapping signal and processing it according to a set of even-numbered response coefficients in the at least one set of response coefficients to generate an even-numbered correction signal included in the at least one echo cancellation correction signal.

7. The digital-to-analog conversion method as described in claim 6 further comprises: receiving the input digital signal and filtering it according to the set of odd filter coefficients and the set of even filter coefficients by a residual echo cancellation circuit to produce a filtering result; receiving the input digital signal and processing it according to a set of residual echo response coefficients by a residual echo cancellation circuit included in the residual echo cancellation circuit to produce a residual echo cancellation signal; subtracting the residual echo cancellation signal and the error signal by a cancellation circuit included in the residual echo cancellation circuit to produce a final error signal; and having the correction parameter calculation circuit actually converge the at least one set of response coefficients according to the final error signal, and generating the offsets according to the final error signal and the path information associated with the echo correction circuit.

8. The digital-to-analog conversion method as described in claim 5 further comprises: an odd-number mapping circuit included in the echo correction circuit receiving the odd-number portion minus the rounding error and mapping it according to an odd-number character deviation table in the codeword deviation table to generate an odd-number mapping signal; an even-number mapping circuit included in the echo correction circuit receiving the even-number portion and mapping it according to an even-number character deviation table in the codeword deviation table to generate an even-number mapping signal; an odd-number filtering circuit included in the echo correction circuit filtering the even-number mapping signal according to a set of odd-number filtering coefficients to generate a filtered signal; a merging circuit included in the echo correction circuit subtracting the odd-number mapping signal and the filtered signal to generate a merged signal; and an odd-number response circuit included in the echo correction circuit receiving the merged signal and processing it according to a set of odd-number response coefficients to generate the at least one echo cancellation correction signal; A residual echo cancellation circuit includes a residual echo even-number mapping circuit that receives the input digital signal and maps it according to an even-number word deviation table to generate a residual echo even-number mapping signal; a residual echo filtering circuit includes the residual echo cancellation circuit that receives the input digital signal and the residual echo even-number mapping signal and filters them according to a set of odd-number filtering coefficients and a set of even-number filtering coefficients to generate a filtering result; a residual echo response circuit includes the residual echo cancellation circuit that receives the filtering result and processes it according to a set of odd-number response coefficients and a set of even-number response coefficients to generate a residual echo cancellation signal; a cancellation circuit includes the residual echo cancellation circuit that subtracts the residual echo cancellation signal and the echo signal from an error signal relative to one of the at least one echo cancellation correction signals to generate a final error signal; and a correction parameter calculation circuit that actually converges the at least one set of response coefficients according to the final error signal and generates the offsets according to the final error signal and the path information associated with the echo correction circuit.

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