Integrator and sigma-delta analog-digital converter

Abstract

The invention provides an integrator used in a sigma-delta analog-to-digital converter, which includes a sampling circuit and an integrating circuit. By designing a specific switch with a charge averaging function in the sampling circuit, the voltage level of terminals of the multiple sampling capacitors can be averaged to be close to a voltage level of the input signal to be sampled before a sampling stage, so that the input buffer only requires lower drive capability to charge or discharge the sampling capacitor. Thus the power consumption of the input buffer can be reduced.

Description

Technical Field

[0001] This invention relates to a trigonometric analog digital converter. Prior Technology

[0002] In trigonometric-integral analog-to-digital converters, an input buffer is typically used to receive an input signal to drive the integrator at the back end. However, when the integrator is a switched-capacitor integrator, the input buffer requires a strong driving capability, resulting in higher power consumption. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide an integrator that allows the input buffer to perform integrator operations with only a weak driving capability, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, an integrator is disclosed, comprising a sampling circuit and an integrating circuit. The sampling circuit samples a first signal to generate a sampled signal, and the integrating circuit integrates the sampled signal to generate a second signal. Furthermore, the sampling circuit includes a first circuit, a second circuit, and a first specific switch. The first circuit includes a first switch, a second switch, a third switch, a fourth switch, and a first sampling capacitor. The first switch is coupled between a first terminal and a common-mode voltage; the second switch is coupled between the first terminal and an output terminal of the sampling circuit; the third switch is coupled between an input terminal of the sampling circuit and a second terminal; the fourth switch is coupled between the second terminal and a first voltage; and the first sampling capacitor is coupled between the first terminal and the second terminal. The second circuit includes a first switch, a second switch, a third switch, a fourth switch, and a second sampling capacitor. The first switch is coupled between a first terminal of the second circuit and the common-mode voltage; the second switch is coupled between the first terminal and the output terminal of the sampling circuit; the third switch is coupled between the input terminal of the sampling circuit and a second terminal; the fourth switch is coupled between the second terminal and a second voltage; and the second sampling capacitor is coupled between the first terminal and the second terminal. A first specific switch is coupled between the second terminal of the first circuit and the second terminal of the second circuit.

[0005] In one embodiment of the present invention, a trigonometric integrator-analog converter is disclosed, comprising an input buffer, an adder, an integrator, a quantization circuit, and a digital-to-analog converter. The input buffer receives an input signal to generate a buffered input signal. The adder subtracts a feedback signal from the buffered input signal to generate a first signal. The integrator samples and integrates the first signal to generate a second signal. The quantization circuit generates an output signal based on the second signal. The digital-to-analog converter performs a digital-to-analog conversion on the output signal to generate the feedback signal. The integrator includes a sampling circuit and an integration circuit, wherein the sampling circuit samples the first signal to generate a sampled signal, and the integration circuit integrates the sampled signal to generate the second signal. Furthermore, the sampling circuit includes a first circuit, a second circuit, and a first specific switch. The first circuit includes a first switch, a second switch, a third switch, a fourth switch, and a first sampling capacitor. The first switch is coupled between a first terminal and a common-mode voltage. The second switch is coupled between the first terminal and an output terminal of a sampling circuit. The third switch is coupled between an input terminal of a sampling circuit and a second terminal. The fourth switch is coupled between the second terminal and a first voltage. The first sampling capacitor is coupled between the first terminal and the second terminal. The second circuit includes a first switch, a second switch, a third switch, a fourth switch, and a second sampling capacitor. The first switch is coupled between a first terminal and the common-mode voltage. The second switch is coupled between the first terminal and the output terminal of the sampling circuit. The third switch is coupled between the input terminal of the sampling circuit and a second terminal. The fourth switch is coupled between the second terminal and a second voltage. The second sampling capacitor is coupled between the first terminal and the second terminal. The first specific switch is coupled between the second terminal of the first circuit and the second terminal of the second circuit. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of a trigonometric analog-to-digital converter according to an embodiment of the present invention. Figure 2 is a schematic diagram of an integrator according to an embodiment of the present invention. Figure 3 is a schematic diagram of multiple clock signals according to an embodiment of the present invention. Implementation

[0007] Figure 1 is a schematic diagram of a recording path 100 according to an embodiment of the present invention, wherein the recording path 100 is used to process an input signal Vin to generate an output signal Dout. As shown in Figure 1, the recording path 100 includes an input buffer 110, a low-pass filter 102, and a sigma-delta analog-to-digital converter (ADC) 104. The sigma-delta ADC 104 includes an adder 120, two integrators 130 and 140, a delay circuit 150, an adder 160, a quantization circuit 170, and a digital-to-analog converter 180. The input buffer 110 includes an amplifier 112, an input resistor R1, and a feedback resistor R2 coupled between an input terminal and an output terminal of the amplifier 112. The low-pass filter 102 includes an output resistor R3 and an output capacitor C1. In this embodiment, the trigonometric integrator ADC 104 can be installed in any electronic device that requires analog-to-digital conversion, such as an electronic device with a microphone, and is used to convert analog sound signals from the microphone into digital audio signals.

[0008] In the operation of recording path 100, input buffer 110 receives input signal Vin to generate a buffered input signal Vin', and the buffered input signal Vin' is further processed by delay circuit 150 to generate a delayed input signal Vin''. Simultaneously, adder 120 subtracts a feedback signal VFB from the buffered input signal Vin' to generate a first signal V1. Integrator 130 samples and integrates the first signal V1 to generate a second signal V2, and integrator 140 samples and integrates the second signal V2 to generate a third signal V3. Then, adder 160 performs a weighted summation operation on the delayed input signal Vin'', the second signal V2, and the third signal V3 to generate a fourth signal V4. Quantization circuit 170 may include multiple comparators and an encoding circuit, which is used to convert the fourth signal V4 into an output signal Dout, where the output signal Dout is a multi-bit digital signal. In one embodiment, the quantization circuit 170 quantizes the fourth signal V4 into eight quantization levels: +7, +5, +3, +1, -1, -3, -5, and -7, and the resulting output signal Dout is a three-bit digital signal. For example, the quantization levels +7, +5, +3, +1, -1, -3, -5, and -7 correspond to the three bits D1, D2, and D3 of the output signal Dout, which can be (1, 1, 1), (1, 1, 0), (1, 0, 1), (1, 0, 0), (0, 1, 1), (0, 1, 0), (0, 0, 1), and (0, 0, 0). Next, the digital-to-analog converter 180 performs a digital-to-analog conversion operation on the output signal Dout to generate a feedback signal VFB.

[0009] Furthermore, the trigonometric integrator ADC 104 in Figure 1 is merely an illustrative example and not a limitation of the invention. For instance, the integrator 130 and the quantization circuit 170 can have different circuit designs, as long as the quantization circuit 170 can generate the output signal Dout based on the fourth signal V4.

[0010] It should be noted that since the operation of the trigonometric integrator ADC 104 is well known to those skilled in the art, and the focus of this invention is on the circuit design of the integrator 130, detailed descriptions of other components of the trigonometric integrator ADC 104 are not elaborated here.

[0011] Figure 2 is a schematic diagram of an integrator 130 according to an embodiment of the present invention. As shown in Figure 2, the integrator 130 includes a sampling circuit 202 and an integration circuit 204. The sampling circuit 202 includes a first circuit 210, a second circuit 220, a third circuit 230, a first specific switch SW1, and a second specific switch SW2. In this embodiment, the first circuit 210 includes a first switch SW11, a second switch SW12, a third switch SW13, a fourth switch SW14, and a first sampling capacitor Cs1. The first switch SW11 is coupled between a first terminal N11 and a common-mode voltage Vcm. The second switch SW12 is coupled between the first terminal N11 and a sampling circuit output terminal No1. The third switch SW13 is coupled between a sampling circuit input terminal Ni1 and a second terminal N12. The fourth switch SW14 is coupled between the second terminal N12 and a first voltage D1*Vr. The first sampling capacitor Cs1 is coupled between the first terminal N11 and the second terminal N12. The second circuit 220 includes a first switch SW21, a second switch SW22, a third switch SW23, a fourth switch SW24, and a second sampling capacitor Cs2. The first switch SW21 is coupled between a first terminal N21 and a common-mode voltage Vcm. The second switch SW22 is coupled between the first terminal N21 and the sampling circuit output terminal No1. The third switch SW23 is coupled between the sampling circuit input terminal Ni1 and a second terminal N22. The fourth switch SW24 is coupled between the second terminal N22 and a second voltage D2*Vr. The second sampling capacitor Cs2 is coupled between the first terminal N21 and the second terminal N22. The third circuit 220 includes a first switch SW31, a second switch SW32, a third switch SW33, a fourth switch SW34, and a third sampling capacitor Cs3. The first switch SW31 is coupled between a first terminal N31 and a common-mode voltage Vcm; the second switch SW32 is coupled between the first terminal N31 and the sampling circuit output terminal No1; the third switch SW33 is coupled between the sampling circuit input terminal Ni1 and a second terminal N32; the fourth switch SW34 is coupled between the second terminal N32 and a third voltage D3*Vr; and the third sampling capacitor Cs3 is coupled between the first terminal N31 and the second terminal N32. In Figure 2, "Vr" can be a reference voltage with a fixed voltage level, while D1, D2, and D3 are the three bits of the output signal Dout.

[0012] The integrating circuit 204 includes an amplifier 240 and an integrating capacitor Cint, wherein the integrating capacitor Cint is coupled between the negative input terminal and the output terminal of the amplifier 240, and the positive input terminal of the amplifier 240 is coupled to the common-mode voltage Vcm.

[0013] It should be noted that the number of sampling capacitors and corresponding switches shown in Figure 2 is merely an illustrative example and not a limitation of the present invention. In other embodiments, if the output signal Dout has only two bits, the third circuit 230 can be removed from the sampling circuit 202; while if the output signal Dout has four bits, the sampling circuit 202 can additionally include a fourth circuit, wherein the architecture of the fourth circuit is the same as that of the first circuit 210, the second circuit 220, and the third circuit 230.

[0014] In this embodiment, referring to Figure 3, the first switches SW11, SW21, and SW31 in the first circuit 210, the second circuit 220, and the third circuit 230 are controlled by a first clock signal CK1, and the second switches SW12, SW22, and SW32 in the first circuit 210, the second circuit 220, and the third circuit 230 are controlled by a second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 will not have high voltage levels at the same time, that is, the first switches SW11 / SW21 / SW31 and the second switches SW12 / SW22 / SW32 will not be turned on at the same time. Furthermore, the third switches SW13, SW23, and SW33 in the first circuit 210, the second circuit 220, and the third circuit 230 are controlled by a third clock signal CK1d. The third clock signal CK1d is generated based on the first clock signal CK1. For example, the third clock signal CK1d is generated from the first clock signal CK1 through a delay circuit, meaning the phase of the third clock signal CK1d lags behind the phase of the first clock signal CK1. The fourth switches SW14, SW24, and SW34 in the first circuit 210, the second circuit 220, and the third circuit 230 are controlled by a fourth clock signal CK2d. The fourth clock signal CK2d is generated based on the second clock signal CK2. For example, the fourth clock signal CK2d is generated from the second clock signal CK2 through a delay circuit, meaning the phase of the fourth clock signal CK2d lags behind the phase of the second clock signal CK2. Furthermore, in one embodiment, the third clock signal CK1d and the second clock signal CK2 will not simultaneously have a high voltage level, and the fourth clock signal CK2d and the first clock signal CK1 will not simultaneously have a high voltage level.

[0015] In other embodiments, the third switches SW13, SW23, and SW33 in the first circuit 210, the second circuit 220, and the third circuit 230 can also be controlled by the first clock signal CK1, and / or the fourth switches SW14, SW24, and SW34 in the first circuit 210, the second circuit 220, and the third circuit 230 can also be controlled by the second clock signal CK2. These design variations should fall within the scope of this invention.

[0016] It should be noted that the timing and duty cycles of the multiple clock signals illustrated in Figure 3 are merely illustrative examples and not limitations of the invention. For instance, as long as the first clock signal CK1 and the second clock signal CK2 do not simultaneously turn on their corresponding switches (e.g., the first clock signal CK1 and the second clock signal CK2 do not simultaneously have a high level), the phase and duty cycle of the first clock signal CK1 and the second clock signal CK2 can vary according to the designer's considerations. Similarly, as long as the third clock signal CK1d and the fourth clock signal CK2d do not simultaneously turn on their corresponding switches, the phase and duty cycle of the third clock signal CK1d and the fourth clock signal CK2d can vary according to the designer's considerations.

[0017] In the operation of integrator 130, firstly, integrator 130 operates in a sampling phase, at which time the first clock signal CK1 and the third clock signal CK1d can have high voltage levels to turn on the first switches SW11, SW21, SW31 (corresponding to clock signal CK1) and the third switches SW13, SW23, SW33 (corresponding to clock signal CK1d) in the first circuit 210, the second circuit 220, and the third circuit 230, respectively; and the second clock signal CK2 and the fourth clock signal CK2d can have low voltage levels to turn on the second switches SW12, SW22, SW32 (corresponding to clock signal CK2) and the fourth switches SW14, SW24, SW34 (corresponding to clock signal CK2d) in the first circuit 210, the second circuit 220, and the third circuit 230, respectively, in a non-conducting state. During the sampling phase, the voltage difference between the first signal V1 and the common-mode voltage Vcm is stored in the first sampling capacitor Cs1, the second sampling capacitor Cs2, and the third sampling capacitor Cs3.

[0018] Furthermore, before the sampling phase begins, that is, before the third switches SW13, SW23, and SW33 are turned on, the first specific switch SW1 and the second specific switch SW2 will be turned on by the first clock signal CK1, so that the second terminals N12, N22, and N32 in the first circuit 210, the second circuit 220, and the third circuit 230 are connected to each other to average their charges, that is, so that the second terminals N12, N22, and N32 have the same or similar voltage levels.

[0019] Following the sampling phase, integrator 130 operates in an integration phase. At this time, the first clock signal CK1 and the third clock signal CK1d can have low voltage levels, so that the first switches SW11, SW21, SW31 and the third switches SW13, SW23, SW33 in the first circuit 210, the second circuit 220 and the third circuit 230 are in an off state; and the second clock signal CK2 and the fourth clock signal CK2d can have high voltage levels, so that the second switches SW12, SW22, SW32 and the fourth switches SW14, SW24, SW34 in the first circuit 210, the second circuit 220 and the third circuit 230 are respectively turned on. During the integration phase, the first sampling capacitor Cs1, the second sampling capacitor Cs2, and the third sampling capacitor Cs3 convert the difference between the stored input signal Vin' and the feedback signal VFB into a sampled signal Vs. The integrating circuit 204 integrates the sampled signal Vs to generate the second signal V2. As described above, the sampling circuit 202 samples the first signal V1 to generate the sampled signal Vs.

[0020] In the embodiment shown in Figure 2, before the sampling phase begins, the first specific switch SW1 and the second specific switch SW2 are turned on by the first clock signal CK1, allowing the second terminals N12, N22, and N32 to have the same or similar voltage levels. This allows the input buffer 110 to quickly transmit the first signal V1 to the first sampling capacitor Cs1, the second sampling capacitor Cs2, and the third sampling capacitor Cs3 without requiring strong driving capability. For example, assuming that before the sampling phase begins, the three bits D1, D2, and D3 of the output signal Dout are (1, 0, 1) respectively, and the voltage levels of the second terminals N12, N22, and N32 in Figure 2 are equal to (Vr, 0, Vr), then before the sampling phase begins, by turning on the first specific switch SW1 and the second specific switch SW2, the voltage levels of the second terminals N12, N22, and N32 will be equal to (2 / 3)*Vr. Furthermore, since the trigonometric integrator ADC 104 uses oversampling technology, the voltage level of the buffered input signal Vin' is usually very close to (2 / 3)*Vr. Therefore, the input buffer 110 only needs a lower drive capability to charge and discharge the voltage levels of the second terminals N12, N22, and N32 to the voltage level of the buffered input signal Vin', thus reducing the power consumption of the input buffer 110.

[0021] In the prior art, since the first specific switch SW1 and the second specific switch SW2 do not have charge averaging function, during the sampling stage, the second terminal N12 of the first circuit 210 needs to be charged and discharged from Vr to the voltage level of the first signal V1, the second terminal N22 of the second circuit 220 needs to be charged and discharged from 0V to the voltage level of the first signal V1, and the second terminal N32 of the third circuit 230 needs to be charged and discharged from Vr to the voltage level of the first signal V1. Therefore, the input buffer 110 requires a strong driving capability and has high power consumption.

[0022] In summary, in the integrator of this invention, by designing a first specific switch SW1 and a second specific switch SW2 with charge averaging function to be turned on before the sampling phase begins, and making the second terminal of the sampling capacitor close to the first signal to be sampled, the input buffer can charge and discharge the sampling capacitor to the voltage level of the first signal with only lower drive capability, thereby reducing the power consumption of the input buffer. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the scope of the claims of the present invention shall be covered by the present invention.

[0023] 100: Recording Path 102: Low-pass filter 104: Trigonometric Integral ADC 110: Input buffer 112: Amplifier 120: Adder 130, 140: Integrator 150: Delay circuit 160: Adder 170: Quantization Circuit 180: Digital-to-Analog Converter 202: Sampling Circuit 204: Integrating Circuit 210: First Circuit 220: Second Circuit 230: Third Circuit 240: Amplifier C1: Output capacitor Cint: Integrating capacitor Cs1: First sampling capacitor Cs2: Second sampling capacitor Cs3: Third sampling capacitor D1, D2, D3: Bits CK1: First clock signal CK2: Second Clock Signal CK1d: Third Clock Signal CK2d: Fourth Clock Signal Dout: Output signal N11, N21, N31: First endpoint N12, N22, N32: Second endpoints Ni1: Input terminal of the sampling circuit No.1: Sampling circuit output terminal R1: Input resistor R2: Feedback resistor R3: Output resistor SW1: First specific switch SW2: Second Specific Switch SW11, SW21, SW31: First switches SW12, SW22, SW32: Second switches SW13, SW23, SW33: Third switches SW14, SW24, SW34: Fourth switches V1: First Signal V2: Second Signal V3: Third Signal V4: Fourth Signal Vcm: Common-mode voltage VFB: Feedback Signal Vin: Input signal Vin': Input signal after buffering Vin": Input signal after delay Vr: Reference voltage Vs: Sampling signal

Claims

1. An integrator comprising: a sampling circuit for sampling a first signal to generate a sampled signal, the sampling circuit comprising: a first circuit including a first switch, a second switch, a third switch, a fourth switch and a first sampling capacitor, wherein the first switch is coupled between a first terminal and a common-mode voltage, the second switch is coupled between the first terminal and an output terminal of the sampling circuit, the third switch is coupled between an input terminal of the sampling circuit and a second terminal, the fourth switch is coupled between the second terminal and the first voltage, and the first sampling capacitor is coupled between the first terminal and the second terminal; A second circuit includes a first switch, a second switch, a third switch, a fourth switch, and a second sampling capacitor, wherein the first switch is coupled between a first terminal of the second circuit and the common-mode voltage, the second switch is coupled between the first terminal and the output terminal of the sampling circuit, the third switch is coupled between the input terminal of the sampling circuit and a second terminal of the second circuit, the fourth switch is coupled between the second terminal and a second voltage, and the second sampling capacitor is coupled between the first terminal and the second terminal; a first specific switch is coupled between the second terminal of the first circuit and the second terminal of the second circuit; and an integrating circuit is coupled to the sampling circuit for integrating the sampled signal to generate a second signal.

2. The integrator as described in claim 1, wherein the first switch of the first circuit and the first switch of the second circuit are controlled by a first clock signal, the second switch of the first circuit and the second switch of the second circuit are controlled by a second clock signal, the third switch of the first circuit and the third switch of the second circuit are controlled by a third clock signal, and the fourth switch of the first circuit and the fourth switch of the second circuit are controlled by a fourth clock signal; and the first clock signal and the second clock signal do not simultaneously turn on the corresponding switches.

3. The integrator as described in claim 2, wherein the third clock signal is generated based on the first clock signal, the fourth clock signal is generated based on the second clock signal, and the third clock signal and the fourth clock signal do not simultaneously turn on the corresponding switches.

4. The integrator as described in claim 3, wherein the phase of the third clock signal lags behind the phase of the first clock signal, and the phase of the fourth clock signal lags behind the phase of the second clock signal.

5. The integrator as described in claim 4, wherein the first specific switch is controlled by the first clock signal.

6. The integrator as claimed in claim 1, wherein before the integrator operates in a sampling phase, the first specific switch is turned on such that the second terminal of the first circuit is connected to the second terminal of the second circuit; when the integrator operates in the sampling phase, the first switch and the third switch of the first circuit, and the first switch and the third switch of the second circuit are turned on, and the second switch and the fourth switch of the first circuit, and the second switch and the fourth switch of the second circuit are not turned on; and when the integrator operates in an integration phase, the first switch and the third switch of the first circuit, and the first switch and the third switch of the second circuit are not turned on, and the second switch and the fourth switch of the first circuit, and the second switch and the fourth switch of the second circuit are turned on.

7. The integrator as described in claim 1, further comprising: a third circuit including a first switch, a second switch, a third switch, a fourth switch, and a third sampling capacitor, wherein the first switch is coupled between a first terminal of the third circuit and the common-mode voltage, the second switch is coupled between the first terminal and the output terminal of the sampling circuit, the third switch is coupled between the input terminal of the sampling circuit and a second terminal of the third circuit, the fourth switch is coupled between the second terminal and the second voltage, and the third sampling capacitor is coupled between the first terminal and the second terminal; and a second specific switch coupled between the second terminal of the second circuit and the second terminal of the third circuit.

8. As described in claim 7, the integrator is characterized in that, prior to operation of the integrator in a sampling phase, the first specific switch and the second specific switch are turned on such that the second terminal of the first circuit, the second terminal of the second circuit, and the second terminal of the third circuit are connected to each other; when the integrator operates in the sampling phase, the first switch and the third switch of the first circuit, the first switch and the third switch of the second circuit, and the first switch and the third switch of the third circuit are turned on, and the second switch and the fourth switch of the first circuit, the second switch and the fourth switch of the second circuit, and the second switch and the fourth switch of the third circuit are not turned on; and when the integrator operates in an integration phase, the first switch and the third switch of the first circuit, the first switch and the third switch of the second circuit, and the first switch and the third switch of the third circuit are not turned on, and the second switch and the fourth switch of the first circuit, the second switch and the fourth switch of the second circuit, and the second switch and the fourth switch of the third circuit are turned on.

9. A trigonometric integrator-analog converter, comprising: an input buffer for receiving an input signal to generate a buffered input signal; and an adder for subtracting a feedback signal from the buffered input signal to generate a first signal; An integrator is used to sample and integrate the first signal to generate a second signal; a quantization circuit is used to generate an output signal based on the second signal; The integrator includes a digital-to-analog converter for performing a digital-to-analog conversion operation on the output signal to generate the feedback signal; wherein the integrator includes: a sampling circuit for sampling the first signal to generate a sampled signal, and the sampling circuit includes: a first circuit including a first switch, a second switch, a third switch, a fourth switch and a first sampling capacitor, wherein the first switch is coupled between a first terminal and a common-mode voltage, the second switch is coupled between the first terminal and an output terminal of the sampling circuit, the third switch is coupled between an input terminal of the sampling circuit and a second terminal, the fourth switch is coupled between the second terminal and a first voltage, and the first sampling capacitor is coupled between the first terminal and the second terminal; A second circuit includes a first switch, a second switch, a third switch, a fourth switch, and a second sampling capacitor, wherein the first switch is coupled between a first terminal of the second circuit and the common-mode voltage, the second switch is coupled between the first terminal and the output terminal of the sampling circuit, the third switch is coupled between the input terminal of the sampling circuit and a second terminal, the fourth switch is coupled between the second terminal and a second voltage, and the second sampling capacitor is coupled between the first terminal and the second terminal; a first specific switch is coupled between the second terminal of the first circuit and the second terminal of the second circuit; and an integrating circuit is coupled to the sampling circuit for integrating the sampled signal to generate the second signal.

10. A trigonometric analog-to-digital converter as claimed in claim 9, wherein before the integrator operates in a sampling phase, the first specific switch is turned on such that the second terminal of the first circuit is connected to the second terminal of the second circuit; when the integrator operates in the sampling phase, the first switch and the third switch of the first circuit, and the first switch and the third switch of the second circuit are turned on, and the second switch and the fourth switch of the first circuit, and the second switch and the fourth switch of the second circuit are not turned on; and when the integrator operates in an integration phase, the first switch and the third switch of the first circuit, and the first switch and the third switch of the second circuit are not turned on, and the second switch and the fourth switch of the first circuit, and the second switch and the fourth switch of the second circuit are turned on.

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