Clock and data recovery circuit and clock and data recovery method thereof

Abstract

A comparator of the N comparators compares a phase of the data signal and a phase of a selected clock of the N clocks. The data sorter is coupled to the phase detector to determine a data order of the sampled values and disable a subset of the N comparators according to the data order and a promised transition edge

Description

Technical Field

[0001] This invention relates to communication systems, and more particularly to clock and data recovery circuits for reducing power consumption, and clock and data recovery methods thereof. Prior Technology

[0002] Clock and Data Recovery (CDR) is a critical procedure in digital data communication, where a separate clock signal is transmitted when no data signal is being transmitted. CDR comprises clock recovery and data recovery. The clock recovery process generates a recovered clock by aligning the phase of the internal clock to the transition point in the input data signal, thus synchronizing the internal clock with the input data signal. The data recovery process uses the recovered clock to re-timing the input data signal to ensure accurate sampling. Therefore, CDR achieves accurate clock synchronization in digital data communication systems, ensuring reliable data transmission.

[0003] Traditional CDR circuits align the internal clock at all possible data transition points to prevent internal clock lock-up, which would result in significant power loss. Summary of the Invention

[0004] This invention provides a clock and data recovery circuit, including a phase detector and a data sequencer. The phase detector includes N samplers and N comparators. The N samplers sample the data signal using N clocks to generate a plurality of sample values, where N is an integer greater than 1. The comparators among the N comparators compare the phase of the data signal with the phase of a selected clock among the N clocks. The data sequencer is coupled to the phase detector, determines the data order of the plurality of sample values, and selectively disables the N comparators based on the data order and to ensure that the transition edge is disabled.

[0005] This invention provides a clock and data recovery method, comprising sampling a data signal using N samplers and N clocks to generate a plurality of sampled values, comparing the phase of the data signal with the phase of a selected clock among the N comparators, determining the data order of the plurality of sampled values ​​using a data sorter, and selectively disabling the N comparators based on the data order and ensuring that the transition edge is disabled. Simple Explanation of the Diagram

[0006] Figure 1 shows a clock and data recovery circuit in an embodiment of the present invention. Figure 2 is a flowchart of a clock and data recovery method for the clock and data recovery circuit in Figure 1. Figure 3 is a circuit diagram of the phase detector in Figure 1. Figure 4 is a schematic diagram of a binary (bang-bang) clock and data recovery method for the clock and data recovery circuit in Figure 1. Figure 5 is a schematic diagram of another binary clock and data recovery method of the clock and data recovery circuit in Figure 1. Figure 6 shows another clock and data recovery circuit in an embodiment of the present invention. Figure 7 is a circuit diagram of the clock and data recovery circuit in Figure 6. Implementation

[0007] Figure 1 illustrates a clock and data recovery (CDR) circuit 100 used in a 1 / 3 data rate bang-bang system according to an embodiment of the present invention. A 1 / 3 data rate refers to sampling the data signal using three clocks with different phases. The CDR circuit 100 samples the data signal Sin using clocks CK0, CK120, and CK240 to generate a sequence signal PB, wherein the phases of the three clocks CK0, CK120, and CK240 differ by 120 degrees from each other. The CDR circuit 100 adjusts the phases of clocks CK0, CK120, and CK240 to align them with the transition points of the data signal Sin to achieve clock recovery, and uses the phase-aligned clocks CK0, CK120, and CK240 to sample the data signal Sin to achieve data recovery. The data signal Sin can be a video signal, including possible transition points and guaranteed transition points. A possible transition point refers to a point in time in the data signal Sin where a transition (from b'0 to b'1 or from b'1 to b'0) may occur, but the transition is not guaranteed to happen. A guaranteed transition point refers to a point in time where a transition is certain to occur based on the encoding method or communication protocol. The CDR circuit 100 can turn off (or disable) the circuit elements related to possible transition points, while turning on (or enabling) the circuit elements related to guaranteed transition points to achieve reliable clock phase alignment and reduce power consumption.

[0008] The data signal Sin can be transmitted differentially or single-ended from a hard drive, camera, streaming service, or other video source. The sequence signal PB can contain sampled values ​​of video data packets, each containing a certain number of sampled values, each representing a specific pixel in a video frame. The sequence signal PB can be transmitted to a display device, such as a liquid crystal display (LCD), for visual presentation.

[0009] The CDR circuit 100 may include a phase detector (PD) 102, a sorting circuit 104, N clocks 106, and a phase-locked loop circuit 108. In this embodiment, N=6, and the N clocks 106 include clocks CK0, CK60, CK120, CK180, CK240, and CK300, with any two adjacent clocks having a phase difference of 60 degrees. For a binary architecture, the CDR circuit 100 can utilize the data conversion in the sampled data signals Sin from clocks CK60, CK180, and CK300, and compare the sampled values ​​generated by clocks CK0, CK120, and CK240 with those generated by clocks CK60, CK180, and CK300 to determine the lead / lag information of all clocks 106. Subsequently, the phase-locked loop circuit 108 can adjust the phase of all clocks 106 according to the lead / lag information of each clock. Specifically, clocks CK0, CK60, CK120, CK180, CK240 and CK300 can adjust their phase based on lead / lag information while maintaining a 60-degree phase difference between adjacent clocks.

[0010] Phase detector 102 may include sampler 103 and comparator 105. Sampler 103 samples data bit values ​​in data signal Sin and the conversion value between two consecutive data bits. The inputs of phase detector 102 are data signal Sin and six clock cycles (CK0, CK60, CK120, CK180, CK240, and CK300). Phase detector 102 samples data signal Sin using clock cycle CK0 and outputs sampled values ​​Di, Di+3, and Di+6 on data line 111; samples using clock cycle CK120 and outputs sampled values ​​Di+1, Di+4, and Di+7 on data line 112; and samples using clock cycle CK240 and outputs sampled values ​​Di+2, Di+5, and Di+8 on data line 113. Sequencing circuit 104 can be coupled to phase detector 102 via data lines 111, 112, and 113. Phase detector 102 can transmit sampled values ​​to sorting circuit 104 via data lines 111, 112, and 113. In addition, each comparator 105 can compare the phase of data signal Sin with the phase of the corresponding clock in N clocks 106 to generate lead / lag information of the corresponding clock, and transmit the lead / lag information of the corresponding clock to phase-locked loop circuit 108.

[0011] The sorting circuit 104 can organize the sampled values ​​of the data signal Sin into a specific sequence Di, Di+1, Di+2, Di+3, Di+4, Di+5, Di+6, Di+7, and Di+8 according to a known pattern. This known pattern can be a preamble sequence of a video frame, such as b'11110000. If the sampled values ​​Di to Di+8 are b'011110000, the sorting circuit 104 can identify the most significant bit (MSB) as sampled value Di+1 and the least significant bit (LSB) as sampled value Di+8, thereby allowing the sorting circuit 104 to accurately interpret and segment all subsequent sampled values, ensuring that the video data is correctly processed and decoded. MSB and LSB can define the data order of sampled values ​​Di to Di+8. The sorting circuit 104 can selectively disable the N comparator and / or the N sampler according to the data order and the promised transition edge. In this embodiment, the sorting circuit 104 can transmit control signals Sc1, Sc2, and Sc3 to the phase detector 102 via control lines 121, 122, and 123 to selectively disable the N comparator and / or sampler. The phase-locked loop circuit 108 can adjust the phase and frequency of clocks CK0, CK60, CK120, CK180, CK240, and CK300 based on the lead / lag information provided by the phase detector 102.

[0012] Upon power-on, the data signal Sin transmits a training pattern for clock training, serving as a reference for the loop from phase detector 102 to sequencing circuit 104, to achieve synchronization and locking of clocks CK0, CK60, CK120, CK180, CK240, and CK300. Once the clocks are successfully locked, sequencing circuit 104 can further perform power management on CDR circuit 100 via control signals Sc1, Sc2, and Sc3 transmitted through control lines 121, 122, and 123, and selectively enable or disable sampler 103 and comparator 105 based on data order and guaranteed transition edges. In this embodiment, at least one guaranteed transition edge exists in the video data packet. A guaranteed transition edge refers to a specific point in time when a state change (from b'0 to b'1 or from b'1 to b'0) is expected to occur, depending on the encoding scheme or protocol used. By selectively enabling samplers 103 and comparators 105 that are associated with the guaranteed transition edge, the CDR circuit 100 can accurately align the phases of clock signals CK0, CK60, CK120, CK180, CK240, and CK300 with the phase of the data signal Sin, thereby improving the reliability of clock and data recovery. Furthermore, by selectively disabling samplers 103 and comparators 105 that are associated with potential transition points (or not associated with the guaranteed transition edge), the overall power consumption of the CDR circuit 100 is reduced, which is beneficial for low-power applications such as mobile devices or large-scale data centers.

[0013] The phase-locked loop circuit 108 may include a charge pump, a filter, and a voltage control oscillator (VCO) to control the phase and frequency of clocks CK0, CK60, CK120, CK180, CK240, and CK300 based on lead / lag information.

[0014] The transition edge is guaranteed to appear in the preamble sequence, the delimiter field of the data packet, or the redundant field of the data packet. Using guaranteed transition edges to generate lead / lag information can improve reliability and reduce power consumption. In this embodiment, the data transfer rate of the CDR circuit 100 is not limited to 1 / 3, and the number of data packets is not limited to 9. The number of control lines and the number of data lines are not limited to 3.

[0015] Figure 2 is a flowchart of method 200 for CDR circuit 100. Any reasonable changes or adjustments to the steps are within the scope of this disclosure. Method 200 includes the following steps:

[0016] Step S202: Sample the data signal using N samplers and N clock cycles to generate sampled values;

[0017] Step S204: Compare the phase of the data signal with the phase of the selected clock from the N clocks using the comparators among the N comparators;

[0018] Step S206: Determine the data order of the sampled values ​​using a data sorter; and

[0019] Step S208: Selectively disable N comparators by means of a data sorter based on data order and to ensure transition edges.

[0020] The method 200 is explained below in conjunction with the CDR circuit 100. In step S202, the data signal Sin is sampled by N samplers 103 using N clocks 106 to generate sampled values. In step S204, the phase of the data signal is compared with the phase of a selected clock among the N clocks 106 by one of the N comparators 105. In step S206, the data order of the sampled values ​​is determined by the sorting circuit 104. In step S208, the N comparators 105 are selectively deactivated by the sorting circuit 104 according to the data order and to ensure the transition edge.

[0021] Figure 3 is a circuit diagram of phase detector 102. Phase detector 102 may include N samplers, N comparators, and N storage devices. In Figure 3, N is 6. Phase detector 102 includes samplers 301 to 306, comparators 311 to 316, and storage devices 321 to 326. Samplers 301 to 306 may be implemented using flip-flops, comparators 311 to 316 may be implemented using exclusive OR (XOR) gates, and storage devices 321 to 326 may be implemented using flip-flops. The N samplers may include conversion samplers and data samplers. The number of conversion samplers and data samplers may be equal or different. In some embodiments, the number of conversion samplers may be N / 2, and the number of data samplers may be N / 2. In this embodiment, the number of conversion samplers is 3, and the number of data samplers is 3. The data sampler samples the data bits in the data signal Sin. Samplers 301, 303, and 305 can be used as data samplers. The conversion sampler samples the value between two adjacent data bits in the data signal Sin. Samplers 302, 304, and 306 can be used as conversion samplers.

[0022] Sampler 301 may include a data terminal D for receiving the data signal Sin; an input clock terminal CK for receiving the clock CK0; an output terminal Q for generating the sampled value D0; and an output clock terminal CKO for outputting the clock CK00. The clock CK00 may be the same as the clock CK0. Comparator 311 may include a first input terminal coupled to the output terminal Q of sampler 301 for receiving the sampled value D0; a second input terminal for receiving the sampled value D60; and an output terminal for outputting the comparison result UP0. Storage device 321 may include a data terminal D coupled to the output terminal of comparator 311 for receiving the comparison result UP0; an input clock terminal CK coupled to the output clock terminal CKO of sampler 301 for receiving the clock CK00; and an output terminal Q for generating phase information PD_UP0. The phase information PD_UP0 may be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0023] Sampler 302 may include a data terminal D for receiving the data signal Sin; an input clock terminal CK for receiving the clock CK60; an output terminal Q for generating the sampled value D60; and an output clock terminal CKO for outputting the clock CK600. The clock CK600 may be the same as the clock CK60. Comparator 312 may include a first input terminal coupled to the output terminal Q of sampler 302 for receiving the sampled value D60; a second input terminal for receiving the sampled value D120; and an output terminal for outputting the comparison result DN0. Storage device 322 may include a data terminal D coupled to the output terminal of comparator 312 for receiving the comparison result DN0; an input clock terminal CK coupled to the output clock terminal CKO of sampler 302 for receiving the clock CK600; and an output terminal Q for generating phase information PD_DN0. Phase information PD_DN0 can be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0024] Sampler 303 may include a data terminal D for receiving data signal Sin; an input clock terminal CK for receiving clock CK120; an output terminal Q for generating sampled value D120; and an output clock terminal CKO for outputting clock CK1200. Clock CK1200 may be the same as clock CK120. Comparator 313 may include a first input terminal coupled to the output terminal Q of sampler 303 for receiving sampled value D120; a second input terminal for receiving sampled value D180; and an output terminal for outputting comparison result UP1. Storage device 323 may include a data terminal D coupled to the output terminal of comparator 313 for receiving comparison result UP1; an input clock terminal CK coupled to the output clock terminal CKO of sampler 303 for receiving clock CK1200; and an output terminal Q for generating phase information PD_UP1. Phase information PD_UP1 can be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0025] Sampler 304 may include a data terminal D for receiving the data signal Sin; an input clock terminal CK for receiving the clock CK180; an output terminal Q for generating the sampled value D180; and an output clock terminal CKO for outputting the clock CK1800. The clock CK1800 may be the same as the clock CK180. Comparator 314 may include a first input terminal coupled to the output terminal Q of sampler 304 for receiving the sampled value D180; a second input terminal for receiving the sampled value D240; and an output terminal for outputting the comparison result DN1. Storage device 324 may include a data terminal D coupled to the output terminal of comparator 314 for receiving the comparison result DN1; an input clock terminal CK coupled to the output clock terminal CKO of sampler 304 for receiving the clock CK1800; and an output terminal Q for generating phase information PD_DN1. Phase information PD_DN1 can be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0026] Sampler 305 may include a data terminal D for receiving the data signal Sin; an input clock terminal CK for receiving the clock CK240; an output terminal Q for generating the sampled value D240; and an output clock terminal CKO for outputting the clock CK2400. The clock CK2400 may be the same as the clock CK240. Comparator 315 may include a first input terminal coupled to the output terminal Q of sampler 305 for receiving the sampled value D240; a second input terminal for receiving the sampled value D300; and an output terminal for outputting the comparison result UP2. Storage device 325 may include a data terminal D coupled to the output terminal of comparator 315 for receiving the comparison result UP2; an input clock terminal CK coupled to the output clock terminal CKO of sampler 305 for receiving the clock CK2400; and an output terminal Q for generating phase information PD_UP2. Phase information PD_UP2 can be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0027] Sampler 306 may include a data terminal D for receiving the data signal Sin; an input clock terminal CK for receiving the clock CK300; an output terminal Q for generating the sampled value D300; and an output clock terminal CKO for outputting the clock CK3000. The clock CK3000 may be the same as the clock CK300. Comparator 316 may include a first input terminal coupled to the output terminal Q of sampler 306 for receiving the sampled value D300; a second input terminal for receiving the sampled value D0; and an output terminal for outputting the comparison result DN2. Storage device 326 may include a data terminal D coupled to the output terminal of comparator 316 for receiving the comparison result DN2; an input clock terminal CK coupled to the output clock terminal CKO of sampler 306 for receiving the clock CK3000; and an output terminal Q for generating phase information PD_DN2. Phase information PD_DN2 can be sent to phase-locked loop circuit 108 to determine lead / lag information.

[0028] In one embodiment, the sorting circuit 104 can determine that the MSB of the video data packet is generated by clock CK0, and that there is a guaranteed transition edge to be sampled by clock CK60. That is, sampler 302 is a transition sampler that samples the guaranteed transition edge. The guaranteed transition edge can occur in a preamble sequence (e.g., a preamble sequence of a video frame), a delimiter field of a data packet (e.g., a delimiter field of a video packet), or a redundant field of a data packet (e.g., an error correction code (ECC)). The following describes how the phase detector 102 is controlled in conjunction with Figures 1 and 3. Control signal Sc1 can be used to enable or disable sampler 302, comparators 311, 312, and storage devices 321, 322. Control signal Sc2 can be used to enable or disable sampler 304, comparators 313, 314, and storage devices 323, 324. Control signal Sc3 can be used to enable or disable sampler 306, comparators 315, 316, and storage devices 325, 326. In some embodiments, sorting circuit 104 can selectively disable samplers 302, 304, 306, comparators 311 to 316, and storage devices 321 to 326 based on data order and guaranteed transition edge. The disabled comparators may be independent of the switching sampler 302 that guarantees the transition edge. That is, the disabled comparators 311 to 316 are comparators not coupled to the switching sampler 302. In this embodiment, comparators 313 to 316 can be disabled.

[0029] When clock CK60 samples the guaranteed transition edge, circuitry in phase detector 102 unrelated to the guaranteed transition edge can be turned off. Therefore, control signal Sc1 can be used to activate sampler 302, comparators 311 and 312, and storage devices 321 and 322. Control signal Sc2 can be used to deactivate sampler 304, comparators 313 and 314, and storage devices 323 and 324. Control signal Sc3 can be used to deactivate sampler 306, comparators 315 and 316, and storage devices 325 and 326. In other words, sampler 302, which samples for the guaranteed transition edge, is activated, while samplers 304 and 306, which do not sample for this transition edge, are deactivated.

[0030] Sampler 301 samples the data signal Sin using clock CK0, generating a sampled value D0 representing the data. Sampler 303 samples the data signal Sin using clock CK120, generating a sampled value D120 representing the data. Sampler 305 samples the data signal Sin using clock CK240, generating a sampled value D240 representing the data. Sampler 302 samples the data signal Sin using clock CK60, generating a sampled value D60 representing the guaranteed transition edge. Since sampled value D60 represents the guaranteed transition edge, the states of sampled values ​​D0 and D120 are reversed. For simplicity, the operation of comparators 311 and 312 will be discussed below in the scenario where sampled value D0 is b'0 and sampled value D120 is b'1.

[0031] Comparator 311 compares the sampled value D0 and sampled value D60 at the guaranteed transition edge, generating a comparison result UP0. If sampled value D60 is b'0, then since sampled value D0 is b'0, comparison result UP0 will be b'0, indicating that clock CK60 leads the guaranteed transition edge. If sampled value D60 is b'1, then since sampled value D0 is b'0, comparison result UP0 will be b'1, indicating that clock CK60 lags the guaranteed transition edge. Comparison result UP0 is then stored in storage device 321, and phase information PD_UP0 is output.

[0032] Comparator 312 compares the sampled value D60 and the sampled value D120 at the guaranteed transition edge, generating a comparison result DN0. If the sampled value D60 is b'0, then since the sampled value D120 is b'1, the comparison result DN0 will be b'1, indicating that the clock CK60 leads the guaranteed transition edge. If the sampled value D60 is b'1, then since the sampled value D120 is b'1, the comparison result DN0 will be b'0, indicating that the clock CK60 lags the guaranteed transition edge. The comparison result DN0 is then stored in storage device 322, and phase information PD_DN0 is output.

[0033] The phase-locked loop circuit 108 can determine whether the information is leading or lagging based on the phase information PD_UP0 and PD_DN0. If the phase information PD_UP0 is b'1 and the phase information PD_DN0 is b'0, the phase-locked loop circuit 108 can determine that the clock CK60 lags behind the guaranteed transition edge and advances the phase of all clocks 106. Conversely, if the phase information PD_UP0 is b'0 and the phase information PD_DN0 is b'1, the phase-locked loop circuit 108 can determine that the clock CK60 leads the guaranteed transition edge and delays the phase of all clocks 106. If both the phase information PD_UP0 and PD_DN0 are b'0, the phase-locked loop circuit 108 can determine that there is no data transition in the data signal Sin and keep the phase of all clocks 106 unchanged.

[0034] For the guaranteed transition edge, the phase information PD_UP0 and PD_DN0 are complementary. That is, when one of the phase information PD_UP0 and PD_DN0 is b'1, the other must be b'0. In some embodiments, the phase-locked loop circuit 108 can determine the lag information based on the phase information PD_UP0 and the lead information based on the phase information PD_DN0. If the phase information PD_UP0 is b'1, the phase-locked loop circuit 108 can determine that the clock CK60 lags behind the guaranteed transition edge and advances the phase of all clocks 106. If the phase information PD_DN0 is b'1, the phase-locked loop circuit 108 can determine that the clock CK60 leads the guaranteed transition edge and delays the phase of all clocks 106.

[0035] When clock pulses CK120 or CK180 sample the guaranteed transition edge, comparators 313 and 314 or comparators 315 and 316 can operate according to principles similar to comparators 311 and 312. The phase-locked loop circuit 108 can determine the leading or lagging information based on phase information PD_UP1 and PD_DN1 or phase information PD_UP2 and PD_DN2, according to principles similar to PD_UP0 and PD_DN0.

[0036] Figure 4 is a schematic diagram of a binary clock and data recovery method for CDR circuit 100. Figure 4 is explained below in conjunction with Figures 1 and 3. Within the data packet duration Tpckt, the data packet contains nine sampled values ​​D0, D1, D2, D3, D4, D5, D6, D7, and D8, sampled by clocks CK0, CK120, and CK240. The data packet duration Tpckt can contain three clock cycle durations Tclk. Within each clock cycle duration Tclk, the data signal Sin can be sampled once by each clock CK0, CK120, and CK240, thereby generating 9 bits of data. The 9 bits of data are generated by samplers 301, 303, and 305. Sampler 301 can use clock CK0 to generate sampled values ​​D0, D3, and D6; sampler 303 can use clock CK120 to generate sampled values ​​D1, D4, and D7; and sampler 305 can use clock CK240 to generate sampled values ​​D2, D5, and D8. The sorting circuit 104 can constantly enable comparators 311 and 312. If the communication protocol defines a guaranteed transition edge (e.g., transition edge 402 in Figure 4) between D0 and D1 in each data packet, and the sorting circuit 104 successfully identifies the correct data packet order, then the sorting circuit 104 can constantly enable comparators 311 and 312. That is, comparators 311 and 312 remain in the "enabled" state for the entire data packet duration Tpckt. Furthermore, the sorting circuit 104 can constantly enable samplers 301 to 303 and 305, as well as storage devices 321 and 322. Meanwhile, samplers 304 and 306, comparators 313 to 316 and storage devices 323 to 326 remain in the "off" state during the data packet duration Tpckt.

[0037] Within the duration Tclk of the first clock cycle, sampled values ​​D0 to D2 are generated sequentially, with a guaranteed transition edge occurring between sampled values ​​D0 and D1. As mentioned earlier, sampled values ​​D0 and D1 are in opposite states; specifically, if sampled value D0 is b'0, then sampled value D1 is b'1, and vice versa. Therefore, sampler 302 uses clock CK60 to sample the value at guaranteed transition edge 402, comparator 311 compares the sampled value at guaranteed transition edge 402 with sampled value D0 to generate phase information PD_UP0, and comparator 312 compares the sampled value at guaranteed transition edge 402 with sampled value D1 to generate phase information PD_DN0. Phase-locked loop circuit 108 can determine lead / lag information based on phase information PD_UP0 and PD_DN0, and adjust clock 106 based on this lead / lag information.

[0038] Comparators 313 and 314 are in the off state, and no lead / lag information is generated between sampled values ​​D1 and D2, therefore the phase of clock 106 will not be adjusted. Similarly, comparators 315 and 316 are in the off state, and no lead / lag information is generated between sampled values ​​D2 and D3, therefore the phase of clock 106 will not be adjusted.

[0039] During the duration Tclk of the second clock cycle, sampled values ​​D3 to D5 are generated sequentially, and a transition edge may occur between sampled values ​​D3 and D4. Sampler 302 uses clock CK60 to sample the value at the possible transition edge 404. Comparator 311 compares the sampled value at the possible transition edge 404 with sampled value D3 to generate phase information PD_UP0, and comparator 312 compares the sampled value at the possible transition edge 404 with sampled value D4 to generate phase information PD_DN0. Phase-locked loop circuit 108 can determine the lead / lag information based on phase information PD_UP0 and PD_DN0. If a data transition occurs between sampled values ​​D3 and D4, clock 106 is adjusted according to the lead / lag information.

[0040] Comparators 313 and 314 are in the off state, and no lead / lag information is generated between sampled values ​​D4 and D5, therefore the phase of clock 106 will not be adjusted. Similarly, comparators 315 and 316 are in the off state, and no lead / lag information is generated between sampled values ​​D5 and D6, therefore the phase of clock 106 will not be adjusted.

[0041] During the duration Tclk of the third clock cycle, sampled values ​​D6 to D8 are generated sequentially, and a transition edge may occur between sampled values ​​D6 and D7. Sampler 302 uses clock CK60 to sample the value at the possible transition edge 406. Comparator 311 compares the sampled value at the possible transition edge 406 with sampled value D6 to generate phase information PD_UP0, and comparator 312 compares the sampled value at the possible transition edge 406 with sampled value D7 to generate phase information PD_DN0. Phase-locked loop circuit 108 can determine lead / lag information based on phase information PD_UP0 and PD_DN0. If a data transition occurs between sampled values ​​D6 and D7, clock 106 is adjusted according to the lead / lag information.

[0042] Comparators 313 and 314 are in the off state, and no lead / lag information is generated between sampled values ​​D7 and D8, therefore the phase of clock 106 will not be adjusted. Similarly, comparators 315 and 316 are in the off state, and no lead / lag information is generated between sampled values ​​D8 and D9, therefore the phase of clock 106 will not be adjusted.

[0043] In this embodiment, the data packet length is not limited to 9, but can be any other positive integer, and the number of transition edges is not limited to 1, but can also be any other positive integer.

[0044] Figure 5 is a schematic diagram of another binary clock and data recovery method for CDR circuit 100. The setup in Figure 5 is similar to that in Figure 4, but the sorting circuit 104 can cyclically enable comparators 311 and 312. If the communication protocol defines a guaranteed transition edge (e.g., transition edge 502 in Figure 5) in each data packet, and this transition edge always occurs between D0 and D1, and the sorting circuit 104 successfully identifies the correct data packet order, then the sorting circuit 104 can cyclically enable comparators 311 and 312. That is, within the duration Tpckt of each data packet, comparators 311 and 312 remain in the "enabled" state during the first clock cycle duration Tclk, and remain in the "disabled" state during the second and third clock cycle durations Tclk. In addition, the sorting circuit 104 can cyclically enable sampler 302, as well as storage devices 321 and 322. Samplers 304 and 306, comparators 313 to 316, and storage devices 323 to 326 remain in the "off" state during the data packet duration Tpckt.

[0045] The operation in Figure 5 is similar to that in Figure 4, except that the operation differs from that in Figure 4 in the possible transition edge 504 between the sampled values ​​D3 and D4 within the second clock cycle duration Tclk, and in the possible transition edge 506 between the sampled values ​​D6 and D7 within the third clock cycle duration Tclk. The following discussion will focus on this difference.

[0046] When a possible transition edge 504 occurs, comparators 311 and 312 are in the off state and do not generate lead / lag information, therefore the phase of clock 106 is not adjusted. Similarly, when a possible transition edge 506 occurs, comparators 311 and 312 are in the off state and do not generate lead / lag information, therefore the phase of clock 106 is not adjusted.

[0047] Sampler 302, comparators 311 and 312, and storage devices 321 and 322 are periodically started and stopped, operating only at the guaranteed transition edge 502. Therefore, the operating time of sampler 302, comparators 311 and 312, and storage devices 321 and 322 is shorter than that in Figure 4, further improving reliability and reducing power consumption.

[0048] Figure 6 illustrates a clock and data recovery (CDR) circuit 600 for a 1 / 2 data rate linear system according to an embodiment of the present invention. A 1 / 2 data rate refers to using two clock phases to sample the data signal Sin. The linear CDR circuit 600 uses an analog phase detector to continuously extract phase information from the data signal Sin using the clock CLK, while the binary CDR circuit 100 uses a binary phase detector to generate discrete lead or lag information. The CDR circuit 600 can sample the data signal Sin at two phases of the clock CLK to generate a sequence signal PL, with the two clock phases differing by 180 degrees. In embodiments, the rising edge and falling edge can be used as the first and second clock phases of the clock CLK, respectively. In some embodiments, the falling edge and rising edge can be used as the first and second clock phases of the clock CLK, respectively.

[0049] The CDR circuit 600 may include a phase detector (PD) 602, a sequencing circuit 604, a clock CLK, and a phase-locked loop circuit 608. The difference between the linear CDR circuit 600 and the binary CDR circuit 100 lies in the structure and operation of the phase detector 602, which will be discussed in detail in later paragraphs. The structure and operation of other circuit elements in the linear CDR circuit 600 are similar to those in the binary CDR circuit 100, and will not be described further here.

[0050] Phase detector 602 receives data signal Sin from a data source and clock CLK from phase-locked loop circuit 608. Phase detector 602 may include sampler 603 and error and reference generator 605. Sampler 603 samples data signal Sin using the rising edge of clock CLK and outputs sampled values ​​Di, Di+2, and Di+4 through data line 611; and samples data signal Sin using the falling edge of clock CLK and outputs sampled values ​​Di+1, Di+3, and Di+5 through data line 612. Sequencing circuit 604 (data sorter) is coupled to phase detector 602 through two data lines 611 and 612. Sequencing circuit 604 can arrange the sampled values ​​into a specific order Di, Di+1, Di+2, Di+3, Di+4, and Di+5 according to a known pattern, and then transmit the sorted sequence as sorting signal PL to subsequent circuits for further processing.

[0051] Error and reference generator 605 generates phase information based on the data signal Sin and the clock signal CLK. The phase information may include an error pulse and a reference pulse. The error pulse represents the time difference between the transition edge of the data signal Sin and the rising or falling edge of the clock signal CLK, while the reference pulse measures the duration of the interval between consecutive rising and falling edges of the clock signal CLK. Error and reference generator 605 can send the phase information to phase-locked loop circuit 608.

[0052] The phase-locked loop circuit 608 may include a charge pump, a filter, and a voltage-controlled oscillator (VCO) to adjust the phase and frequency of the clock CLK. The charge pump receives an error pulse in the rising signal (UP signal) and a reference pulse in the falling signal (DOWN signal). When an error pulse appears in the rising signal, the charge pump increases the voltage of the charge pump signal; when a reference pulse appears in the falling signal, the charge pump decreases the voltage of the charge pump signal, adjusting the level of the charge pump signal according to the UP and DOWN signals. The charge pump signal is filtered to smooth fluctuations and remove high-frequency noise, generating a stable VCO control voltage. The VCO adjusts the frequency of the clock CLK according to the VCO control voltage, adjusting the first and second clock phases of the clock CLK transmitted to the phase detector 602. The CDR circuit 600 continuously adjusts the phase of the clock CLK based on the phase information generated by the first and second clock phases.

[0053] The sorting circuit 604 can be coupled to the phase detector 602 via two control lines 621 and 622. Based on the data sequence and to ensure the transition edge, the circuit elements in the error and reference generator 605 can be disabled by the control signals Sc1 and Sc2 transmitted via control lines 621 and 622 respectively.

[0054] Figure 7 is a circuit diagram of phase detector 602. Sampler 603 may include flip-flops FF1 and FF2. Error and reference generator 605 may include latches L1 to L4 and mutual exclusion gates XOR1 to XOR3. Sampler 603 and error and reference generator 605 may receive data signal Sin and clock signal CLK. Error and reference generator 605 may also receive control signals Sc1 and Sc2.

[0055] The flip-flop FF1 includes an input terminal D for receiving the data signal Sin; a clock terminal CK for receiving the rising edge of the clock signal CLK; and an output terminal Q for generating the sampled data signal D0. The flip-flop FF2 includes an input terminal D for receiving the data signal Sin; a clock terminal CK for receiving the falling edge of the clock signal CLK; and an output terminal Q for generating the sampled data signal D180.

[0056] Latch L1 includes input D for receiving the data signal Sin; clock input CK for receiving the rising edge of the clock signal CLK; and output Q for generating the latch signal SL1. Latch L2 includes input D for receiving the data signal Sin; clock input CK for receiving the falling edge of the clock signal CLK; and output Q for generating the latch signal SL2. Latch L3 includes input D, coupled to the output Q of latch L1; clock input CK for receiving the falling edge of the clock signal CLK; and output Q for generating the latch signal SL3. Latch L4 includes input D, coupled to the output Q of latch L2; clock input CK for receiving the rising edge of the clock signal CLK; and output Q for generating the latch signal SL4.

[0057] The mutual exclusion gate XOR1 includes a first input terminal coupled to the output terminal Q of latch L2 to receive latch signal SL2; a second input terminal coupled to the output terminal Q of latch L3 to receive latch signal SL3; and an output terminal to output an error pulse on the error signal ERR2. The mutual exclusion gate XOR2 includes a first input terminal coupled to the output terminal Q of latch L3 to receive latch signal SL3; a second input terminal coupled to the output terminal Q of latch L4 to receive latch signal SL4; and an output terminal to output a reference pulse on the reference signal REF. The mutual exclusion gate XOR3 includes a first input terminal coupled to the output terminal Q of latch L4 to receive latch signal SL4; a second input terminal coupled to the output terminal Q of latch L1 to receive latch signal SL1; and an output terminal to output an error pulse on the error signal ERR1. Therefore, error signals ERR1 and ERR2 can be used as rising signals for the charge pump, and reference signal REF can be used as falling signals for the charge pump.

[0058] The mutex XOR1 can be disabled by control signal Sc1, while the mutex XOR3 can be disabled by control signal Sc2. Latches L1 to L4 and the mutex XOR2 can be disabled by control signals Sc1 and Sc2.

[0059] In this embodiment of the invention, the CDR circuit and CDR method disable circuit elements according to data sequence and ensure switching edges, thereby improving reliability while saving power consumption. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0060] 100, 600: Clock and data recovery circuit 102, 602: Phase detectors 103, 603: Sampler 104, 604: Sorting circuits 105: Comparator 106: Time Pulse 108, 608: Phase-locked loop circuit 111 to 113, 611, 612: Data lines 121 to 123, 621, 622: Control lines 200: Method S202 to S208: Steps 301 to 306: Sampler 311 to 316: Comparators 321 to 326: Storage devices 605: Error and Reference Generator CK0, CK60, CK120, CK180, CK240, CK300, CLK: Clock Speed CK0O, CK60O, CK120O, CK180O, CK240O, CK300O: Clock Di to Di+8, D0, D60, D120, D180, D240, D300, D0 to D11: Sample values ERR1, ERR2: Error signals L1 to L4: Latches FF1 and FF2: Shifters LSB: Least Significant Bit MSB: Most significant bit PB, PL: Sequencing signals PD_UP0 to PD_UP2, PD_DN0 to PD_DN2: Phase information REF: Reference Signal Sc1 to Sc3: Control signals Sin: Data signal SL1 to SL4: Latch Signals Tclk: Clock cycle duration Tpckt: Data packet duration UP0 to UP2, DN0 to DN2: Comparison Results XOR1 to XOR3: Mutually exclusive or gate-dependent

Claims

1. A clock and data recovery circuit, comprising: a phase detector, comprising: N samplers for sampling a data signal using N clocks to generate a plurality of sampled values, wherein N is an integer greater than 1; and N comparators, wherein one of the N comparators compares a phase of the data signal with a phase of a selected clock among the N clocks; and a data sequencer coupled to the phase detector for determining a data order of the plurality of sampled values, and selectively disabling the N comparators based on the data order and a promised transition edge.

2. The circuit as described in claim 1 further includes a plurality of control lines coupled to the data sequencer and the phase detector, transmitting a plurality of control signals from the data sequencer to the phase detector to selectively disable the N comparators.

3. The circuit as described in claim 1, wherein the data sorter further enables the remaining comparators among the N comparators in a cyclic manner.

4. The circuit as described in claim 1, wherein the data sorter further enables the remaining comparators among the N comparators in a constant manner.

5. The circuit as described in claim 1, wherein the guaranteed transition edge occurs in a preamble sequence.

6. The circuit as described in claim 1, wherein the guaranteed transition edge appears in a delimiter field of a data packet.

7. The circuit as described in claim 1, wherein the guaranteed transition edge appears in a redundant field of a data packet.

8. The circuit as described in claim 1, wherein the data sorter further selectively disables the N samplers based on the data order and the guaranteed transition edge.

9. The circuit as described in claim 8, wherein: The N samplers include a plurality of transition samplers that sample a plurality of transition edges; and the data sorter identifies a target transition sampler from the plurality of transition samplers according to the data order, the target transition sampler samples the guaranteed transition edge, and disables the remaining transition samplers in the plurality of transition samplers.

10. The circuit as described in claim 9, wherein: The comparator is coupled to two corresponding samplers among the N samplers, and compares the two corresponding sample values ​​to produce a comparison result; The data sorter disables any of the N comparators that are not coupled to the target transformation sampler.

11. The circuit as described in claim 10, wherein: The phase detector further includes N storage devices, each storage device being coupled to a corresponding comparator among the N comparators to store a comparison result from the corresponding comparator; and the data sorter selectively disables the N storage devices according to the data order and the guaranteed transition edge.

12. The circuitry as described in claim 11, wherein the data sorter disables any of the N storage devices that are not coupled to the target conversion sampler.

13. A clock and data recovery method, comprising: sampling a data signal using N clocks with N samplers to generate a plurality of sampled values, wherein N is an integer greater than 1; comparing a phase of the data signal with a phase of a selected clock among the N clocks using one of the N comparators; determining a data order of the plurality of sampled values ​​using a data sorter; and selectively disabling the N comparators based on the data order and a guaranteed transition edge using the data sorter.

14. The method of claim 13, wherein a phase detector includes the N samplers and the N comparators; and selectively disabling the N comparators by means of the data sorter according to the data order and the guaranteed transition edge comprises: transmitting a plurality of control signals to the phase detector via a plurality of control lines by means of the data sorter to selectively disable the N comparators.

15. The method as described in claim 13 further includes enabling the remaining comparators among the N comparators in a cyclic manner by means of the data sorter.

16. The method as described in claim 13 further includes enabling the remaining comparators among the N comparators in a constant manner by means of the data sorter.

17. The method as described in claim 13, wherein the guaranteed transition edge appears in a leading sequence.

18. The method as described in claim 13, wherein the guaranteed conversion edge appears in a delimiter field of a data packet.

19. The method as described in claim 13, wherein the guaranteed transition edge appears in a redundant field of a data packet.

20. The method as described in claim 13 further comprises: selectively deactivating the N samplers by means of the data sorter based on the data order and the guaranteed transition edge.

21. The method of claim 20, wherein the N samplers comprise a plurality of transition samplers that sample transition edges; and selectively deactivating the N samplers by means of the data sorter according to the data order and the guaranteed transition edge comprises: identifying a target transition sampler from the plurality of transition samplers according to the data order by means of the data sorter, the target transition sampler sampling the guaranteed transition edge; and deactivating the remaining transition samplers from the plurality of transition samplers by means of the data sorter.

22. The method as described in claim 21, wherein the comparator is coupled to two corresponding samplers of the N samplers, compares two corresponding sample values ​​to produce a comparison result; and selectively deactivating the N comparators by means of the data sorter according to the data order and the guaranteed transition edge includes: deactivating any comparator among the N comparators that is not coupled to the target transition sampler by means of the data sorter.

23. The method as described in claim 22 further comprises: storing a comparison result from a corresponding comparator in one of the N storage devices; and selectively deactivating the N storage devices by means of the data sorter based on the data order and the guaranteed transition edge.

24. The method as described in claim 23, wherein selectively disabling the N storage devices by means of the data sorter based on the data order and the guaranteed transition edge comprises: disabling any of the N storage devices that are not coupled to the target transition sampler by means of the data sorter.

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