Disaggregated caches for processor cores
TW202634909APending Publication Date: 2026-08-16AMERICAN CO ADIA SEMICON BONDING TECH CO LTD
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Patent Information
- Application Number
- TW115100272
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-01-27
- Filing Date
- 2026-01-05
- Publication Date
- 2026-08-16
Smart Images
Figure TWG2TA001073344_001 
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Abstract
A structure is disclosed. The structure can include a first processor core, first one or more wiring layers, second one or more wiring layers, and a first cache chiplet. The first one or more wiring layers can be disposed vertically below the first processor core, with wires of the first one or more wiring layers having a first average wire width. The second one or more wiring layers can be disposed vertically below the first one or more wiring layers, with wires of the second one or more wiring layers having a second average wire width that is larger than the first average wire width. The first cache chiplet can be disposed vertically below the first one or more wiring layers and at least partially embedded within the second one or more wiring layer. The first cache chiplet can be hybrid bonded to the first one or more wiring layers.
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