Manufacturing method of memory device

Abstract

A manufacturing method of a memory device including: forming a landing pad over a substrate; forming a first insulating structure over the substrate and the landing pad; forming a patterned mask layer over the insulating structure; removing portions of the first insulating structure by the patterned mask layer to form a container exposing the landing pad; forming an electrode structure over the substrate, wherein the electrode structure comprises a first portion disposed on the patterned mask layer and a second portion disposed in the container; removing the first portion of the electrode structure by a first etching back process; removing the patterned mask layer by a second etching back process to form recesses on the first insulating structure and beside the second portion of the electrode structure; and forming a second insulating structure in the recesses.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a memory device. Prior Technology

[0002] As technology continues to advance, the height and width of the storage electrodes in a capacitor will affect the performance of memory devices. For example, capacitors with a high aspect ratio (AR) present challenges related to cost and quality. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a memory device, comprising: forming a landing pad on a substrate; forming a first insulating structure on the substrate and the landing pad; forming a patterned masking layer on the first insulating structure; removing a portion of the first insulating structure through the patterned masking layer to form a container exposing the landing pad; forming an electrode structure including a first portion disposed on the patterned masking layer and a second portion disposed in the container; removing the first portion of the electrode structure through a first etching process; removing the patterned masking layer through a second etching process to form a recess on the first insulating structure and next to the second portion of the electrode structure; and forming a second insulating structure in the recess.

[0004] To make the above easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Simple Explanation of the Diagram

[0005] The drawings are provided to further illustrate the invention and are incorporated in and constitute a part of this specification. The drawings depict exemplary embodiments of the invention and are used in conjunction with the text to explain the principles of the invention. Figure 1 is a flowchart of some intermediate steps in some embodiments of a method for manufacturing a memory device. Figures 2 to 9 show partial cross-sectional views of a method for manufacturing a memory device according to some embodiments of the present disclosure. Figure 10 shows a partial cross-sectional view of a memory device according to another alternative embodiment of the present disclosure. Implementation

[0006] Embodiments or examples of the present disclosure illustrated in the figures will now be described using specific language. It should be understood that this is not intended to limit the scope of the disclosure in any way. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as generally occurring to those skilled in the art associated with this disclosure. Reference numerals may appear repeatedly throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0007] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the "first element," "component," "region," "layer," or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0008] The performance of memory devices may involve the capacitors within each cell. For example, the storage electrodes of the capacitors in a memory device are container-shaped, and technological advancements have led to an increase in the height and a decrease in the width of container-shaped storage nodes. Here, the height of the container can be formed by various insulating films (e.g., at least five stacked insulating layers). However, this design may result in a high aspect ratio, potentially increasing manufacturing costs. For instance, etching techniques used for high aspect ratios are very expensive, such as the high cost of photolithography equipment. Furthermore, the quality of the container may be degraded when the desired container height is achieved through a single etching process (deep etching). In this disclosure, the problem of high aspect ratios can be mitigated by first reducing the container height and then performing a back-etch process followed by backfilling with another insulating layer that can compensate for the remaining portion of the desired height.

[0009] Figure 1 is a flowchart of some intermediate steps in some embodiments of a method for manufacturing a memory device. The method includes multiple blocks (block S101, block S102, block S103, block S104, block S105, block S106, block S107, and block S108). The description and illustrations are not intended to limit the order of operations.

[0010] In block S101, a landing pad is formed on the substrate. In block S102, a first insulating structure is formed on the substrate and the landing pad. In block S103, a patterned masking layer is formed on the first insulating structure. Figure 2 shows cross-sectional views corresponding to some embodiments of blocks S101, S102, and S103.

[0011] In Figure 2, a substrate 110 is provided. In some embodiments, substrate 110 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. In some embodiments, substrate 110 comprises elemental semiconductors of silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials comprising at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials comprising at least one of silicon, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable materials, or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a silicon alloy with gradient silicon characteristics, wherein the silicon and metal composition varies from one ratio at one location of the gradient silicon characteristics to another ratio at another location. For example, the alloy semiconductor substrate may be a silicon-germanium alloy with gradient silicon-germanium characteristics, wherein the silicon and germanium composition varies from one ratio at one location of the gradient silicon-germanium characteristics to another ratio at another location. In another embodiment, a silicon-germanium alloy is formed on a silicon substrate. In some embodiments, the silicon-germanium alloy may be mechanically strained by another material in contact with the silicon-germanium alloy.

[0012] Furthermore, an isolation layer 111 and a plurality of landing pads 112 are formed on the substrate 110, wherein the landing pads 112 are embedded in the isolation layer 111 to maintain better electrical performance. In some embodiments, a chemical mechanical planarization (CMP) operation may be performed over the isolation layer 111 and the landing pads 112 such that the top surface 111t of the isolation layer 111 and the top surface 112t of the landing pads 112 are substantially coplanar. In some embodiments, the isolation layer 111 comprises a suitable insulating material, and the landing pads 112 comprise a suitable conductive material.

[0013] Then, an insulating structure 120 (which may be referred to as a first insulating structure) is formed on the substrate 110, extending over the top surface 111t of the isolation layer 111 and the top surface 112t of the landing pad 112. The material of the insulating structure 120 includes nitrides or oxides, such as silicon nitride (SiN), BPSG, TEOS, or the like. After forming the insulating structure 120, a patterned masking layer 130 is formed on the insulating structure 120 for subsequent processes (such as etching processes). In this embodiment, the top surface 120t of the insulating structure 120 directly contacts the bottom surface 130b of the patterned masking layer 130. Furthermore, the patterned masking layer 130 may include a plurality of openings 130a to expose portions of the top surface 120t of the insulating structure 120 directly above the landing pad 112. In some embodiments, the material of the patterned masking layer 130 includes polycrystalline silicon. Here, the insulating structure 120 and the patterned masking layer 130 can be formed by a suitable deposition process, such as blanket deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or similar methods.

[0014] The term "patterning" as used in this disclosure describes the operation of forming a predetermined pattern on a surface. Patterning operations include various steps and processes, and vary depending on the embodiment. In some embodiments, a patterning process is used to pattern an existing thin film or layer (e.g., polycrystalline silicon). The patterning process includes forming a mask on the existing thin film or layer and removing the unmasked thin film or layer by etching or other removal processes. The mask may be a photoresist or a hard mask.

[0015] In block S104, a portion of the first insulating structure is removed by a patterned masking layer to form a container that exposes the landing pad. Figures 2 and 3 show cross-sectional views corresponding to some embodiments of block S104.

[0016] In Figure 2, the insulating structure 120 includes four insulating layers 121. For example, a nitride layer 121a (which may be referred to as the first nitride layer), an oxide layer 121b (which may be referred to as the first oxide layer), a nitride layer 121c (which may be referred to as the second nitride layer), and an oxide layer 121d (which may be referred to as the second oxide layer) are sequentially stacked on the substrate 110. In some embodiments, the materials of the nitride layers 121a and 121c include silicon nitride (SiN) or the like, and the materials of the oxide layers 121b and 121d include BPSG, TEOS, or the like. It should be noted that the number of layers (121a, 121b, 121c, and 121d) is not considered a limitation of this disclosure, and the number of layers in the insulating structure 120 may be determined according to actual design requirements.

[0017] In Figure 3, a portion of the insulating structure 120 is removed by a patterned mask layer 130 to form multiple containers 10 exposing the landing pad 112. Here, the removal process can be a suitable etching process. In this embodiment, the aspect ratio is the ratio of the height 120H of the insulating structure 120 to the width 10W (e.g., critical dimension, CD) of the container 10. For example, the four insulating layers 121 of the insulating structure 120 can replace the five insulating layers of the capacitor structure; in other words, the height 120H of the insulating structure 120 (four insulating layers 121) is smaller than the height of the capacitor structure (five insulating layers), allowing for a reduction in the removal height (e.g., etching height). This eliminates the need for sophisticated lithography equipment, improves the quality of the container 10 (better etching process completion), and mitigates the problem of a high aspect ratio.

[0018] In some embodiments, the height 120H of the insulating structure 120 ranges from 1000 nm to 1300 nm, and the width 10W of the container 10 ranges from 20 nm to 30 nm (e.g., from 20 nm to 24 nm). Therefore, the aspect ratio of each container 10 ranges from 30 to 40, and the aspect ratio of the container 10 can be controlled within a range that is easier to etch. In this embodiment, since the oxide is easier to remove, the heights of the oxide layers 121b and 121d are greater than those of the nitride layers 121a and 121c. For example, the height Ha of the nitride layer 121a ranges from 20 nm to 30 nm, the height Hb of the oxide layer 121b ranges from 5000 Å to 5400 Å, the height Hc of the nitride layer 121c ranges from 20 nm to 30 nm, and the height Hd of the oxide layer 121d ranges from 4000 Å to 4500 Å. On the other hand, in step 2 of Figure 2, the height 130H of the patterned masking layer 130 ranges from 350 nm to 500 nm, while in step 3 of Figure 3, the height 130H of the patterned masking layer 130 may become 100 nm to 200 nm. That is to say, part of the patterned masking layer 130 can be removed during the formation of the container 10. In this embodiment, the width 10W of the container 10 is less than or equal to the width of the landing pad 112. By doing so, the impedance is reduced, and better electrical performance can be achieved.

[0019] In block S105, an electrode structure is formed on the substrate. Figures 4 to 6 show cross-sectional views corresponding to some embodiments of block S105.

[0020] In one embodiment, as shown in Figures 4 to 6, a double-site electrode structure 140 is formed on a substrate 110. That is, the electrode structure 140 consists of two conductive layers 141 and 143 and a dielectric layer 142 between the two conductive layers 141 and 143. The electrode structure 140 is formed as follows: In Figure 4, the conductive layer 141 is conformally formed on the substrate 110. Therefore, the conductive layer 141 covers the top surface 112t of the landing pad 112, the sidewalls 120s of the insulating structure 120, the sidewalls 130s of the patterned masking layer 130, and the top surface 130t of the patterned masking layer 130. The conductive layer 141 can be referred to as the top electrode. In this embodiment, the conductive layer 141 directly contacts and is electrically connected to the landing pad 112. In Figure 5, the dielectric layer 142 is conformally formed on the substrate 110. For example, the top surface 141t of the conductive layer 141 is covered by the dielectric layer 142. In FIG. 6, the conductive layer 143 is conformally formed on the substrate 110. For example, the top surface 142t of the dielectric layer 142 is covered by the conductive layer 143, wherein the conductive layer 143 may be referred to as the bottom electrode. In this embodiment, the electrode structure 140 does not fill the container 10 in FIG. 3.

[0021] In this embodiment, the nitride layer 121a is disposed beside and in direct contact with the bottom portion of the electrode structure 140 (which may be within one-third of the electrode structure 140) to enhance the structural strength of the electrode structure 140. Furthermore, the nitride layer 121c is disposed beside and in direct contact with the middle portion of the electrode structure 140 (which may be within one-third to two-thirds of the electrode structure 140) to further enhance the structural strength of the electrode structure 140.

[0022] In some embodiments, the material of conductive layer 141 includes TiN or the like. In some embodiments, the material of dielectric layer 142 includes a suitable high-k dielectric material. In some embodiments, the material of conductive layer 143 includes TiN or the like. Here, conductive layers 141, 143 and dielectric layer 142 can be formed by a suitable deposition process, such as blanket deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or the like.

[0023] In block S106, the first portion of the electrode structure is removed by a first etching back process. Figures 6 and 7 show cross-sectional views corresponding to some embodiments of block S106.

[0024] In Figure 6, the electrode structure 140 includes a first portion disposed on the patterned masking layer 130 and a second portion disposed in the container 10. Then, in Figure 7, the first portion disposed on the patterned masking layer 130 can be removed by a first etching process. For example, the etching gas in the first etching process may include Cl, BCl3, and Ar, and there is a high etch selectivity between the patterned masking layer 130 and the electrode structure 140, so that the first portion of the electrode structure 140 can be easily removed. In some embodiments, when Cl, BCl3, and Ar are used simultaneously in the first etching process, the ratio may be 3:1:1, but this disclosure is not limited to this, and other suitable values ​​may be used. After the first etching process, the top surface 140t of the electrode structure 140 and the top surface 130t of the patterned masking layer 130 are substantially coplanar. In this embodiment, the first etching process may slightly remove the patterned masking layer 130. For example, the height 130H of the patterned mask layer 130 in step 7 may be smaller than the height 130H of the patterned mask layer 130 in step 6, becoming approximately 80 nanometers or other suitable values.

[0025] In block S107, a patterned mask layer is removed by a second etching process to form a recess on the first insulating structure and next to the second portion of the electrode structure. Figure 8 shows a cross-sectional view corresponding to some embodiments of block S107.

[0026] In Figure 8, the etching gas in the second etching process may include Cl and CF4. The recess R can be formed by a high etch selectivity between the patterned mask layer 130 and the electrode structure 140, thereby allowing easy removal of the patterned mask layer 130. In some embodiments, when Cl and CF4 are used simultaneously in the second etching process, the ratio may be 3:1, but this disclosure is not limited thereto, and other suitable values ​​may be used.

[0027] In block S108, a second insulating structure is formed in the recess. Figure 9 shows a cross-sectional view corresponding to some embodiments of block S108.

[0028] In Figure 9, nitride material is deposited and the recess R is filled to form an insulating structure 150 (which may be referred to as a second insulating structure). In this embodiment, the insulating structure 150 can first completely cover the electrode structure 140 (not shown), and then remove it through another etching process, such that the top surface 140t of the electrode structure 140 and the top surface 150t of the insulating structure 150 are substantially coplanar. Furthermore, the height 150H of the insulating structure 150 is greater than the height Ha of the nitride layer 121a or the height Hc of the nitride layer 121c. In addition, the insulating structure 150 is disposed next to and in direct contact with the top portion of the electrode structure 140 to enhance the structural strength of the electrode structure 140.

[0029] Following Figure 9, other suitable processes can be performed to manufacture the capacitor. For example, the steps of Figures 2 through 9 (not shown) can be repeated. Furthermore, insulation structures 120 and 150 (not shown) can be removed depending on actual design requirements. It should be noted that the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing, material composition, methods, and steps described herein. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machines, manufacturing, material composition, methods, or steps are included within the scope of this patent application.

[0030] Referring to Figure 10, the memory device in Figure 10 includes a substrate 110, an isolation layer 111, a landing pad 112, an insulating structure 120, an insulating structure 150, and an electrode structure 240. The structures of the substrate 110, isolation layer 111, landing pad 112, insulating structure 120, and insulating structure 150 can be similar to those in the aforementioned embodiments, and will not be described again here. The electrode structure 240 of the memory device in this embodiment differs from the electrode structure 140 in the aforementioned embodiments. For example, the electrode structure 240 consists of a single conductive layer (single site) and fills the container 10. In this embodiment, the top surface 240t of the electrode structure 240 and the top surface 150t of the insulating structure 150 are substantially coplanar.

[0031] In this disclosure, the height of the container 10 (e.g., the etch height 120H of the insulating structure 120) can be reduced, while the remaining height required for the capacitor in the memory device can be achieved through at least two etch-back processes and backfilling with another insulating layer (e.g., the insulating structure 150). This allows the height of the container 10 to be flexibly designed, thereby improving the high aspect ratio problem. Furthermore, the quality of the container 10 can be improved.

[0032] To those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

[0033] 10: Container 10W: Width 110: Base 111: Isolation layer 111t, 112t, 120t, 130t, 140t, 141t, 142t, 150t, 240t: Top surface 112: Landing mat 120H, 130H, 150H, Ha, Hb, Hc, Hd: Height 120s, 130s: Sidewall 120, 150: Insulation structure 121a, 121c: Nitride layers 121b, 121d: Oxide layer 130: Patterned mask layer 130a: Opening 130b: Bottom surface 140, 240: Electrode Structure 141, 143: Conductive layer 142: Dielectric layer S101, S102, S103, S104, S105, S106, S107, S108: Squares R: Depression

Claims

1. A method for manufacturing a memory device, comprising: A landing pad is formed on the substrate; A first insulating structure is formed on the substrate and the landing pad; A patterned mask layer is formed on the first insulating structure; a portion of the first insulating structure is removed using the patterned mask layer to form a container exposing the landing pad, wherein the aspect ratio of the container is between 30 and 40; an electrode structure is formed on the substrate, wherein the electrode structure includes a first portion disposed on the patterned mask layer and a second portion disposed in the container; the first portion of the electrode structure is removed using a first etch process. The patterned mask layer is removed by a second etching process to form a recess on the first insulating structure and next to the second portion of the electrode structure; and a second insulating structure is formed in the recess.

2. A method for manufacturing a memory device as claimed in claim 1, wherein the etching gas in the first etching process comprises Cl, BCl3 and Ar.

3. A method for manufacturing a memory device as claimed in claim 1, wherein the etching gas in the second etching process comprises Cl and CF4.

4. A method of manufacturing a memory device as claimed in claim 1, wherein forming a second insulating structure in the recess includes depositing a nitride material to fill the recess.

5. A method of manufacturing a memory device as claimed in claim 1, wherein the material of the patterned mask layer includes polysilicon.

6. A method of manufacturing a memory device as claimed in claim 1, wherein the top surface of the first insulating structure directly contacts the bottom surface of the patterned mask layer.

7. A method of manufacturing a memory device as claimed in claim 1, wherein after the first etch process, the top surface of the electrode structure and the top surface of the patterned mask layer are coplanar.

8. A method of manufacturing a memory device as claimed in claim 1, wherein the top surface of the electrode structure and the top surface of the second insulating structure are coplanar.

9. A method of manufacturing a memory device as claimed in claim 1, wherein the height of the first insulating structure is between 1000 nanometers and 1300 nanometers.

10. A method of manufacturing a memory device as claimed in claim 1, wherein the width of the container is less than or equal to the width of the landing pad.

11. A method of manufacturing a memory device as claimed in claim 1, wherein the first insulating structure includes a first nitride layer disposed on the substrate and a first oxide layer disposed on the first nitride layer.

12. A method of manufacturing a memory device as claimed in claim 11, wherein the first nitride layer is disposed beside and in direct contact with the bottom portion of the electrode structure.

13. The method of manufacturing a memory device as claimed in claim 11, wherein the height of the first oxide layer is greater than the height of the first nitride layer.

14. A method of manufacturing a memory device as claimed in claim 11, wherein the height of the second insulating structure is greater than the height of the first nitride layer.

15. A method of manufacturing a memory device as claimed in claim 11, wherein the height of the first nitride layer is between 20 nanometers and 30 nanometers.

16. A method of manufacturing a memory device as claimed in claim 11, wherein the first insulating structure further comprises a second nitride layer disposed on the first oxide layer and a second oxide layer disposed on the second nitride layer.

17. A method of manufacturing a memory device as claimed in claim 16, wherein the second nitride layer is disposed beside and in direct contact with the middle portion of the electrode structure.

18. A method of manufacturing a memory device as claimed in claim 1, wherein the electrode structure comprises two conductive layers and a dielectric layer inserted between the two conductive layers, and the electrode structure is conformally formed on the substrate.

19. A method of manufacturing a memory device as claimed in claim 1, wherein the electrode structure comprises a conductive layer and the electrode structure fills the container.

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