Vertical channel transistor and dram structure

Abstract

A vertical channel transistor includes at least an oxide semiconductor pillar, a first electrode, a second electrode, a gate layer and a gate oxide layer. The oxide semiconductor pillar has a first end and a second end. The first electrode connects to the first end of the oxide semiconductor pillar, and the second electrode connects to the second end of the oxide semiconductor pillar. The gate layer surrounds a middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material which is difficult to react with oxygen. The gate oxide layer is disposed between the oxide semiconductor pillar and the gate layer.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a vertical channel transistor and dynamic random access memory (DRAM) structure. Prior Technology

[0002] In order to continue the development path of DRAM below 10nm, it is proposed to replace the 6F2 unit cell structure with a 4F2 unit cell structure of vertical channel / pillar transistor (VCT / VPT) to meet the requirements of high density and low cost.

[0003] To realize the vertical channel / pillar transistor (VCT / VPT) in 4F2DRAM, oxide semiconductor transistors are used as the channel material because they have extremely low leakage current, large bandgap and high electron mobility.

[0004] However, there are some problems that affect the performance of oxide semiconductor transistors, such as the side effects caused by Vth instability (Vth negative shift), namely, deterioration of gate controllability, poor high turn-off current and low drive current. Summary of the Invention

[0005] This invention provides a vertical channel transistor and DRAM structure that can avoid Vth instability and obtain high drive current.

[0006] A vertical channel transistor according to one embodiment of the present invention includes at least an oxide semiconductor pillar having a first end and a second end, a first electrode connected to the first end of the oxide semiconductor pillar, a second electrode connected to the second end of the oxide semiconductor pillar, a gate layer, and a gate oxide layer. The gate layer surrounds the middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material that is difficult to react with oxygen. The gate oxide layer is located between the oxide semiconductor pillar and the gate layer.

[0007] In one embodiment of the present invention, the oxide semiconductor pillars are vertically disposed above the substrate.

[0008] In one embodiment of the present invention, the distance between the first electrode and the gate layer is equal to or different from the distance between the second electrode and the gate layer.

[0009] In embodiments of the present invention, the aforementioned metal-containing barrier material includes titanium nitride or tantalum nitride.

[0010] In one embodiment of the present invention, the gate layer has a thickness of less than 20 nm.

[0011] In one embodiment of the present invention, the gate layer is a single-layer structure.

[0012] In one embodiment of the present invention, the above-mentioned vertical channel transistor further includes an insulating structure, and the oxide semiconductor pillar, the gate oxide layer and the gate layer are located within the insulating structure.

[0013] In one embodiment of the present invention, the gate oxide layer may also be disposed between the oxide semiconductor pillar and the insulating structure.

[0014] In one embodiment of the present invention, the oxygen vacancy concentration in the middle part of the oxide semiconductor pillar is less than the oxygen vacancy concentration in the remaining part of the oxide semiconductor pillar.

[0015] Another embodiment of the DRAM structure of the present invention includes at least the above-described vertical channel transistor and a storage device coupled to the vertical channel transistor.

[0016] In another embodiment of the invention, the storage device includes a capacitor.

[0017] Based on the above, the vertical channel transistor of the present invention, by employing a barrier material as the gate layer, can prevent oxygen from diffusing out from the middle part of the oxide semiconductor, thereby improving the stability of the critical voltage (Vth). Furthermore, oxygen vacancies exist at both the upper and lower ends of the oxide semiconductor, thus reducing the resistivity of the interface between the oxide semiconductor and the two electrodes.

[0018] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0019] Figure 1 shows a plan view of a vertical channel transistor according to some embodiments of the present invention. Figure 2 shows a cross-sectional view of the vertical channel transistor in Figure 1. Figure 3 shows a cross-sectional view of the vertical channel transistor in Figure 2 after a high-temperature (HT) process. Figure 4 shows a cross-sectional view of a DRAM structure according to some embodiments of the present invention. Implementation

[0020] The invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for clarity and explicitness, the dimensions of each layer and region and their relative dimensions may not be shown to exact scale.

[0021] Figure 1 shows a plan view of a plurality of vertical channel transistors according to some embodiments of the present disclosure, and Figure 2 shows a cross-sectional view of the vertical channel transistor of Figure 1. For clarity, certain components, such as the insulating structure 112 and the second electrode 104 in Figure 2, are not shown in Figure 1.

[0022] Referring to Figures 1 and 2, each vertical channel transistor 100 includes at least an oxide semiconductor pillar OS having a first end e1 and a second end e2, a first electrode 102 connected to the first end e1 of the oxide semiconductor pillar OS, a second electrode 104 connected to the second end e2 of the oxide semiconductor pillar OS, a gate layer 106, and a gate oxide layer 108. In some embodiments, the oxide semiconductor pillar OS is vertically disposed above the substrate 110. In some embodiments, the material of the oxide semiconductor pillar OS can be at least one of indium gallium zinc oxide (IGZO), manganese oxide (MnO2), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., and the present invention does not impose any limitations thereon.

[0023] Gate layer 106 surrounds the central portion MP of oxide semiconductor pillar OS, wherein the central portion MP may be a central part occupying one-third of the height of oxide semiconductor pillar OS. In some embodiments, the height of gate layer 106 is less than the height of the central portion MP, but is not limited thereto. Gate layer 106 is made of a metal-containing barrier material that is not easily reactive with oxygen. For example, the aforementioned metal-containing barrier material may include titanium nitride or tantalum nitride. Gate layer 106 shown in FIG1 may also serve as a word line of vertical channel transistor 100. Gate oxide layer 108 is located between oxide semiconductor pillar OS and gate layer 106. In some embodiments, vertical channel transistor 100 also includes insulating structure 112. The aforementioned oxide semiconductor pillar OS, gate oxide layer 108 and gate layer 106 may be disposed in insulating structure 112. In some embodiments, gate oxide layer 108 is also disposed between oxide semiconductor pillar OS and insulating structure 112. In some embodiments, gate layer 106 has a thickness t1 of less than 20 nm; for example, 15 nm or less. In this text, "thickness t1" represents the dimension of the gate layer 106 perpendicular to the extension direction of the oxide semiconductor pillar OS. Research indicates that when the thickness t1 of titanium nitride is less than a certain value, its conductivity will be the same as, or even higher than, that of a metal of comparable thickness (e.g., tungsten). Therefore, metal-containing barrier materials can indeed serve as the gate of the vertical channel transistor 100. In some embodiments, the gate layer 106 is a single-layer structure, meaning that the gate layer 106 does not contain other layers, but only a single layer of metal-containing barrier material.

[0024] In some embodiments, the distance d2 between the first electrode 102 and the gate layer 106 is different from the distance d1 between the second electrode 104 and the gate layer 106. For example, distance d1 is shorter than distance d2, or distance d1 is greater than distance d2. In some embodiments, the distance d2 between the first electrode 102 and the gate layer 106 is equal to the distance d1 between the second electrode 104 and the gate layer 106.

[0025] In some embodiments, the insulating structure 112 includes a lower insulating layer 112L, an intermediate insulating layer 112M, and an upper insulating layer 112U stacked in sequence. The gate layer 106 may be located within the intermediate insulating layer 112M, which may be made of oxide or other suitable insulating material.

[0026] In some embodiments, the oxygen vacancy concentration in the middle portion MP of the oxide semiconductor pillar OS is lower than that in the rest of the oxide semiconductor pillar OS, as shown in FIG3. In FIG3, the vertical channel transistor 100 undergoes a high-temperature (HT) process, such as a hydrogen / chlorine / fluorine material-related process, to reduce the resistance at the top of the oxide semiconductor pillar OS, and oxygen out-diffusion occurs at both ends of the oxide semiconductor pillar OS, generating oxygen vacancies OV. Since oxygen vacancies help create space in the lattice, allowing elements to move when an electric field is applied, it helps reduce the channel resistance, thus expecting to generate a larger drive current. On the other hand, since the gate layer 106 is made of a metal-containing barrier material, oxygen does not diffuse out of the oxide semiconductor pillar OS or is difficult to diffuse out, so the middle portion MP has no oxygen vacancies or has fewer oxygen vacancies. Therefore, when the gate layer 106 has a shielding function to prevent the occurrence of oxygen vacancies, Vth (critical voltage) can become stable.

[0027] Figure 4 shows a cross-sectional view of a DRAM structure according to some embodiments of the present disclosure.

[0028] Referring to Figure 4, the DRAM structure includes the vertical channel transistor 100 in the above embodiments and a storage device 200 coupled to the vertical channel transistor 100. In some embodiments, the second electrode 104 of the vertical channel transistor 100 is connected to the storage device 200, and the first electrode 102 of the vertical channel transistor 100 can be connected to a bit line (not shown) or the storage device 200 through an interconnect (not shown). In some embodiments, the storage device 200 includes a capacitor. For example, the DRAM structure uses a 1T1C storage cell, where 1T represents the vertical channel transistor 100 and 1C represents the capacitor (storage device 200). In some embodiments, the capacitor may include two conductive layers (not shown) and a capacitive medium layer located between the two conductive layers, and the capacitive medium layer (not shown) and the two conductive layers may form a cylindrical structure. However, the content disclosed herein is not limited to this.

[0029] In summary, the gate layer acts as a barrier, preventing oxygen out-diffusion around the gate. Therefore, no oxygen vacancies are generated, and Vth remains stable (without negative shift). On the other hand, oxygen out-diffusion occurs in other areas (such as the top and bottom of the channel), creating oxygen vacancies. This helps reduce channel resistance and is expected to enable a larger drive current.

[0030] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0031] 100: Vertical Channel Transistor 102: First electrode 104: Second electrode 106: Gate Layer 108: Gate oxide layer 110:Substrate 112: Insulation structure 112L: Lower insulation layer 112M: Intermediate Insulation Layer 112U: Upper insulating layer 200: Storage device d1, d2: Distance e1: First end e2: Second end MP: Middle section OS: Oxide Semiconductor Pillar OV: Oxygen vacancy t1: Thickness

Claims

1. A vertical channel transistor, comprising: An oxide semiconductor pillar has a first end and a second end; a first electrode is connected to the first end of the oxide semiconductor pillar; A second electrode is connected to the second end of the oxide semiconductor pillar; a gate layer surrounds the middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material that is difficult to react with oxygen; and a gate oxide layer is located between the oxide semiconductor pillar and the gate layer, wherein the oxygen vacancy concentration in the middle portion of the oxide semiconductor pillar is less than the oxygen vacancy concentration in the rest of the oxide semiconductor pillar.

2. The vertical channel transistor as claimed in claim 1, wherein the oxide semiconductor pillar is vertically disposed above a substrate.

3. The vertical channel transistor as claimed in claim 1, wherein the distance between the first electrode and the gate layer is equal to the distance between the second electrode and the gate layer.

4. The vertical channel transistor as claimed in claim 1, wherein the distance between the first electrode and the gate layer is different from the distance between the second electrode and the gate layer.

5. The vertical channel transistor as claimed in claim 1, wherein the metal-containing barrier material comprises titanium nitride or tantalum nitride.

6. The vertical channel transistor as claimed in claim 1, wherein the gate layer has a thickness of less than 20 nm.

7. The vertical channel transistor as claimed in claim 1, further comprising an insulating structure, wherein the oxide semiconductor pillar, the gate oxide layer, and the gate layer are disposed in the insulating structure.

8. The vertical channel transistor as claimed in claim 7, wherein the gate oxide layer is further disposed between the oxide semiconductor pillar and the insulating structure.

9. The vertical channel transistor as claimed in claim 1, wherein the gate layer is a single-layer structure.

10. A DRAM structure, comprising: The vertical channel transistor as described in claim 1; And a storage device coupled to the vertical channel transistor.

11. The DRAM structure as claimed in claim 10, wherein the storage device includes a capacitor.

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