Integrated circuit device and method of manufacture

Abstract

A memory device includes a single logic die bonded with multiple memory dies, each memory die containing arrays of 1T1C memory cells of the type formed using back-end-of-line processing. Each memory die can include multiple vertically stacked tiers of the memory cells. Control circuits for the memory cells, including sense amplifiers and column drivers, are in the logic die. The logic die has a substrate and the memory die opposite the logic die has a substrate, but the substrates of the middle dies are absent having been removed during processing. Switches may be provided to isolate bitline segments, reducing parasitic capacitance and removing a constraint on the number of memory cell tiers that can be operated using the single logic die.

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