Method for forming semiconductor structure
TW202634928AInactive Publication Date: 2026-08-16NAN YA TECH
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Patent Information
- Application Number
- TW114106343
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-06
- Filing Date
- 2025-02-20
- Publication Date
- 2026-08-16
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
A method for forming a semiconductor structure is provided, which includes following steps. A stacked structure including a floating gate layer, an inter-gate dielectric layer, and a control gate layer stacked on the tunneling oxide material layer in sequence is formed on a tunneling oxide material layer on a substrate. A first spacer material layer is formed on the tunneling oxide material layer to cover a top surface and sidewalls of the stacked structure. A second spacer material layer is formed on the first spacer material layer. A mask pattern is formed on the second spacer material layer and side portions of the second spacer material layer are exposed by the mask pattern. An ion implant process is performed on side portions of the first spacer material layer through the side portions of the second spacer material layer to form first doped regions in the first spacer material layer.
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