A non-volatile memory unit and its memory cell

Abstract

This application relates to a non-volatile memory cell and its memory. The memory cell includes: a first well and a second well of different types arranged adjacent to each other; a first transistor located in the first well, the first transistor including a float gate and its gate oxide; a capacitor located in the second well, the capacitor including a coupling region located in the second well, the float gate and its gate oxide extending from the first well to the second well, constituting the gate of the capacitor and its gate oxide; the float gate includes two electrically different parts, the junction of the two parts forming a PN junction adjacent to one end of the float gate, the distance between the PN junction and the adjacent end of the float gate being less than 150 nm. In the memory cell of this application, the PN junction in the float gate is adjacent to the end of the float gate, which can weaken or eliminate the adverse effects of the PN junction on the float gate, increase the coupling potential obtained by the float gate, improve the uniformity and stability of the coupling potential obtained by the float gate, and help improve the stability and reliability of the memory.

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