Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device of this invention is provided, the semiconductor device includes a circuit substrate, an interposer, a memory stack and a system on chip device. The interposer is bonded to the circuit substrate. The memory stack is bonded to the interposer and electrically connected to the circuit substrate through the interposer. The memory stack includes a plurality of memory dies stacked together. The system on chip device is bonded to the memory stack. The memory stack is located between the system on chip device and the interposer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. [Previous Technology]

[0002] Due to the diminishing economic benefits of Moore's Law, improving manufacturing processes alone is no longer sufficient to optimize the performance of semiconductor devices. The industry has shifted from simply increasing the number of transistors per unit area on a single silicon wafer through process improvements to utilizing complex system-on-a-chip (SoC) designs to enhance the overall performance of semiconductor devices. Among these advancements, chiplet technology has garnered significant attention because it can achieve higher transistor density and performance at a relatively low cost.

[0003] Three-dimensional (3D) packaging is a new semiconductor device design concept that breaks down the numerous components originally contained in a single chip into smaller units, redesigns and remanufactures each unit to enhance its functionality, and finally integrates these smaller units into a single semiconductor device through advanced packaging technology. To increase the number of small chips contained in a semiconductor device, many manufacturers are dedicated to developing technologies that stack multiple small chips together. [Summary of the Invention]

[0004] This invention provides a semiconductor device including a substrate, an interposer, a memory stack layer, and a system-on-a-chip (SoC). The interposer is bonded to the substrate. The memory stack layer is bonded to the interposer and electrically connected to the substrate through the interposer. The memory stack layer includes a plurality of memory dies stacked together. The SoC is bonded to the memory stack layer. The memory stack layer is located between the SoC and the interposer.

[0005] This invention provides a method for manufacturing a semiconductor device, comprising the following steps: Providing a silicon substrate. Forming a first interconnect structure and a first bonding layer on the silicon substrate. Forming a memory stack layer on the first interconnect structure, wherein the memory stack layer is bonded to the first bonding layer, and wherein the memory stack layer includes a plurality of memory chips stacked together. Bonding a system wafer to the memory stack layer, wherein the memory stack layer is located between the system wafer and the silicon substrate. Forming a second interconnect structure and a plurality of connection terminals on a side of the silicon substrate opposite to the first interconnect structure. Electrically connecting the second interconnect structure to the substrate via the plurality of connection terminals.

Implementation Method

[0006] Figures 1A to 1M are schematic cross-sectional views of a method for manufacturing a semiconductor device 1 according to an embodiment of the present invention. Referring to Figure 1A, a silicon substrate 110 is provided. The silicon substrate 110 is, for example, an elemental semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or the like), a compound semiconductor substrate (e.g., a silicon carbide substrate, a gallium arsenide substrate, or the like), or other suitable semiconductor substrates.

[0007] A plurality of conductive vias (e.g., through silicon vias, TSVs) 112 are disposed in a silicon substrate 110 and extend inwardly from a first side 110a of the silicon substrate 110. Each conductive via 112 includes a conductive filler 112A and a buffer layer 112C. Optionally, a liner 112B is included between the conductive filler 112A and the buffer layer 112C. The buffer layer 112C includes titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof. The liner 112B includes a liner, a silicon layer, or other suitable materials. The conductive filler 112A includes copper, tungsten, an alloy of the above metals, or other suitable materials.

[0008] A first interconnect structure 120 is formed on a silicon substrate 110. A conductive via 112 is electrically connected to the first interconnect structure 120. The first interconnect structure 120 includes a dielectric structure 121, a conductive layer 122, and a conductive via 123. The conductive layer 122 and the conductive via 123 are distributed in the dielectric structure 121. The dielectric structure 121 includes one or more insulating layers, the material of which includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other suitable materials or combinations thereof.

[0009] A first bonding layer 130 is formed on the first interconnect structure 120. The first bonding layer 130 includes a dielectric structure 131, metal pads 132, and metal vias 133. The metal pads 132 and metal vias 133 are distributed in the dielectric structure 131. The material of the dielectric structure 131 includes silicon oxide or other suitable materials.

[0010] Referring to Figures 1B to 1H, a memory stack layer MC is formed on the first interconnect structure 120. The memory stack layer MC includes a plurality of memory chips 200, 300, 400, and 500 stacked together. Referring to Figure 1B, an interconnect structure 220 is formed on the first semiconductor substrate 210. A first bonding layer 230 is formed on the interconnect structure 220. The first bonding layer 230 is then bonded to the first bonding layer 130.

[0011] The first semiconductor substrate 210 is, for example, an elemental semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or the like), a compound semiconductor substrate (e.g., a silicon carbide substrate, a gallium arsenide substrate, or the like), or other suitable semiconductor substrate. The first semiconductor substrate 210 includes an array of memory cells 213.

[0012] The interconnect structure 220 is located on a first side 210a of the first semiconductor substrate 210 and is electrically connected to the memory cell 213. The interconnect structure 220 includes a dielectric structure 221, a conductive layer 222, and a conductive via 223. The conductive layer 222 and the conductive via 223 are distributed in the dielectric structure 221. The dielectric structure 221 includes one or more insulating layers, the material of which includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other suitable materials or combinations thereof.

[0013] The first bonding layer 230 includes a dielectric structure 231, metal pads 232, and metal vias 233. The metal pads 232 and metal vias 233 are distributed within the dielectric structure 231. The dielectric structure 231 is made of silicon oxide or other suitable materials. The first bonding layers 130 and 230 are connected to each other via hybrid bonding. Specifically, the metal pads 232 and 132 are connected to each other via metal-to-metal bonding, while the dielectric structure 231 and 131 are connected to each other via dielectric-to-dielectric bonding.

[0014] Referring to FIG1C, the second side 210b of the first semiconductor substrate 210 is ground to reduce its thickness. For example, the thickness of the first semiconductor substrate 210 is reduced by a planarization process such as chemical mechanical planarization (CMP).

[0015] A plurality of conductive vias 212 are formed in the first semiconductor substrate 210. Each conductive via 212 includes a conductive filler 212A and a buffer layer 212C. Optionally, a liner 212B is included between the conductive filler 212A and the buffer layer 212C. The buffer layer 212C includes titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof. The liner 212B includes a liner, a silicon layer, or other suitable materials. The conductive filler 212A includes copper, tungsten, an alloy of the above metals, or other suitable materials.

[0016] The conductive via 212 is formed on the second side 210b of the first semiconductor substrate 210 after the first semiconductor substrate 210 is thinned, but the present invention is not limited thereto. The conductive via 212 is formed on the first side 210a of the first semiconductor substrate 210 before the interconnect structure 220 is formed.

[0017] Referring to FIG. 1D, a second bonding layer 240 is formed on the second side 210b of the first semiconductor substrate 210. The second bonding layer 240 includes a dielectric structure 241, metal pads 242, and metal vias 243. The metal pads 242 and metal vias 243 are distributed in the dielectric structure 241. The material of the dielectric structure 241 includes silicon oxide. At this point, the memory die 200 bonded to the first bonding layer 130 is substantially complete.

[0018] Referring to FIG1E, an interconnect structure 320 is formed on the second semiconductor substrate 310. A first bonding layer 330 is formed on the interconnect structure 320. The first bonding layer 330 is then bonded to the second bonding layer 240.

[0019] The second semiconductor substrate 310 is, for example, an elemental semiconductor substrate (e.g., a silicon substrate, a germanium substrate or the like), a compound semiconductor substrate (e.g., a silicon carbide substrate, a gallium arsenide substrate or the like) or other suitable semiconductor substrate, and the second semiconductor substrate 310 includes an array of memory cells 313.

[0020] The interconnect structure 320 is located on a first side 310a of the second semiconductor substrate 310 and is electrically connected to the memory cell 313. The interconnect structure 320 includes a dielectric structure 321, a conductive layer 322, and a conductive via 323. The conductive layer 322 and the conductive via 323 are distributed in the dielectric structure 321. The dielectric structure 321 includes one or more insulating layers, the material of which includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other suitable materials or combinations thereof.

[0021] The first bonding layer 330 includes a dielectric structure 331, metal pads 332, and metal vias 333. The metal pads 332 and metal vias 333 are distributed in the dielectric structure 331. The material of the dielectric structure 331 includes silicon oxide. The first bonding layer 330 and the second bonding layer 240 are connected to each other by hybrid bonding. Specifically, the metal pads 332 and 242 are connected to each other by metal-to-metal bonding, and the dielectric structure 331 and 241 are connected to each other by dielectric-to-dielectric bonding.

[0022] Referring to FIG1F, the second side 310b of the second semiconductor substrate 310 is ground to reduce its thickness. For example, the thickness of the second semiconductor substrate 310 is reduced by a planarization process such as chemical mechanical planarization (CMP).

[0023] A plurality of conductive vias 312 are formed in the second semiconductor substrate 310. The conductive vias 312 include a conductive filler 312A and a buffer layer 312C. Optionally, a liner 312B is included between the conductive filler 312A and the buffer layer 312C.

[0024] The conductive via 312 is formed on the second side 310b of the second semiconductor substrate 310 after the second semiconductor substrate 310 is thinned, but the present invention is not limited thereto. The conductive via 312 is formed on the first side 310a of the second semiconductor substrate 310 before the interconnect structure 320 is formed.

[0025] Referring to FIG. 1G, a second bonding layer 340 is formed on the second side 310b of the second semiconductor substrate 310. The second bonding layer 340 includes a dielectric structure 341, metal pads 342, and metal vias 343. The metal pads 342 and metal vias 343 are distributed in the dielectric structure 341. The material of the dielectric structure 341 includes silicon oxide or other suitable materials. At this point, the memory die 300 bonded to the memory die 200 is substantially complete.

[0026] Repeat the steps of Figures 1E to 1G to form a memory die 400 on the memory die 300. The memory die 400 includes a third semiconductor substrate 410, an interconnect structure 420, a first bonding layer 430, and a second bonding layer 440. The third semiconductor substrate 410 includes an array of conductive vias 412 and memory cells 413. The first bonding layer 430 of the memory die 400 is bonded to the second bonding layer 340 of the memory die 300 by hybrid bonding.

[0027] Repeat the steps of Figures 1E to 1F to form a fourth semiconductor substrate 510, an interconnect structure 520, and a first bonding layer 530 on the memory die 400. The fourth semiconductor substrate 510 includes an array of conductive vias 512 and memory cells 513. The first bonding layer 530 is bonded to a second bonding layer 440 of the memory die 400 by hybrid bonding.

[0028] An interconnect structure 550 is formed on the second side 510b of the fourth semiconductor substrate 510. The interconnect structure 550 includes a plurality of pads 552.

[0029] The memory stack layer MC includes four memory chips, but the present invention is not limited thereto. The steps of FIG1E to FIG1F are repeated multiple times to make the memory stack layer MC include more memory chips.

[0030] Referring to Figure 1I, the system on chip (SOC) device 600 is bonded to the memory stack layer MC. The memory stack layer MC is located between the system on chip 600 and the silicon substrate 110.

[0031] The system-on-a-chip 600 includes a semiconductor substrate 610 and an interconnect layer 630 located on the semiconductor substrate 610. Connector terminals 660 are formed on the interconnect layer 630, and the system-on-a-chip 600 is bonded to pads 552 of the interconnect structure 550 via the connector terminals 660. The connector terminals 660 are, for example, microbumps or other similar features. The spacing between the connector terminals 660 is 30 micrometers to 60 micrometers.

[0032] Referring to Figure 1J, an underfill material 710 may optionally be formed between the system chip 600 and the memory stack layer MC. The underfill material 710 may be used to protect the connection terminal 660 and fix the system chip 600.

[0033] An encapsulation layer 720 is formed to cover the system-on-a-chip 600. The encapsulation layer 720 laterally surrounds the system-on-a-chip 600. The encapsulation layer 720 is polished to expose the top of the system-on-a-chip 600, but the invention is not limited thereto.

[0034] Referring to FIG1K, a second interconnect structure 150 and a plurality of connection terminals 160 are formed on the side of the silicon substrate 110 opposite to the first interconnect structure 120 (i.e., the second side 110b). The connection terminals 160 are, for example, solder balls. The interposer layer 100 includes the silicon substrate 110, the first interconnect structure 120, the first bonding layer 130, the second interconnect structure 150, and the connection terminals 160. The memory stack layer MC is bonded to the interposer layer 100 and is located between the system chip 600 and the interposer layer 100.

[0035] Next, a dicing process (e.g., a single-segment process) is performed on the encapsulation layer 720, the memory stack layer MC, and the interposer layer 100. After the dicing process, the sidewalls 720s of the encapsulation layer 720, the sidewalls MCs of the memory stack layer MC, and the sidewalls 100s of the interposer layer 100 are aligned. The area of ​​the bottom surface MCb of the memory stack layer MC (i.e., the bottom surface of the first bonding layer 230) is substantially equal to the area of ​​the top surface 100t of the interposer layer 100 (i.e., the top surface of the first bonding layer 130). After the dicing process, the width of the silicon substrate 110 (e.g., the lateral width in FIG. 1K) is substantially equal to the width of at least one of the memory chips 200, 300, 400, and 500.

[0036] Referring to FIG1L, the interposer 100 is electrically connected to the substrate 800. Specifically, the second interconnect structure 150 is electrically connected to the substrate 800 via the connection terminal 160. A connection terminal 810 is formed on the bottom surface of the substrate 800. The connection terminal 810 is, for example, a solder ball.

[0037] Referring to Figure 1M, a thermal interface material layer 910 and a heat dissipation structure 920 can be formed on the system-on-a-chip 600. The thermal interface material layer 910 is located on the top surface of the system-on-a-chip 600. The heat dissipation structure 920 is located on the thermal interface material layer 910. The thermal interface material layer 910 extends from the top surface of the system-on-a-chip 600 to the top surface of the packaging layer 720, and the thermal interface material layer 910 is only located on the top surface of the system-on-a-chip 600.

[0038] Since the system single chip 600 is located above the memory stack layer MC, the system single chip 600 is closer to the heat dissipation structure 920 than the memory stack layer MC. Therefore, the system single chip 600 has a better heat dissipation effect.

[0039] FIG2 is a schematic cross-sectional view of a semiconductor device 2 according to another embodiment of the present invention. The semiconductor device 2 of FIG2 is similar to the semiconductor device 1 of FIG1M, except that: in the semiconductor device 2 of FIG2, the interposer 100 includes an array of passive elements 125 and redundant memory 113.

[0040] Passive element 125 is disposed, for example, in the first interconnect structure 120. Passive element 125 is, for example, a capacitor, an inductor, a resistor, or other passive element. Capacitor is, for example, a cylindrical capacitor, a deep trench capacitor, a metal-insulator-metal (MIM) capacitor, or other types of capacitor.

[0041] Redundant memory 113 can be used to repair memory stack layer MC. For example, if the memory cell of one or more memory chips in memory stack layer MC is found to be damaged during the testing process, redundant memory 113 can be electrically connected to memory stack layer MC through the repair process to replace the damaged memory cell.

[0042] FIG3 is a schematic cross-sectional view of a semiconductor device 3 according to another embodiment of the present invention. The semiconductor device 3 of FIG3 is similar to the semiconductor device 2 of FIG2, except that in the semiconductor device 3 of FIG3, the system single-chip 600 is bonded to the memory stack layer MC by a hybrid bonding process. Specifically, the memory die 500 includes a second bonding layer 550A. The second bonding layer 550A is formed on the second side 510b of the fourth semiconductor substrate 510. The second bonding layer 550A includes a dielectric structure 551 and metal pads 552. The metal pads 552 are distributed in the dielectric structure 551. The material of the dielectric structure 551 includes silicon oxide or other suitable materials.

[0043] The system-on-a-chip 600 includes a bonding layer 670. The bonding layer 670 includes a dielectric structure 671 and metal pads 672. The metal pads 672 are distributed in the dielectric structure 671. In some embodiments, the material of the dielectric structure 671 includes silicon oxide or other suitable materials. The spacing of the metal pads 672 is from 1 micrometer to 9 micrometers.

[0044] Metal pad 672 and metal pad 552 are connected to each other by metal-to-metal bonding, and dielectric structure 671 and dielectric structure 551 are connected to each other by dielectric-to-dielectric bonding.

[0045] FIG4A is a schematic cross-sectional view of a passive element 125 according to an embodiment of the present invention. FIG4B is a schematic cross-sectional view along line a-a' of FIG4A. The passive element 125 shown in FIG4A and FIG4B is disposed, for example, in the interposer layer 100 of FIG2 or FIG3. Referring to FIG4A and FIG4B, the passive element 125 is a cylindrical capacitor and includes a bottom electrode 125a, a dielectric layer 125b, and a top electrode 125c. The dielectric layer 125b is located between the bottom electrode 125a and the top electrode 125c.

[0046] The dielectric structure 121b surrounds the passive element 125 and is a single-layer or multi-layer structure. The conductive layer 122a is located in the dielectric layer 121a and is electrically connected to the bottom electrode 125a. The conductive layer 122b is located in the dielectric layer 121c and is electrically connected to the top electrode 125c.

[0047] In summary, in the semiconductor device of the present invention, the system single chip is bonded to the memory stack layer, and the memory stack layer is located between the system single chip and the interposer layer, thereby improving the heat dissipation efficiency of the system single chip. [Simplified Explanation of the Diagram]

[0048] Figures 1A to 1M are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2 and 3 are schematic cross-sectional views of a semiconductor device according to different embodiments of the present invention. Figure 4A is a schematic cross-sectional view of a passive element according to an embodiment of the present invention. Figure 4B is a schematic cross-sectional view along line a-a' of Figure 4A.

Claims

1. A semiconductor device, comprising: substrate; Intermediate layer, bonded to the substrate; A memory stack layer, bonded to the interposer layer and electrically connected to the substrate through the interposer layer, wherein the memory stack layer includes a plurality of memory dies stacked together, wherein the sidewalls of the memory stack layer are aligned with and continuous with the sidewalls of the interposer layer; and a system chip, bonded to the memory stack layer, wherein the memory stack layer is located between the system chip and the interposer layer.

2. The semiconductor device as claimed in claim 1, wherein the area of ​​the bottom surface of the memory stack layer is substantially equal to the area of ​​the top surface of the interposer layer.

3. The semiconductor device as claimed in claim 1, wherein the interposer layer comprises: A silicon substrate, wherein the width of the silicon substrate is substantially equal to the width of at least one of the plurality of memory chips; And a first interconnect structure located on the first side of the silicon substrate.

4. The semiconductor device as claimed in claim 1, wherein the interposer layer comprises: Silicon substrate; And a first interconnect structure located on a first side of the silicon substrate, wherein the first interconnect structure includes a passive element.

5. The semiconductor device as claimed in claim 1, wherein the interposer layer includes an array of redundant memory.

6. The semiconductor device as claimed in claim 1, further comprising: A thermal interface material layer is located on the top surface of the single wafer of this system; And a heat dissipation structure, located on the thermal interface material layer.

7. The semiconductor device as claimed in claim 1, further comprising: A packaging layer laterally surrounds the system wafer, wherein the sidewalls of the memory stack layer are aligned with the sidewalls of the packaging layer.

8. The semiconductor device as claimed in claim 7, further comprising: A thermal interface material layer extends from the top surface of the single-chip of the system to the top surface of the encapsulation layer; And a heat dissipation structure, located on the thermal interface material layer.

9. A method for manufacturing a semiconductor device, comprising: Silicon substrates are provided; A first interconnect structure and a first bonding layer are formed on the silicon substrate; A memory stack layer is formed on the first interconnect structure, wherein the memory stack layer is bonded to the first bonding layer, and wherein the memory stack layer includes a plurality of memory dies stacked together; a system wafer is bonded to the memory stack layer, wherein the memory stack layer is located between the system wafer and the silicon substrate; a second interconnect structure and a plurality of connection terminals are formed on the side of the silicon substrate opposite to the first interconnect structure, wherein the interposer layer includes the silicon substrate, the first interconnect structure, the first bonding layer, the second interconnect structure, and the plurality of connection terminals; after forming the second interconnect structure, a dicing process is performed on the memory stack layer and the interposer layer to align and make the sidewalls of the memory stack layer and the sidewalls of the interposer layer continuous; and the second interconnect structure is electrically connected to the substrate through the plurality of connection terminals.

10. The manufacturing method of claim 9, further comprising forming a packaging layer laterally around the system wafer before performing the dicing process, wherein after performing the dicing process, the sidewall of the memory stack layer is aligned with the sidewall of the packaging layer.

11. The manufacturing method as claimed in claim 9, wherein the system wafer is bonded to the memory stack layer via a hybrid bonding process.

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