Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a first doped type epitaxial layer, a gate structure, a side shielding layer, a second doped type epitaxial layer, a bottom shielding layer, and a plurality of source regions. The first doped type epitaxial layer is disposed on the substrate. The gate structure is disposed on the first doped type epitaxial layer, in which the gate structure has a stepped profile. The side shielding layer is disposed on one side of the gate structure and the first doped type epitaxial layer. The second doped type epitaxial layer is disposed on the other side of the gate structure and the first doped type epitaxial layer. The bottom shielding layer is disposed under the bottom of the gate structure. The source regions are disposed on both sides of the gate structure and are disposed on the second doped type epitaxial layer and the side shielding layer.

Description

Technical Field

[0001] This disclosure pertains to a semiconductor structure. Prior Technology

[0002] Compared to traditional planar metal-oxide-semiconductor (MOS) devices, where current flows along the plane of the substrate surface, trench-type MOS devices place the gate within a trench, changing the channel position of the MOS device and making the current flow perpendicular to the substrate. This allows for a reduction in device size, increased device efficiency, and ultimately, lower manufacturing costs. Common MOS devices include metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs).

[0003] While costs can be reduced by shrinking device geometry, various trade-offs and challenges must be met when increasing device functionality per unit area. For example, reducing the on-state resistance RonxA relative to the area ratio can affect other device characteristics, such as device reliability that may be limited by high electric fields in trench dielectrics (e.g., gate oxides).

[0004] In view of the above, there is a need to provide a semiconductor structure that can improve electrical properties. Summary of the Invention

[0005] This disclosure provides a semiconductor structure including a substrate, a first-doped epitaxial layer, a gate structure, a side shielding layer, a second-doped epitaxial layer, a bottom shielding layer, and a plurality of source regions. The first-doped epitaxial layer is disposed on the substrate. The gate structure is disposed on the first-doped epitaxial layer, wherein the gate structure has a stepped profile. The side shielding layer is disposed on one side of the gate structure and on the first-doped epitaxial layer. The second-doped epitaxial layer is disposed on the other side of the gate structure and on the first-doped epitaxial layer. The bottom shielding layer is disposed below the bottom of the gate structure. The plurality of source regions are disposed on both sides of the gate structure and are located on the second-doped epitaxial layer and the side shielding layer.

[0006] In some embodiments, the gate structure has a first portion and a second portion located on the first portion, and the bottom width of the second portion is 200 to 1000 angstroms larger than the top width of the first portion.

[0007] In some embodiments, the gate structure includes a gate electrode layer and a gate oxide layer surrounding the gate electrode layer. The gate structure has a first portion and a second portion located on the first portion, and the thickness of the gate oxide layer located on the first portion is greater than the thickness of the gate oxide layer located on the second portion.

[0008] In some embodiments, the gate structure includes a gate electrode layer and a gate oxide layer surrounding the gate electrode layer. The gate oxide layer includes a first gate oxide layer and a second gate oxide layer. The second gate oxide layer is located between the lower part of the gate electrode layer and the first gate oxide layer, and the upper part of the gate electrode layer is in contact with the first gate oxide layer.

[0009] In some embodiments, the top surface of the second gate oxide layer is flush with the bottom surface of the second doped epitaxial layer.

[0010] In some embodiments, the semiconductor structure further includes a first heavily doped epitaxial layer disposed between the first doped epitaxial layer and the second doped epitaxial layer.

[0011] In some implementations, the bottom shielding layer covers multiple bottom corners on both sides of the gate structure.

[0012] In some embodiments, the side shielding layer and the second doped epitaxial layer have the same doping type, and the doping concentration of the side shielding layer is greater than the doping concentration of the second doped epitaxial layer.

[0013] In some implementations, the bottom shielding layer and the second doped epitaxial layer have the same doping type, and the doping concentration of the bottom shielding layer is greater than the doping concentration of the second doped epitaxial layer.

[0014] In some implementations, the side shielding layer is connected to or separated from the bottom shielding layer.

[0015] The semiconductor structure disclosed herein can not only reduce the gate-drain capacitance (C gd) and increase the breakdown voltage (V bd) at the bottom of the gate structure, but also improve the on-resistance (R on) of the semiconductor structure.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are intended to provide further explanation of the claimed content of this disclosure. Simple Explanation of the Diagram

[0017] This disclosure can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings. Figure 1 is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present disclosure. Figure 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure. Implementation

[0018] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0019] The following plurality of embodiments are described and disclosed in detail with reference to the accompanying drawings. For clarity, many practical details will be set forth in the following description. However, it should be understood that these practical details are not intended to limit the scope of this disclosure. That is, these practical details are not essential in some embodiments of this disclosure. Furthermore, for the sake of simplicity, some known structures and elements will be shown schematically in the drawings.

[0020] In this document, the range expressed as "from one value to another" is a concise way of representing a range to avoid listing all the values ​​in that range in the specification. Therefore, the description of a specific range of values ​​covers any value within that range as well as the smaller range of values ​​defined by that value, just as if the arbitrary value and the smaller range of values ​​were explicitly stated in the specification.

[0021] To achieve high-voltage, high-current transistor devices, trench transistors have become a trend in the development of high-power transistor devices due to their lower on-resistance compared to planar transistors. This disclosure provides a semiconductor structure, particularly a trench semiconductor structure, which can not only reduce the gate-drain capacitance (Cgd) and increase the breakdown voltage (Vbd) at the bottom of the gate structure, but also improve the on-resistance (Ron) of the semiconductor structure.

[0022] Figure 1 is a schematic cross-sectional view of a semiconductor structure 10 according to various embodiments of the present disclosure. As shown in Figure 1, the semiconductor structure 10 includes a substrate 100, a first-doped epitaxial layer 110, a gate structure 120, a side shielding layer 130, a second-doped epitaxial layer 140, a bottom shielding layer 150, and a plurality of source regions 160. Specifically, the first-doped epitaxial layer 110 is disposed on the substrate 100.

[0023] In some embodiments, substrate 100 may further include various dopants, such as n-type wells and / or p-type wells formed by ion implantation and / or diffusion. In this embodiment, substrate 100 is a silicon substrate with heavy N-type doping (N+). This silicon substrate with heavy N-type doping serves as the drain of a power metal-oxide-semiconductor field-effect transistor structure. In some embodiments, the first doping type epitaxial layer 110 is, for example, an epitaxial layer with light N-type doping (N-). N+ represents a layer with a higher concentration of N-type impurities, while N- represents a layer with a lower concentration of N-type impurities.

[0024] As shown in Figure 1, a gate structure 120 is disposed on a first doped epitaxial layer 110, and the gate structure 120 has a stepped profile. In some embodiments, the gate structure 120 includes a gate electrode layer 122 and a gate oxide layer 124 surrounding the gate electrode layer 122. Specifically, the gate oxide layer 124 covers the sidewalls and bottom surface of the gate electrode layer 122.

[0025] In this embodiment, the gate oxide layer 124 includes a first gate oxide layer 1241 and a second gate oxide layer 1242, wherein the second gate oxide layer 1242 is located between the lower part of the gate electrode layer 122 and the first gate oxide layer 1241, and the upper part of the gate electrode layer 122 is in direct contact with the first gate oxide layer 1241. In this embodiment, the material of the first gate oxide layer 1241 is different from the material of the second gate oxide layer 1242. Specifically, the first gate oxide layer 1241 includes an insulating oxide, such as silicon dioxide or a high-dielectric insulating oxide material with a dielectric constant of 4 or higher, while the second gate oxide layer 1242 includes an insulating nitride, such as silicon nitride, aluminum nitride, or a high-dielectric insulating nitride material with a dielectric constant of 4 or higher. In some embodiments, the thickness of the first gate oxide layer 1241 is from 650 Å to 350 Å. In some embodiments, the thickness of the second gate oxide layer 1242 is 350 Å to 1650 Å. In this embodiment, the outer wall 1241S of the first gate oxide layer 1241 has a stepped or funnel-shaped profile, which can provide a straighter current path, thereby reducing on-resistance.

[0026] In some embodiments, the gate electrode layer 122 may include a barrier layer, a work function adjustment layer, an adhesion layer, and a host metal layer (such as tungsten, copper, cobalt, ruthenium, etc.). In some embodiments, the gate electrode layer 122 may include a metal or metal alloy layer and / or doped polycrystalline silicon. In other embodiments, a metal silicide may be additionally formed on the doped polycrystalline silicon to reduce the gate resistance.

[0027] In some embodiments, the location of the gate structure can be defined first using a mask pattern (not shown), and trenches (not shown) can be fabricated within the first doped epitaxial layer 110 using dry or wet etching. More specifically, the trenches are strip-shaped trenches extending along the Z direction. In other embodiments, the number of trenches can be multiple, and these trenches are parallel strip-shaped trenches.

[0028] Depending on the etching process used, the sidewalls of the trench can be vertical or angled. In other words, the cross-sectional profile of the trench can be rectangular or trapezoidal. Next, after removing the mask pattern, a gate structure 120 is formed within the trench. Therefore, the gate structure 120 also exhibits a strip-like shape extending along the Z-direction.

[0029] In some embodiments, the gate structure 120 has a first portion 1201 and a second portion 1202 located on the first portion 1201, wherein the bottom width 1202W of the second portion 1202 is 200 Å to 1000 Å greater than the top width 1201W of the first portion 1201. In some embodiments, the thickness of the gate oxide layer 124 located on the first portion 1201 is greater than the thickness of the gate oxide layer 124 located on the second portion 1202.

[0030] It is understood that the first portion 1201 includes only a first gate oxide layer 1241 and a gate electrode layer 122, and the first gate oxide layer 1241 in the first portion 1201 is used as the gate oxide layer of a metal-oxide-semiconductor field-effect transistor (MOSFET), that is, it can be used to form an inversion layer, also known as a conductive channel. In some embodiments, if the thickness of the first gate oxide layer 1241 in the first portion 1201 is greater than a certain value, such as 650 Å, an inversion layer cannot be formed. Conversely, if the thickness of the first gate oxide layer 1241 in the first portion 1201 is less than a certain value, such as 350 Å, gate leakage or gate oxide layer breakdown is likely to occur.

[0031] It is understood that the second portion 1202 includes a first gate oxide layer 1241, a second gate oxide layer 1242, and a gate electrode layer 122. In some embodiments, if the thickness of the first gate oxide layer 1241 and the second gate oxide layer 1242 located in the second portion 1202 is greater than a certain value, such as 2000 Å, it will affect the ability of the subsequent gate electrode layer 122 to fill into the trench. In this embodiment, by thickening the oxide layer at the bottom of the gate structure 120, the gate-drain capacitance (C gd) can be reduced and the breakdown voltage (V bd) at the bottom of the gate structure can be increased.

[0032] Please refer to Figure 1. The side shielding layer 130 is disposed on one side of the gate structure 120 and on the first doped epitaxial layer 110. In some embodiments, after the gate structure 120 is formed, a second doped type (P-type) dopant can be implanted into the first doped type epitaxial layer 110, and a high-temperature process can be applied to diffuse the implanted second doped type (P-type) dopant to form the side shielding layer 130 formed above the first doped type epitaxial layer 110. Although the surface region of the first doped type epitaxial layer 110 contains first doped type (N-type) dopant, the concentration of these N-type dopant is much lower than the implantation concentration of the dopant (P-type) in the side shielding layer 130. Therefore, the presence of these N-type dopant does not affect the formation of the side shielding layer 130.

[0033] Please refer to Figure 1. The second doped epitaxial layer 140 is disposed on the other side of the gate structure 120 and on the first doped epitaxial layer 110. In some embodiments, the bottom of the side shielding layer 130 is lower than the bottom of the second doped epitaxial layer 140. In some embodiments, the top surface of the second gate oxide layer 1242 is flush with the bottom surface of the second doped epitaxial layer 140. In some embodiments, the second doped epitaxial layer 140 can be formed by epitaxial (or epitaxial) growth, thus having good material quality and precise thickness and doping concentration. In this embodiment, the second doped epitaxial layer 140 can be referred to as the P-based region.

[0034] In some embodiments, the side shielding layer 130 and the second-doped epitaxial layer 140 have the same doping type, and the doping concentration of the side shielding layer 130 is greater than or equal to the doping concentration of the second-doped epitaxial layer 140. For example, the doping concentration of the side shielding layer 130 is 1 to 5 times the doping concentration of the second-doped epitaxial layer 140.

[0035] In some embodiments, the semiconductor structure 10 further includes a first heavily doped epitaxial layer 170 disposed between the first doped epitaxial layer 110 and the second doped epitaxial layer 140. In some embodiments, the first heavily doped epitaxial layer 170 and the first doped epitaxial layer 110 have the same doping type, and the doping concentration of the first heavily doped epitaxial layer 170 is greater than the doping concentration of the first doped epitaxial layer 110. By providing the first heavily doped epitaxial layer 170, electrons can diffuse better in all directions of the first doped epitaxial layer 110 after passing through the channel, reducing the conduction current.

[0036] Please refer to Figure 1. A bottom shielding layer 150 is disposed beneath the bottom of the gate structure 120. In some embodiments, the bottom shielding layer 150 covers a plurality of bottom corners on both sides of the gate structure 120. In some embodiments, the bottom shielding layer 150 and the second-doped epitaxial layer 140 have the same doping type, and the doping concentration of the bottom shielding layer 150 is greater than or equal to the doping concentration of the second-doped epitaxial layer 140. For example, the doping concentration of the bottom shielding layer 150 is 1 to 10 times that of the second-doped epitaxial layer 140. In some embodiments, the doping concentration of the bottom shielding layer 150 is less than or equal to the doping concentration of the side shielding layer 130. For example, the doping concentration of the bottom shielding layer 150 is 0.5 to 1 times that of the side shielding layer 130. That is, the side shielding layer 130 can be a P++ doped region and the bottom shielding layer 150 can be a P+ doped region.

[0037] In some embodiments, an ion implantation process can be used to form the bottom shielding layer 150. The bottom shielding layer 150 can shield the electric field at the bottom of the gate structure 120, reduce electric field concentration, and thus improve reliability.

[0038] In some embodiments, the side shielding layer 130 and the bottom shielding layer 150 are spaced apart from each other, as shown in Figure 1. In other words, the side shielding layer 130 and the bottom shielding layer 150 are separated by a first-doped epitaxial layer 110. It can also be understood that the bottom shielding layer 150 is floating, i.e., not electrically connected to the source region 160. In this embodiment, an additional contact pad (not shown) can be electrically connected to the bottom shielding layer 150 to provide a bias voltage to the contact pad, thereby independently adjusting the voltage potential of the bottom shielding layer 150. This improves the on-resistance of the semiconductor structure 20 and increases the breakdown voltage.

[0039] Referring again to Figure 1, a plurality of source regions 160 are disposed on both sides of the gate structure 120, and located on the second doped epitaxial layer 140 and the side shielding layer 130. In some embodiments, these source regions 160 can be formed on both sides of the top of the gate structure 120 using ion implantation. In some embodiments, an interlayer dielectric layer (not shown) can be deposited to cover the gate electrode layer 122 within the gate structure 120, and then a P-type heavily doped region (not shown) can be formed between adjacent source regions 160 (if there are multiple transistor elements) using this interlayer dielectric layer as a mask to improve the avalanche energy resistance of the device. Thus, the fabrication of the semiconductor structure 10 is substantially completed.

[0040] Therefore, it can be understood that the semiconductor structure 10 can be a vertical semiconductor device with load current flowing in a direction perpendicular to the surface of the substrate 100 (i.e., the Y direction). The vertical power semiconductor device can be configured to conduct currents greater than 1 A or even greater than 100 A, and can also be configured to block voltages between load electrodes (e.g., between the drain and source of a MOSFET), said voltages being in the range of several hundred to several thousand volts, for example, 400 V to 10.0 kV. For example, the blocking voltage can correspond to the voltage level specified in the datasheet of the power semiconductor device. The trench-type semiconductor structure 10 can further reduce the on-resistance of the semiconductor structure compared to a planar semiconductor structure.

[0041] Smaller semiconductor structure 10 means a smaller gate structure 120 area, which reduces the equivalent gate capacitance. Furthermore, a smaller gate structure 120 typically has a thinner gate oxide layer 124, which reduces the channel resistance per unit area. However, this change also makes it easier for charge to accumulate at the bottom corners of the gate structure when conducting high currents, potentially even causing the thin gate oxide layer to break down due to quantum tunneling. Therefore, this disclosure increases the thickness of the gate oxide layer 124 (i.e., the first gate oxide layer 1241 and the second gate oxide layer 1242) in the first portion 1201 of the gate structure 120 and simultaneously forms bottom shielding layers 150 at the bottom corners of the gate structure 120 to protect the gate structure 120 and improve the breakdown voltage at the bottom corners.

[0042] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure 20 according to another embodiment of the present disclosure. In order to facilitate comparison with the above embodiments and to simplify the description, the same symbols are used to label the same elements in the following embodiments, and the description mainly focuses on the differences between the embodiments, without repeating the repeated parts.

[0043] The difference between semiconductor structure 20 and semiconductor structure 10 is that the side shielding layer 130 of semiconductor structure 20 is connected to the bottom shielding layer 150. In this embodiment, the region on the right side of the gate structure 120 no longer functions, i.e., it does not form a channel.

[0044] In summary, the semiconductor structure disclosed herein reduces the gate-drain capacitance (C gd) and increases the breakdown voltage (V bd) at the bottom of the gate structure by thickening the oxide layer at the bottom of the gate structure. Furthermore, the semiconductor structure disclosed herein provides a straighter current path, thereby improving the on-resistance (R on) of the semiconductor structure.

[0045] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0046] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended patent applications.

[0047] 10: Semiconductor Structure 100:Substrate 110: First type of doped epitaxial layer 120: Gate structure 1201: Part One 1201W: Top width 1202: Part Two 1202W: Bottom width 122: Gate electrode layer 124: Gate oxide layer 1241: First gate oxide layer 1241S: Lateral wall 1242: Second gate oxide layer 130: Side shielding layer 140: Second type of doped epitaxial layer 150: Bottom shielding layer 160: Source Region 170: First-level doped epitaxial layer 20: Semiconductor Structure X: Direction Y: direction Z: Direction

[0048] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure, comprising: An epitaxial layer of the first doping type is disposed on a substrate; A gate structure is disposed on the first doped epitaxial layer, wherein the gate structure has a stepped profile, wherein the gate structure includes a gate electrode layer and a gate oxide layer surrounding the gate electrode layer, the gate structure has a first portion and a second portion located on the first portion, and the thickness of the gate oxide layer located on the first portion is greater than the thickness of the gate oxide layer located on the second portion; a side shielding layer is disposed on one side of the gate structure and on the first doped epitaxial layer; a second doped epitaxial layer is disposed on the other side of the gate structure and on the first doped epitaxial layer; a bottom shielding layer is disposed at a bottom of the gate structure; and a plurality of source regions are disposed on both sides of the gate structure and located on the second doped epitaxial layer and the side shielding layer.

2. The semiconductor structure as claimed in claim 1, wherein the bottom width of the second portion is 200 to 1000 angstroms greater than the top width of the first portion.

3. The semiconductor structure as described in claim 1 further includes a first heavily doped epitaxial layer disposed between the first doped epitaxial layer and the second doped epitaxial layer.

4. The semiconductor structure as claimed in claim 1, wherein the bottom shielding layer covers a plurality of bottom corners on both sides of the gate structure.

5. The semiconductor structure as claimed in claim 1, wherein the side shielding layer and the second doped epitaxial layer are of the same doping type, and a doping concentration of the side shielding layer is greater than a doping concentration of the second doped epitaxial layer.

6. The semiconductor structure as claimed in claim 1, wherein the bottom shielding layer and the second doped epitaxial layer are of the same doping type, and a doping concentration of the bottom shielding layer is greater than a doping concentration of the second doped epitaxial layer.

7. The semiconductor structure as described in claim 1, wherein the side shielding layer is connected to or separated from the bottom shielding layer.

8. A semiconductor structure, comprising: An epitaxial layer of the first doping type is disposed on a substrate; A gate structure is disposed on the first doped epitaxial layer, wherein the gate structure has a stepped profile, wherein the gate structure includes a gate electrode layer and a gate oxide layer surrounding the gate electrode layer, the gate oxide layer includes a first gate oxide layer and a second gate oxide layer, the second gate oxide layer being located between the lower part of the gate electrode layer and the first gate oxide layer, and an upper part of the gate electrode layer contacting the first gate oxide layer; a side shielding layer is disposed on one side of the gate structure and on the first doped epitaxial layer; a second doped epitaxial layer is disposed on the other side of the gate structure and on the first doped epitaxial layer; a bottom shielding layer is disposed at a bottom of the gate structure; and a plurality of source regions are disposed on both sides of the gate structure and located on the second doped epitaxial layer and the side shielding layer.

9. The semiconductor structure as claimed in claim 8, wherein a top surface of the second gate oxide layer is flush with a bottom surface of the second doped epitaxial layer.

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